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nv_ram_rwsp_4x64_logic.v 53.1 KB
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// nv_ram_rwsp_4x64: synthesizable model core
// Generated by /home/nvtools/branch/release/t194_rg/2017/06/01_10_25_11/nvtools/rams/scripts/ramgen - DO NOT EDIT
// Estimated area: 543.49 um^2 (nvstd_tsmc16fflr)
`ifdef _SIMULATE_X_VH_
`else
`ifndef SYNTHESIS
`define tick_x_or_0 1'bx
`define tick_x_or_1 1'bx
`else
`define tick_x_or_0 1'b0
`define tick_x_or_1 1'b1
`endif
`endif
// verilint 549 off - async flop inferred
// verilint 446 off - reading from output port
// verilint 389 off - multiple clocks in module
// verilint 287 off - unconnected ports
// verilint 401 off - Clock is not an input to the module (we use gated clk)
// verilint 257 off - delays ignored by synth tools
// verilint 240 off - Unused input
// verilint 542 off - enabled flop inferred
// verilint 210 off - too few module ports
// verilint 280 off - delay in non-blocking assignment
// verilint 332 off - not all possible cases covered, but default case exists
// verilint 390 off - multiple resets in this module
// verilint 396 off - flop w/o async reset
// verilint 69 off - case without default, all cases covered
// verilint 34 off - unused macro
// verilint 528 off - variable set but not used
// verilint 530 off - flop inferred
// verilint 550 off - mux inferred
// verilint 113 off - multiple drivers to flop
// leda ELB072 off
`timescale 1ns / 10ps
module nv_ram_rwsp_4x64_logic (
               SI,
               SO_int_net,
               clk,
               debug_mode,
               di,
               dout,
               mbist_ramaccess_rst_,
               ore,
               pwrbus_ram_pd,
               ra,
               re,
               scan_en,
               scan_ramcen,
               shiftDR,
               updateDR,
               wa,
               we
        );
parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
// port list for submodule
input SI;
output SO_int_net;
input clk;
input debug_mode;
input [63:0] di;
output [63:0] dout;
input mbist_ramaccess_rst_;
input ore;
input [31:0] pwrbus_ram_pd;
input [1:0] ra;
input re;
input scan_en;
input scan_ramcen;
input shiftDR;
input updateDR;
input [1:0] wa;
input we;
wire [7:0] sleep_en = pwrbus_ram_pd[7:0];
wire ret_en = pwrbus_ram_pd[8];
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30]));
NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31]));
// DFT ATPG signals
wire la_bist_clkw0;
wire la_bist_clkr0;
assign la_bist_clkr0 = la_bist_clkw0;
wire updateDR_sync;
sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_));
reg updateDR_sync_1p;
always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin
    if (!mbist_ramaccess_rst_)
        updateDR_sync_1p <= 1'b0;
    else
        updateDR_sync_1p <= updateDR_sync;
end
wire debug_mode_sync;
wire dft_rst_gated_clk;
CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en));
sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_));
wire reg_shiftDR = shiftDR;
wire reg_data_shiftDR = reg_shiftDR;
wire [1:0] Ra_array_reg_r0;
// Declare the Data_reg signal beforehand
reg [63:0] Data_reg_r0;
// Data out bus for read port r0 for Output Mux
wire [63:0] r0_OutputMuxDataOut;
CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(debug_mode_sync), .TE(scan_en));
// Write enable bus
wire we_0_0;
// start of predeclareNvregSignals
// Write Data wires for latch array
wire [63:0] Wdata_w0;
wire ctx_ctrl_we;
wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p;
// latch array piece specific gated write clock
wire gated_clk_latch;
CKLNQD12PO4 UJ_clk_gated_w0 (.Q(gated_clk_latch), .CP(clk), .E((we)), .TE(debug_mode_sync | scan_en));
wire shiftDR_en;
wire [1:0] D_Ra_array_reg_r0;
wire [1:0] la_muxedRa_r0;
assign D_Ra_array_reg_r0 = ra;
wire Ra_array_capture_enr0 = ( ((re))) ;
wire muxed_Ra_array_capture_enr0 = !debug_mode_sync & Ra_array_capture_enr0;
wire Ra_to_Wi_so;
wire [1:0]radr_latchq;
assign Ra_array_reg_r0 = radr_latchq ;
assign la_muxedRa_r0 = Ra_array_reg_r0;
// ------------------ START PIECE ----------------------------------
// Suffix : Piece Latch_Array (LatchArray)
// Covers Addresses from 0 to 3 Addressrange: [1:0]
// Data Bit range: [63:0] (64 bits)
// Enables: 1 Enable range:
// Write Address bus
wire [1:0] wa_0_0;
assign wa_0_0 = wa;
// Write Data in bus
wire [63:0] di_0_0;
assign di_0_0 = di[63:0];
assign we_0_0 = we;
// Read Address bus
wire [1:0] ra_0_0;
assign ra_0_0 = la_muxedRa_r0;
// Read DataOut bus
wire [63:0] dout_0_0;
reg [3:0] WA_w0_decode;
always @(wa)
begin
   WA_w0_decode = 4'd0;
   case(wa)
      2'd0 : WA_w0_decode[0] = 1;
      2'd1 : WA_w0_decode[1] = 1;
      2'd2 : WA_w0_decode[2] = 1;
      2'd3 : WA_w0_decode[3] = 1;
   endcase
end
wire [3 : 0 ] muxed_Wa_decode_w0 = WA_w0_decode[3 : 0] & {4{we}} & {4{!debug_mode}};
wire [3 : 0 ] muxed_Wa_decode_common = muxed_Wa_decode_w0 ;
wire latchInst_qg_row0_w0EN_r0;
assign latchInst_qg_row0_w0EN_r0 = muxed_Wa_decode_common[0] & !debug_mode_sync & !scan_ramcen;
wire latchNet_G_en0;
SCKLNQD2PO4 latchInst_qg_row0_w0 (.Q(latchNet_G_en0), .CP(gated_clk_latch), .E(latchInst_qg_row0_w0EN_r0), .SE(1'b0), .SI(1'b0), .SO());
wire latchInst_qg_row1_w0EN_r1;
assign latchInst_qg_row1_w0EN_r1 = muxed_Wa_decode_common[1] & !debug_mode_sync & !scan_ramcen;
wire latchNet_G_en1;
SCKLNQD2PO4 latchInst_qg_row1_w0 (.Q(latchNet_G_en1), .CP(gated_clk_latch), .E(latchInst_qg_row1_w0EN_r1), .SE(1'b0), .SI(1'b0), .SO());
wire latchInst_qg_row2_w0EN_r2;
assign latchInst_qg_row2_w0EN_r2 = muxed_Wa_decode_common[2] & !debug_mode_sync & !scan_ramcen;
wire latchNet_G_en2;
SCKLNQD2PO4 latchInst_qg_row2_w0 (.Q(latchNet_G_en2), .CP(gated_clk_latch), .E(latchInst_qg_row2_w0EN_r2), .SE(1'b0), .SI(1'b0), .SO());
wire latchInst_qg_row3_w0EN_r3;
assign latchInst_qg_row3_w0EN_r3 = muxed_Wa_decode_common[3] & !debug_mode_sync & !scan_ramcen;
wire latchNet_G_en3;
SCKLNQD2PO4 latchInst_qg_row3_w0 (.Q(latchNet_G_en3), .CP(gated_clk_latch), .E(latchInst_qg_row3_w0EN_r3), .SE(1'b0), .SI(1'b0), .SO());
// Declare the SI and SO signals for this piece
wire SO_0_0;
reg [63:0] RaDecodeDor0;
wire [63:0] LatchArray_row0;
wire [63:0] LatchArray_row1;
wire [63:0] LatchArray_row2;
wire [63:0] LatchArray_row3;
// Register to hold the input data for port w0
wire [63:0] bist_Wdata_w0_reg_d = RaDecodeDor0;
wire [63:0] Wdata_w0_reg_d;
assign Wdata_w0_reg_d = (debug_mode_sync) ? bist_Wdata_w0_reg_d : di_0_0;
wire wdata_w0_scanin = Ra_to_Wi_so;
// testInst_Wdata_reg for latch array only
wire [63:0]wd_q;
assign Wdata_w0 = wd_q ;
wire [63:0] Wdata_row0 = Wdata_w0 ;
wire [63:0] Wdata_row1 = Wdata_w0 ;
wire [63:0] Wdata_row2 = Wdata_w0 ;
wire [63:0] Wdata_row3 = Wdata_w0 ;
LHQLPD1PO4 latchInst_latch_bit0_row0 (
                   .Q(LatchArray_row0[0]),
                   .D(Wdata_row0[0]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit0_row1 (
                   .Q(LatchArray_row1[0]),
                   .D(Wdata_row1[0]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit0_row2 (
                   .Q(LatchArray_row2[0]),
                   .D(Wdata_row2[0]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit0_row3 (
                   .Q(LatchArray_row3[0]),
                   .D(Wdata_row3[0]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit1_row0 (
                   .Q(LatchArray_row0[1]),
                   .D(Wdata_row0[1]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit1_row1 (
                   .Q(LatchArray_row1[1]),
                   .D(Wdata_row1[1]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit1_row2 (
                   .Q(LatchArray_row2[1]),
                   .D(Wdata_row2[1]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit1_row3 (
                   .Q(LatchArray_row3[1]),
                   .D(Wdata_row3[1]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit2_row0 (
                   .Q(LatchArray_row0[2]),
                   .D(Wdata_row0[2]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit2_row1 (
                   .Q(LatchArray_row1[2]),
                   .D(Wdata_row1[2]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit2_row2 (
                   .Q(LatchArray_row2[2]),
                   .D(Wdata_row2[2]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit2_row3 (
                   .Q(LatchArray_row3[2]),
                   .D(Wdata_row3[2]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit3_row0 (
                   .Q(LatchArray_row0[3]),
                   .D(Wdata_row0[3]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit3_row1 (
                   .Q(LatchArray_row1[3]),
                   .D(Wdata_row1[3]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit3_row2 (
                   .Q(LatchArray_row2[3]),
                   .D(Wdata_row2[3]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit3_row3 (
                   .Q(LatchArray_row3[3]),
                   .D(Wdata_row3[3]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit4_row0 (
                   .Q(LatchArray_row0[4]),
                   .D(Wdata_row0[4]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit4_row1 (
                   .Q(LatchArray_row1[4]),
                   .D(Wdata_row1[4]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit4_row2 (
                   .Q(LatchArray_row2[4]),
                   .D(Wdata_row2[4]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit4_row3 (
                   .Q(LatchArray_row3[4]),
                   .D(Wdata_row3[4]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit5_row0 (
                   .Q(LatchArray_row0[5]),
                   .D(Wdata_row0[5]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit5_row1 (
                   .Q(LatchArray_row1[5]),
                   .D(Wdata_row1[5]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit5_row2 (
                   .Q(LatchArray_row2[5]),
                   .D(Wdata_row2[5]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit5_row3 (
                   .Q(LatchArray_row3[5]),
                   .D(Wdata_row3[5]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit6_row0 (
                   .Q(LatchArray_row0[6]),
                   .D(Wdata_row0[6]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit6_row1 (
                   .Q(LatchArray_row1[6]),
                   .D(Wdata_row1[6]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit6_row2 (
                   .Q(LatchArray_row2[6]),
                   .D(Wdata_row2[6]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit6_row3 (
                   .Q(LatchArray_row3[6]),
                   .D(Wdata_row3[6]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit7_row0 (
                   .Q(LatchArray_row0[7]),
                   .D(Wdata_row0[7]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit7_row1 (
                   .Q(LatchArray_row1[7]),
                   .D(Wdata_row1[7]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit7_row2 (
                   .Q(LatchArray_row2[7]),
                   .D(Wdata_row2[7]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit7_row3 (
                   .Q(LatchArray_row3[7]),
                   .D(Wdata_row3[7]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit8_row0 (
                   .Q(LatchArray_row0[8]),
                   .D(Wdata_row0[8]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit8_row1 (
                   .Q(LatchArray_row1[8]),
                   .D(Wdata_row1[8]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit8_row2 (
                   .Q(LatchArray_row2[8]),
                   .D(Wdata_row2[8]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit8_row3 (
                   .Q(LatchArray_row3[8]),
                   .D(Wdata_row3[8]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit9_row0 (
                   .Q(LatchArray_row0[9]),
                   .D(Wdata_row0[9]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit9_row1 (
                   .Q(LatchArray_row1[9]),
                   .D(Wdata_row1[9]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit9_row2 (
                   .Q(LatchArray_row2[9]),
                   .D(Wdata_row2[9]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit9_row3 (
                   .Q(LatchArray_row3[9]),
                   .D(Wdata_row3[9]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit10_row0 (
                   .Q(LatchArray_row0[10]),
                   .D(Wdata_row0[10]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit10_row1 (
                   .Q(LatchArray_row1[10]),
                   .D(Wdata_row1[10]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit10_row2 (
                   .Q(LatchArray_row2[10]),
                   .D(Wdata_row2[10]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit10_row3 (
                   .Q(LatchArray_row3[10]),
                   .D(Wdata_row3[10]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit11_row0 (
                   .Q(LatchArray_row0[11]),
                   .D(Wdata_row0[11]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit11_row1 (
                   .Q(LatchArray_row1[11]),
                   .D(Wdata_row1[11]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit11_row2 (
                   .Q(LatchArray_row2[11]),
                   .D(Wdata_row2[11]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit11_row3 (
                   .Q(LatchArray_row3[11]),
                   .D(Wdata_row3[11]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit12_row0 (
                   .Q(LatchArray_row0[12]),
                   .D(Wdata_row0[12]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit12_row1 (
                   .Q(LatchArray_row1[12]),
                   .D(Wdata_row1[12]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit12_row2 (
                   .Q(LatchArray_row2[12]),
                   .D(Wdata_row2[12]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit12_row3 (
                   .Q(LatchArray_row3[12]),
                   .D(Wdata_row3[12]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit13_row0 (
                   .Q(LatchArray_row0[13]),
                   .D(Wdata_row0[13]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit13_row1 (
                   .Q(LatchArray_row1[13]),
                   .D(Wdata_row1[13]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit13_row2 (
                   .Q(LatchArray_row2[13]),
                   .D(Wdata_row2[13]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit13_row3 (
                   .Q(LatchArray_row3[13]),
                   .D(Wdata_row3[13]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit14_row0 (
                   .Q(LatchArray_row0[14]),
                   .D(Wdata_row0[14]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit14_row1 (
                   .Q(LatchArray_row1[14]),
                   .D(Wdata_row1[14]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit14_row2 (
                   .Q(LatchArray_row2[14]),
                   .D(Wdata_row2[14]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit14_row3 (
                   .Q(LatchArray_row3[14]),
                   .D(Wdata_row3[14]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit15_row0 (
                   .Q(LatchArray_row0[15]),
                   .D(Wdata_row0[15]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit15_row1 (
                   .Q(LatchArray_row1[15]),
                   .D(Wdata_row1[15]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit15_row2 (
                   .Q(LatchArray_row2[15]),
                   .D(Wdata_row2[15]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit15_row3 (
                   .Q(LatchArray_row3[15]),
                   .D(Wdata_row3[15]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit16_row0 (
                   .Q(LatchArray_row0[16]),
                   .D(Wdata_row0[16]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit16_row1 (
                   .Q(LatchArray_row1[16]),
                   .D(Wdata_row1[16]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit16_row2 (
                   .Q(LatchArray_row2[16]),
                   .D(Wdata_row2[16]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit16_row3 (
                   .Q(LatchArray_row3[16]),
                   .D(Wdata_row3[16]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit17_row0 (
                   .Q(LatchArray_row0[17]),
                   .D(Wdata_row0[17]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit17_row1 (
                   .Q(LatchArray_row1[17]),
                   .D(Wdata_row1[17]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit17_row2 (
                   .Q(LatchArray_row2[17]),
                   .D(Wdata_row2[17]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit17_row3 (
                   .Q(LatchArray_row3[17]),
                   .D(Wdata_row3[17]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit18_row0 (
                   .Q(LatchArray_row0[18]),
                   .D(Wdata_row0[18]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit18_row1 (
                   .Q(LatchArray_row1[18]),
                   .D(Wdata_row1[18]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit18_row2 (
                   .Q(LatchArray_row2[18]),
                   .D(Wdata_row2[18]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit18_row3 (
                   .Q(LatchArray_row3[18]),
                   .D(Wdata_row3[18]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit19_row0 (
                   .Q(LatchArray_row0[19]),
                   .D(Wdata_row0[19]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit19_row1 (
                   .Q(LatchArray_row1[19]),
                   .D(Wdata_row1[19]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit19_row2 (
                   .Q(LatchArray_row2[19]),
                   .D(Wdata_row2[19]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit19_row3 (
                   .Q(LatchArray_row3[19]),
                   .D(Wdata_row3[19]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit20_row0 (
                   .Q(LatchArray_row0[20]),
                   .D(Wdata_row0[20]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit20_row1 (
                   .Q(LatchArray_row1[20]),
                   .D(Wdata_row1[20]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit20_row2 (
                   .Q(LatchArray_row2[20]),
                   .D(Wdata_row2[20]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit20_row3 (
                   .Q(LatchArray_row3[20]),
                   .D(Wdata_row3[20]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit21_row0 (
                   .Q(LatchArray_row0[21]),
                   .D(Wdata_row0[21]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit21_row1 (
                   .Q(LatchArray_row1[21]),
                   .D(Wdata_row1[21]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit21_row2 (
                   .Q(LatchArray_row2[21]),
                   .D(Wdata_row2[21]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit21_row3 (
                   .Q(LatchArray_row3[21]),
                   .D(Wdata_row3[21]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit22_row0 (
                   .Q(LatchArray_row0[22]),
                   .D(Wdata_row0[22]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit22_row1 (
                   .Q(LatchArray_row1[22]),
                   .D(Wdata_row1[22]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit22_row2 (
                   .Q(LatchArray_row2[22]),
                   .D(Wdata_row2[22]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit22_row3 (
                   .Q(LatchArray_row3[22]),
                   .D(Wdata_row3[22]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit23_row0 (
                   .Q(LatchArray_row0[23]),
                   .D(Wdata_row0[23]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit23_row1 (
                   .Q(LatchArray_row1[23]),
                   .D(Wdata_row1[23]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit23_row2 (
                   .Q(LatchArray_row2[23]),
                   .D(Wdata_row2[23]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit23_row3 (
                   .Q(LatchArray_row3[23]),
                   .D(Wdata_row3[23]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit24_row0 (
                   .Q(LatchArray_row0[24]),
                   .D(Wdata_row0[24]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit24_row1 (
                   .Q(LatchArray_row1[24]),
                   .D(Wdata_row1[24]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit24_row2 (
                   .Q(LatchArray_row2[24]),
                   .D(Wdata_row2[24]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit24_row3 (
                   .Q(LatchArray_row3[24]),
                   .D(Wdata_row3[24]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit25_row0 (
                   .Q(LatchArray_row0[25]),
                   .D(Wdata_row0[25]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit25_row1 (
                   .Q(LatchArray_row1[25]),
                   .D(Wdata_row1[25]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit25_row2 (
                   .Q(LatchArray_row2[25]),
                   .D(Wdata_row2[25]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit25_row3 (
                   .Q(LatchArray_row3[25]),
                   .D(Wdata_row3[25]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit26_row0 (
                   .Q(LatchArray_row0[26]),
                   .D(Wdata_row0[26]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit26_row1 (
                   .Q(LatchArray_row1[26]),
                   .D(Wdata_row1[26]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit26_row2 (
                   .Q(LatchArray_row2[26]),
                   .D(Wdata_row2[26]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit26_row3 (
                   .Q(LatchArray_row3[26]),
                   .D(Wdata_row3[26]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit27_row0 (
                   .Q(LatchArray_row0[27]),
                   .D(Wdata_row0[27]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit27_row1 (
                   .Q(LatchArray_row1[27]),
                   .D(Wdata_row1[27]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit27_row2 (
                   .Q(LatchArray_row2[27]),
                   .D(Wdata_row2[27]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit27_row3 (
                   .Q(LatchArray_row3[27]),
                   .D(Wdata_row3[27]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit28_row0 (
                   .Q(LatchArray_row0[28]),
                   .D(Wdata_row0[28]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit28_row1 (
                   .Q(LatchArray_row1[28]),
                   .D(Wdata_row1[28]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit28_row2 (
                   .Q(LatchArray_row2[28]),
                   .D(Wdata_row2[28]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit28_row3 (
                   .Q(LatchArray_row3[28]),
                   .D(Wdata_row3[28]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit29_row0 (
                   .Q(LatchArray_row0[29]),
                   .D(Wdata_row0[29]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit29_row1 (
                   .Q(LatchArray_row1[29]),
                   .D(Wdata_row1[29]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit29_row2 (
                   .Q(LatchArray_row2[29]),
                   .D(Wdata_row2[29]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit29_row3 (
                   .Q(LatchArray_row3[29]),
                   .D(Wdata_row3[29]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit30_row0 (
                   .Q(LatchArray_row0[30]),
                   .D(Wdata_row0[30]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit30_row1 (
                   .Q(LatchArray_row1[30]),
                   .D(Wdata_row1[30]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit30_row2 (
                   .Q(LatchArray_row2[30]),
                   .D(Wdata_row2[30]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit30_row3 (
                   .Q(LatchArray_row3[30]),
                   .D(Wdata_row3[30]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit31_row0 (
                   .Q(LatchArray_row0[31]),
                   .D(Wdata_row0[31]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit31_row1 (
                   .Q(LatchArray_row1[31]),
                   .D(Wdata_row1[31]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit31_row2 (
                   .Q(LatchArray_row2[31]),
                   .D(Wdata_row2[31]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit31_row3 (
                   .Q(LatchArray_row3[31]),
                   .D(Wdata_row3[31]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit32_row0 (
                   .Q(LatchArray_row0[32]),
                   .D(Wdata_row0[32]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit32_row1 (
                   .Q(LatchArray_row1[32]),
                   .D(Wdata_row1[32]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit32_row2 (
                   .Q(LatchArray_row2[32]),
                   .D(Wdata_row2[32]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit32_row3 (
                   .Q(LatchArray_row3[32]),
                   .D(Wdata_row3[32]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit33_row0 (
                   .Q(LatchArray_row0[33]),
                   .D(Wdata_row0[33]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit33_row1 (
                   .Q(LatchArray_row1[33]),
                   .D(Wdata_row1[33]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit33_row2 (
                   .Q(LatchArray_row2[33]),
                   .D(Wdata_row2[33]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit33_row3 (
                   .Q(LatchArray_row3[33]),
                   .D(Wdata_row3[33]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit34_row0 (
                   .Q(LatchArray_row0[34]),
                   .D(Wdata_row0[34]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit34_row1 (
                   .Q(LatchArray_row1[34]),
                   .D(Wdata_row1[34]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit34_row2 (
                   .Q(LatchArray_row2[34]),
                   .D(Wdata_row2[34]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit34_row3 (
                   .Q(LatchArray_row3[34]),
                   .D(Wdata_row3[34]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit35_row0 (
                   .Q(LatchArray_row0[35]),
                   .D(Wdata_row0[35]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit35_row1 (
                   .Q(LatchArray_row1[35]),
                   .D(Wdata_row1[35]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit35_row2 (
                   .Q(LatchArray_row2[35]),
                   .D(Wdata_row2[35]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit35_row3 (
                   .Q(LatchArray_row3[35]),
                   .D(Wdata_row3[35]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit36_row0 (
                   .Q(LatchArray_row0[36]),
                   .D(Wdata_row0[36]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit36_row1 (
                   .Q(LatchArray_row1[36]),
                   .D(Wdata_row1[36]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit36_row2 (
                   .Q(LatchArray_row2[36]),
                   .D(Wdata_row2[36]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit36_row3 (
                   .Q(LatchArray_row3[36]),
                   .D(Wdata_row3[36]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit37_row0 (
                   .Q(LatchArray_row0[37]),
                   .D(Wdata_row0[37]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit37_row1 (
                   .Q(LatchArray_row1[37]),
                   .D(Wdata_row1[37]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit37_row2 (
                   .Q(LatchArray_row2[37]),
                   .D(Wdata_row2[37]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit37_row3 (
                   .Q(LatchArray_row3[37]),
                   .D(Wdata_row3[37]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit38_row0 (
                   .Q(LatchArray_row0[38]),
                   .D(Wdata_row0[38]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit38_row1 (
                   .Q(LatchArray_row1[38]),
                   .D(Wdata_row1[38]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit38_row2 (
                   .Q(LatchArray_row2[38]),
                   .D(Wdata_row2[38]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit38_row3 (
                   .Q(LatchArray_row3[38]),
                   .D(Wdata_row3[38]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit39_row0 (
                   .Q(LatchArray_row0[39]),
                   .D(Wdata_row0[39]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit39_row1 (
                   .Q(LatchArray_row1[39]),
                   .D(Wdata_row1[39]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit39_row2 (
                   .Q(LatchArray_row2[39]),
                   .D(Wdata_row2[39]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit39_row3 (
                   .Q(LatchArray_row3[39]),
                   .D(Wdata_row3[39]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit40_row0 (
                   .Q(LatchArray_row0[40]),
                   .D(Wdata_row0[40]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit40_row1 (
                   .Q(LatchArray_row1[40]),
                   .D(Wdata_row1[40]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit40_row2 (
                   .Q(LatchArray_row2[40]),
                   .D(Wdata_row2[40]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit40_row3 (
                   .Q(LatchArray_row3[40]),
                   .D(Wdata_row3[40]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit41_row0 (
                   .Q(LatchArray_row0[41]),
                   .D(Wdata_row0[41]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit41_row1 (
                   .Q(LatchArray_row1[41]),
                   .D(Wdata_row1[41]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit41_row2 (
                   .Q(LatchArray_row2[41]),
                   .D(Wdata_row2[41]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit41_row3 (
                   .Q(LatchArray_row3[41]),
                   .D(Wdata_row3[41]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit42_row0 (
                   .Q(LatchArray_row0[42]),
                   .D(Wdata_row0[42]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit42_row1 (
                   .Q(LatchArray_row1[42]),
                   .D(Wdata_row1[42]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit42_row2 (
                   .Q(LatchArray_row2[42]),
                   .D(Wdata_row2[42]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit42_row3 (
                   .Q(LatchArray_row3[42]),
                   .D(Wdata_row3[42]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit43_row0 (
                   .Q(LatchArray_row0[43]),
                   .D(Wdata_row0[43]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit43_row1 (
                   .Q(LatchArray_row1[43]),
                   .D(Wdata_row1[43]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit43_row2 (
                   .Q(LatchArray_row2[43]),
                   .D(Wdata_row2[43]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit43_row3 (
                   .Q(LatchArray_row3[43]),
                   .D(Wdata_row3[43]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit44_row0 (
                   .Q(LatchArray_row0[44]),
                   .D(Wdata_row0[44]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit44_row1 (
                   .Q(LatchArray_row1[44]),
                   .D(Wdata_row1[44]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit44_row2 (
                   .Q(LatchArray_row2[44]),
                   .D(Wdata_row2[44]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit44_row3 (
                   .Q(LatchArray_row3[44]),
                   .D(Wdata_row3[44]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit45_row0 (
                   .Q(LatchArray_row0[45]),
                   .D(Wdata_row0[45]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit45_row1 (
                   .Q(LatchArray_row1[45]),
                   .D(Wdata_row1[45]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit45_row2 (
                   .Q(LatchArray_row2[45]),
                   .D(Wdata_row2[45]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit45_row3 (
                   .Q(LatchArray_row3[45]),
                   .D(Wdata_row3[45]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit46_row0 (
                   .Q(LatchArray_row0[46]),
                   .D(Wdata_row0[46]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit46_row1 (
                   .Q(LatchArray_row1[46]),
                   .D(Wdata_row1[46]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit46_row2 (
                   .Q(LatchArray_row2[46]),
                   .D(Wdata_row2[46]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit46_row3 (
                   .Q(LatchArray_row3[46]),
                   .D(Wdata_row3[46]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit47_row0 (
                   .Q(LatchArray_row0[47]),
                   .D(Wdata_row0[47]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit47_row1 (
                   .Q(LatchArray_row1[47]),
                   .D(Wdata_row1[47]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit47_row2 (
                   .Q(LatchArray_row2[47]),
                   .D(Wdata_row2[47]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit47_row3 (
                   .Q(LatchArray_row3[47]),
                   .D(Wdata_row3[47]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit48_row0 (
                   .Q(LatchArray_row0[48]),
                   .D(Wdata_row0[48]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit48_row1 (
                   .Q(LatchArray_row1[48]),
                   .D(Wdata_row1[48]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit48_row2 (
                   .Q(LatchArray_row2[48]),
                   .D(Wdata_row2[48]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit48_row3 (
                   .Q(LatchArray_row3[48]),
                   .D(Wdata_row3[48]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit49_row0 (
                   .Q(LatchArray_row0[49]),
                   .D(Wdata_row0[49]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit49_row1 (
                   .Q(LatchArray_row1[49]),
                   .D(Wdata_row1[49]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit49_row2 (
                   .Q(LatchArray_row2[49]),
                   .D(Wdata_row2[49]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit49_row3 (
                   .Q(LatchArray_row3[49]),
                   .D(Wdata_row3[49]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit50_row0 (
                   .Q(LatchArray_row0[50]),
                   .D(Wdata_row0[50]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit50_row1 (
                   .Q(LatchArray_row1[50]),
                   .D(Wdata_row1[50]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit50_row2 (
                   .Q(LatchArray_row2[50]),
                   .D(Wdata_row2[50]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit50_row3 (
                   .Q(LatchArray_row3[50]),
                   .D(Wdata_row3[50]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit51_row0 (
                   .Q(LatchArray_row0[51]),
                   .D(Wdata_row0[51]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit51_row1 (
                   .Q(LatchArray_row1[51]),
                   .D(Wdata_row1[51]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit51_row2 (
                   .Q(LatchArray_row2[51]),
                   .D(Wdata_row2[51]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit51_row3 (
                   .Q(LatchArray_row3[51]),
                   .D(Wdata_row3[51]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit52_row0 (
                   .Q(LatchArray_row0[52]),
                   .D(Wdata_row0[52]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit52_row1 (
                   .Q(LatchArray_row1[52]),
                   .D(Wdata_row1[52]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit52_row2 (
                   .Q(LatchArray_row2[52]),
                   .D(Wdata_row2[52]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit52_row3 (
                   .Q(LatchArray_row3[52]),
                   .D(Wdata_row3[52]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit53_row0 (
                   .Q(LatchArray_row0[53]),
                   .D(Wdata_row0[53]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit53_row1 (
                   .Q(LatchArray_row1[53]),
                   .D(Wdata_row1[53]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit53_row2 (
                   .Q(LatchArray_row2[53]),
                   .D(Wdata_row2[53]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit53_row3 (
                   .Q(LatchArray_row3[53]),
                   .D(Wdata_row3[53]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit54_row0 (
                   .Q(LatchArray_row0[54]),
                   .D(Wdata_row0[54]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit54_row1 (
                   .Q(LatchArray_row1[54]),
                   .D(Wdata_row1[54]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit54_row2 (
                   .Q(LatchArray_row2[54]),
                   .D(Wdata_row2[54]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit54_row3 (
                   .Q(LatchArray_row3[54]),
                   .D(Wdata_row3[54]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit55_row0 (
                   .Q(LatchArray_row0[55]),
                   .D(Wdata_row0[55]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit55_row1 (
                   .Q(LatchArray_row1[55]),
                   .D(Wdata_row1[55]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit55_row2 (
                   .Q(LatchArray_row2[55]),
                   .D(Wdata_row2[55]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit55_row3 (
                   .Q(LatchArray_row3[55]),
                   .D(Wdata_row3[55]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit56_row0 (
                   .Q(LatchArray_row0[56]),
                   .D(Wdata_row0[56]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit56_row1 (
                   .Q(LatchArray_row1[56]),
                   .D(Wdata_row1[56]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit56_row2 (
                   .Q(LatchArray_row2[56]),
                   .D(Wdata_row2[56]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit56_row3 (
                   .Q(LatchArray_row3[56]),
                   .D(Wdata_row3[56]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit57_row0 (
                   .Q(LatchArray_row0[57]),
                   .D(Wdata_row0[57]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit57_row1 (
                   .Q(LatchArray_row1[57]),
                   .D(Wdata_row1[57]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit57_row2 (
                   .Q(LatchArray_row2[57]),
                   .D(Wdata_row2[57]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit57_row3 (
                   .Q(LatchArray_row3[57]),
                   .D(Wdata_row3[57]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit58_row0 (
                   .Q(LatchArray_row0[58]),
                   .D(Wdata_row0[58]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit58_row1 (
                   .Q(LatchArray_row1[58]),
                   .D(Wdata_row1[58]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit58_row2 (
                   .Q(LatchArray_row2[58]),
                   .D(Wdata_row2[58]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit58_row3 (
                   .Q(LatchArray_row3[58]),
                   .D(Wdata_row3[58]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit59_row0 (
                   .Q(LatchArray_row0[59]),
                   .D(Wdata_row0[59]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit59_row1 (
                   .Q(LatchArray_row1[59]),
                   .D(Wdata_row1[59]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit59_row2 (
                   .Q(LatchArray_row2[59]),
                   .D(Wdata_row2[59]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit59_row3 (
                   .Q(LatchArray_row3[59]),
                   .D(Wdata_row3[59]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit60_row0 (
                   .Q(LatchArray_row0[60]),
                   .D(Wdata_row0[60]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit60_row1 (
                   .Q(LatchArray_row1[60]),
                   .D(Wdata_row1[60]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit60_row2 (
                   .Q(LatchArray_row2[60]),
                   .D(Wdata_row2[60]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit60_row3 (
                   .Q(LatchArray_row3[60]),
                   .D(Wdata_row3[60]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit61_row0 (
                   .Q(LatchArray_row0[61]),
                   .D(Wdata_row0[61]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit61_row1 (
                   .Q(LatchArray_row1[61]),
                   .D(Wdata_row1[61]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit61_row2 (
                   .Q(LatchArray_row2[61]),
                   .D(Wdata_row2[61]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit61_row3 (
                   .Q(LatchArray_row3[61]),
                   .D(Wdata_row3[61]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit62_row0 (
                   .Q(LatchArray_row0[62]),
                   .D(Wdata_row0[62]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit62_row1 (
                   .Q(LatchArray_row1[62]),
                   .D(Wdata_row1[62]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit62_row2 (
                   .Q(LatchArray_row2[62]),
                   .D(Wdata_row2[62]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit62_row3 (
                   .Q(LatchArray_row3[62]),
                   .D(Wdata_row3[62]),
                   .E(latchNet_G_en3));
LHQLPD1PO4 latchInst_latch_bit63_row0 (
                   .Q(LatchArray_row0[63]),
                   .D(Wdata_row0[63]),
                   .E(latchNet_G_en0));
LHQLPD1PO4 latchInst_latch_bit63_row1 (
                   .Q(LatchArray_row1[63]),
                   .D(Wdata_row1[63]),
                   .E(latchNet_G_en1));
LHQLPD1PO4 latchInst_latch_bit63_row2 (
                   .Q(LatchArray_row2[63]),
                   .D(Wdata_row2[63]),
                   .E(latchNet_G_en2));
LHQLPD1PO4 latchInst_latch_bit63_row3 (
                   .Q(LatchArray_row3[63]),
                   .D(Wdata_row3[63]),
                   .E(latchNet_G_en3));
// Declare the Do buses for data out.
// Do Ra decode
always @(ra_0_0 or LatchArray_row0 or LatchArray_row1 or LatchArray_row2 or
         LatchArray_row3)
// verilint 332 off - not all cases covered, default exists
   case(ra_0_0)
       2'd0 : RaDecodeDor0 = LatchArray_row0;
       2'd1 : RaDecodeDor0 = LatchArray_row1;
       2'd2 : RaDecodeDor0 = LatchArray_row2;
       2'd3 : RaDecodeDor0 = LatchArray_row3;
       default :RaDecodeDor0 = {64{`tick_x_or_0}};
    endcase
// verilint 332 on
assign dout_0_0 = RaDecodeDor0;
//------------ Done generating latch array Latch_Array -------------
// ---------------------------------------------
// Declare the interface wires for Output Mux logic
// verilint 552 off - Different bits of a net are driven in different blocks (harmless,
// but some synthesis tools generate a warning for this)
reg [63:0] ram_r0_OutputMuxDataOut;
//For bitEnd 63, only one piece Latch_Array in the column.
// verilint 17 off - Range (rather than full vector) in the sensitivity list
always @(dout_0_0)
begin
    ram_r0_OutputMuxDataOut[63:0] = dout_0_0;
end
assign r0_OutputMuxDataOut[63:0] = ram_r0_OutputMuxDataOut[63:0];
// verilint 17 on - Range (rather than full vector) in the sensitivity list
// --------------------- Output Mbist Interface logic -------------
wire captureDR_r0 = ((((ore)) & !debug_mode_sync) || ( debug_mode_sync ? (1'b1) : 1'b0 ));
////MSB 63 LSB 0  and total rambit is 64 and  dsize is 64
always @(posedge clk) begin
    if (captureDR_r0)
       Data_reg_r0[63:0] <= r0_OutputMuxDataOut[63:0];
end
assign dout = Data_reg_r0;
// Declare the SO which goes out finally
`ifndef EMU
`ifndef FPGA
`define NO_EMU_NO_FPGA
// lock-up latch for ram_access SO
LNQD1PO4 testInst_ram_access_lockup (
                   .Q(SO_int_net),
                   .D(SO_0_0),
                   .EN(la_bist_clkw0));
`endif
`endif
`ifndef NO_EMU_NO_FPGA
// no latch allow during emulation synthesis
assign SO_int_net = SO_0_0;
`endif
// Ram access scan chain
wire gated_clk_jtag_Ra_array_reg_r0_reg;
CKLNQD12PO4 UJ_clk_jtag_Ra_array_reg_r0_reg (.Q(gated_clk_jtag_Ra_array_reg_r0_reg), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (muxed_Ra_array_capture_enr0 | 1'b0 | ( 1'b0 ) ) ), .TE(scan_en));
ScanShareSel_JTAG_reg_ext_cg #(2, 0, 0) testInst_Ra_array_reg_r0_reg (
     .clk(gated_clk_jtag_Ra_array_reg_r0_reg), .sel(debug_mode),
            .shiftDR(shiftDR),
            .reset_(1'b1), .D(D_Ra_array_reg_r0), .Q(radr_latchq),
            .scanin(SI), .scanout(Ra_to_Wi_so) );
wire gated_clk_jtag_Wdata_w0_reg;
CKLNQD12PO4 UJ_clk_jtag_Wdata_w0_reg (.Q(gated_clk_jtag_Wdata_w0_reg), .CP(clk), .E(debug_mode_sync ? (posedge_updateDR_sync| ( 1'b0 | shiftDR ) ) : ((|we_0_0) | 1'b0 | 1'b0 | ( 1'b0 ) ) ), .TE(scan_en));
ScanShareSel_JTAG_reg_ext_cg #(64, 0, 0) testInst_Wdata_w0_reg (
     .clk(gated_clk_jtag_Wdata_w0_reg), .sel(debug_mode),
            .shiftDR(shiftDR),
            .reset_(1'b1), .D(Wdata_w0_reg_d), .Q(wd_q),
            .scanin(wdata_w0_scanin), .scanout(SO_0_0) );
`ifdef ASSERT_ON
`ifndef SYNTHESIS
reg sim_reset_;
initial sim_reset_ = 0;
always @(posedge clk) sim_reset_ <= 1'b1;
wire start_of_sim = sim_reset_;
wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0;
nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk);
nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk);
reg [4-1:0] written;
always@(posedge clk or negedge sim_reset_) begin
   if(!sim_reset_) begin
      written <= {4{1'b0}};
   end else if( |we)begin
      written[wa] <= 1'b1;
   end
end
`endif // SYNTHESIS 
`endif // ASSERT_ON
`ifdef ASSERT_ON
`ifndef SYNTHESIS
`endif
`endif
`ifdef ASSERT_ON
`ifndef SYNTHESIS
wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active");
nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx);
nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx);
`endif
`endif
// submodule done
endmodule