Added NVDLA design

Signed-off-by: sakundu <sakundu@ucsd.edu>

Flows/NanGate45/ariane136/scripts/cadence/run_genus.tcl

@@ -31,6 +31,8 @@ set link_library $list_lib
 set target_library $list_lib
 
 # set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
 set_db auto_ungroup none
 
 set_db library $list_lib
@@ -65,6 +67,7 @@ syn_generic
 time_info GENERIC
 
 # generate a summary for the current stage of synthesis
+write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
 write_reports -directory ${REPORTS_PATH} -tag generic
 write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
 

Flows/NanGate45/nvdla/constraints/NV_NVDLA_partition_c.sdc

+# ===================================================================
+# File: syn/cons/NV_NVDLA_partition_c.sdc
+# NVDLA Open Source Project
+#
+# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the
+# NVDLA Open Hardware License; see the "LICENSE.txt" file that came
+# with this distribution for more information.
+# ===================================================================
+
+set_max_area 0
+set_ideal_network [get_ports direct_reset_]
+set_ideal_network [get_ports dla_reset_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
+set_ideal_network [get_ports test_mode]
+create_clock [get_ports nvdla_core_clk]  -period 0.9  -waveform {0 0.45}
+set_clock_transition -max -rise 0.05 [get_clocks nvdla_core_clk]
+set_clock_transition -max -fall 0.05 [get_clocks nvdla_core_clk]
+set_clock_transition -min -rise 0.05 [get_clocks nvdla_core_clk]
+set_clock_transition -min -fall 0.05 [get_clocks nvdla_core_clk]
+set_false_path   -from [get_ports direct_reset_]
+set_false_path   -from [get_ports dla_reset_rstn]
+set_false_path   -from [get_ports test_mode]
+set_false_path   -from [get_ports pwrbus_ram_pd*]
+set_false_path   -from [get_ports tmc2slcg_disable_clock_gating]
+set_false_path   -from [get_ports global_clk_ovr_on]
+set_false_path   -from [get_ports nvdla_clk_ovr_on]

Flows/NanGate45/nvdla/scripts/cadence/design_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+set DESIGN NV_NVDLA_partition_c
+set sdc  ../../constraints/${DESIGN}.sdc
+
+# def file with die size and placed IO pins
+set floorplan_def ../../def/${DESIGN}_fp.def
+
+set rtl_path ../../../../../Testcases/nvdla/rtl/
+
+#
+# Effort level during optimization in syn_generic -physical (or called generic) stage
+# possible values are : high, medium or low
+set GEN_EFF medium
+
+# Effort level during optimization in syn_map -physical (or called mapping) stage
+# possible values are : high, medium or low
+set MAP_EFF high

Flows/NanGate45/nvdla/scripts/cadence/gen_mp_config.tcl

+# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+puts "VERSION 1.0"
+set mem_hier ""
+foreach a [dbget [dbget top.insts.cell.name fakeram45_* -p2 ].name ] {
+    regexp {(.*)(/)([^/]*)} $a c b
+    lappend mem_hier $b
+}
+set unique_mem_hier [lsort -unique $mem_hier]
+puts "BEGIN SEED"
+foreach a $unique_mem_hier {
+puts "name=$a util=$util"
+}
+puts "END SEED"
+
+puts "BEGIN MACRO"
+foreach a [dbget top.insts.cell.name fakeram45_* -u] {
+puts "name=$a  orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5"
+}
+puts "END MACRO"
+
+puts "BEGIN CONSTRAINT"
+puts "END CONSTRAINT"

Flows/NanGate45/nvdla/scripts/cadence/lib_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+# lib and lef, RC setup
+
+set libdir "../../../../../Enablements/NanGate45/lib"
+set lefdir "../../../../../Enablements/NanGate45/lef"
+set qrcdir "../../../../../Enablements/NanGate45/qrc"
+
+set_db init_lib_search_path { \
+    ${libdir} \
+    ${lefdir} \
+}
+
+set libworst "  
+    ${libdir}/NangateOpenCellLibrary_typical.lib \
+    ${libdir}/fakeram45_256x16.lib \
+    ${libdir}/fakeram45_256x64.lib \
+    "
+
+
+set libbest " 
+    ${libdir}/NangateOpenCellLibrary_typical.lib \
+    ${libdir}/fakeram45_256x16.lib \
+    ${libdir}/fakeram45_256x64.lib \
+    "
+
+set lefs "  
+    ${lefdir}/NangateOpenCellLibrary.tech.lef \
+    ${lefdir}/NangateOpenCellLibrary.macro.mod.lef \
+    ${lefdir}/fakeram45_256x16.lef \
+    ${lefdir}/fakeram45_256x64.lef \
+    "
+
+set qrc_max "${qrcdir}/NG45.tch"
+set qrc_min "${qrcdir}/NG45.tch"
+#
+# Ensures proper and consistent library handling between Genus and Innovus
+#set_db library_setup_ispatial true

Flows/NanGate45/nvdla/scripts/cadence/mmmc_iSpatial_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+#create_opcond -name op_cond_wc -process 1.0 -voltage 0.72 -temperature 125
+#create_opcond -name op_cond_bc -process 1.0 -voltage 0.88 -temperature -40
+ 
+create_timing_condition -name timing_wc  -library_sets { WC_LIB }
+create_timing_condition -name timing_bc  -library_sets { BC_LIB }
+ 
+create_rc_corner -name Cmax -qrc_tech $qrc_max
+create_rc_corner -name Cmin -qrc_tech $qrc_min
+
+create_delay_corner -name WC -early_timing_condition { timing_wc } \
+                             -late_timing_condition  { timing_wc } \
+                             -early_rc_corner          Cmax        \
+                             -late_rc_corner           Cmax
+
+create_delay_corner -name BC -early_timing_condition { timing_bc } \
+                             -late_timing_condition  { timing_bc } \
+                             -early_rc_corner          Cmin        \
+                             -late_rc_corner           Cmin
+
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON
+ 
+set_analysis_view -setup WC_VIEW -hold BC_VIEW

Flows/NanGate45/nvdla/scripts/cadence/mmmc_setup.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+
+create_library_set -name WC_LIB -timing $libworst
+create_library_set -name BC_LIB -timing $libbest
+ 
+create_rc_corner -name Cmax
+create_rc_corner -name Cmin
+
+
+create_delay_corner -name WC -library_set WC_LIB -rc_corner Cmax
+create_delay_corner -name BC -library_set BC_LIB -rc_corner Cmin
+
+create_constraint_mode -name CON -sdc_file $sdc 
+create_analysis_view -name WC_VIEW -delay_corner WC -constraint_mode CON
+create_analysis_view -name BC_VIEW -delay_corner BC -constraint_mode CON

Flows/NanGate45/nvdla/scripts/cadence/mp_config.tcl

+# This script was written and developed by ABKGroup students at UCSD; however, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+##########################################
+# Masterplan User Constraint File Template
+##########################################
+
+###########################################################
+# Syntax Convention:                                      #
+# [] means optional                                       #
+# <> means filling with real value or name in your design #
+# () indicates the unit name for your value               #
+# | means OR                                              #
+# {} is used to enclose a group of names (one or more)    #
+# ... means more similar items                            #
+###########################################################
+
+
+###########################################################
+# Version section (required on and after Innovus 10.1)  #
+# If not provided, will be parsed as older format         #
+# VERSION <N.N>                                           #
+# For example:                                            #
+###########################################################
+VERSION 1.0
+
+
+######################################################################
+# Seed Section (optional) : one single line per seed                 #
+# name=<seedName> [util=<float>] [createFence=true]\                 #
+#    [minWHRatio=<float>] [maxWHRatio=<float>]\                      #
+#    [minFenceToFenceSpace=<(um)>] [minFenceToCoreSpace=<(um)>]\     #
+#    [minFenceToInsideMacroSpace=<(um)>]\                            #
+#    [minFenceToOutsideMacroSpace=<(um)>]\                           #
+#    [minInsideFenceMacroToMacroSpace=<(um)>]\                       #
+#    [master=<nameOrOtherName>] [cloneOrient={R0|MX|MY|R180}]        #
+# For example:                                                       #
+######################################################################
+BEGIN SEED
+name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_icache/sram_block_0__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_icache/sram_block_0__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_icache/sram_block_1__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_icache/sram_block_1__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_icache/sram_block_2__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_icache/sram_block_2__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_icache/sram_block_3__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_icache/sram_block_3__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_0__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_0__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_1__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_1__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_2__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_2__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_3__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_3__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_4__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_4__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_5__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_5__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_6__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_6__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_7__data_sram/genblk1_1__i_ram
+name=i_cache_subsystem/i_nbdcache/sram_block_7__tag_sram/genblk1_0__i_ram
+name=i_cache_subsystem/i_nbdcache/valid_dirty_sram/genblk1_0__i_ram
+END SEED
+
+
+######################################################################
+# MACRO section syntax  : one single line per macro                  #
+# name=<InstOrCell> [minLeftSpace=<(um)>] [minRightSpace=<(um)>]\    #
+#                   [minTopSpace=<(um)>] [minBottomSpace=<(um)>]\    #
+#                   [orient={R0|MX|MY|R180|MX90|R90|R270|MY90}]\     #
+#                   [isCell=true] [minMacroToCoreSpace=<(um)>]       #
+# For example:                                                       #
+######################################################################
+BEGIN MACRO
+name=fakeram45_256x16 orient={R0} isCell=true minRightSpace=10 minLeftSpace=10 minTopSpace=5 minBottomSpace=5
+END MACRO
+
+
+#################################################################################
+# relative placement CONSTRAINT section syntax                                  #
+# name=<HInstOrGroupOrHM> loc=<T|B|R|L|TL|TR|BL|BR|(x,y)>                       #
+# name=<NewName> members={<Module1> <Module2> <Module3>..} [strength=Soft|Hard] #
+# For example:                                                                  #
+#################################################################################
+BEGIN CONSTRAINT
+END CONSTRAINT

Flows/NanGate45/nvdla/scripts/cadence/rtl_list.tcl

+#-y nv_small/src
+#+incdir+nv_small/src
++libext+.v
++libext+.sv
++libext+.gv
++define+DISABLE_TESTPOINTS
++define+NV_SYNTHESIS
+//+define+RAM_INTERFACE
+
+NV_nvdla.v
+NV_NVDLA_apb2csb.v
+NV_NVDLA_partition_c.v
+NV_NVDLA_partition_a.v
+NV_NVDLA_partition_p.v
+NV_NVDLA_partition_o.v
+NV_NVDLA_partition_m.v
+NV_NVDLA_CFGROM_rom.v
+NV_NVDLA_sync3d.v
+NV_NVDLA_cfgrom.v
+NV_NVDLA_glb.v
+NV_NVDLA_core_reset.v
+NV_NVDLA_sync3d_s.v
+NV_NVDLA_mcif.v
+NV_NVDLA_cdp.v
+NV_NVDLA_csb_master.v
+NV_NVDLA_pdp.v
+NV_NVDLA_reset.v
+NV_NVDLA_PDP_rdma.v
+NV_NVDLA_CDP_rdma.v
+NV_NVDLA_CDP_DP_nan.v
+NV_NVDLA_PDP_slcg.v
+NV_NVDLA_PDP_core.v
+NV_NVDLA_CDP_slcg.v
+NV_NVDLA_MCIF_csb.v
+NV_NVDLA_PDP_nan.v
+NV_NVDLA_CDP_wdma.v
+NV_NVDLA_PDP_wdma.v
+NV_NVDLA_PDP_reg.v
+NV_NVDLA_GLB_ic.v
+NV_NVDLA_CDP_reg.v
+NV_NVDLA_GLB_csb.v
+NV_NVDLA_CDP_dp.v
+NV_NVDLA_MCIF_read.v
+NV_NVDLA_MCIF_write.v
+NV_NVDLA_MCIF_CSB_reg.v
+NV_NVDLA_MCIF_WRITE_ig.v
+NV_NVDLA_MCIF_READ_ig.v
+NV_NVDLA_MCIF_WRITE_cq.v
+NV_NVDLA_MCIF_READ_eg.v
+NV_NVDLA_MCIF_WRITE_eg.v
+NV_NVDLA_MCIF_READ_IG_arb.v
+NV_NVDLA_MCIF_READ_IG_bpt.v
+NV_NVDLA_MCIF_READ_IG_cvt.v
+NV_NVDLA_MCIF_WRITE_IG_bpt.v
+NV_NVDLA_MCIF_WRITE_IG_cvt.v
+NV_NVDLA_MCIF_WRITE_IG_arb.v
+NV_CLK_gate_power.v
+CKLNQD12.v
+CKLNQD12PO4.v
+NV_BLKBOX_SRC0_X.v
+AN2D4PO4.v
+NV_NVDLA_CDP_RDMA_eg.v
+NV_NVDLA_CDP_DP_cvtout.v
+NV_NVDLA_CDP_DP_sum.v
+NV_NVDLA_CDP_RDMA_ig.v
+NV_NVDLA_CDP_DP_lut.v
+NV_NVDLA_CDP_DP_LUT_ctrl.v
+NV_NVDLA_CDP_REG_single.v
+NV_NVDLA_CDP_RDMA_reg.v
+NV_NVDLA_CDP_DP_cvtin.v
+NV_NVDLA_CDP_RDMA_cq.v
+NV_NVDLA_CDP_DP_bufferin_tp1.v
+NV_NVDLA_CDP_DP_mul.v
+NV_NVDLA_CDP_REG_dual.v
+NV_NVDLA_CDP_DP_syncfifo.v
+NV_NVDLA_CDP_DP_intp.v
+NV_NVDLA_CDP_DP_LUT_CTRL_unit.v
+NV_NVDLA_CDP_DP_INTP_unit.v
+NV_NVDLA_CDP_DP_MUL_unit.v
+sync_reset.v
+NV_BLKBOX_SRC0.v
+OR2D1.v
+p_SSYNC2DO_C_PP.v
+MUX2D4.v
+MUX2HDD2.v
+sync3d_s_ppp.v
+sync3d.v
+p_SSYNC3DO_S_PPP.v
+p_SSYNC3DO.v
+NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v
+NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
+oneHotClk_async_read_clock.v
+p_STRICTSYNC3DOTM_C_PPP.v
+oneHotClk_async_write_clock.v
+p_SSYNC3DO_C_PPP.v
+NV_NVDLA_XXIF_libs.v
+NV_NVDLA_DMAIF_rdreq.v
+NV_BLKBOX_SINK.v
+NV_NVDLA_CDP_RDMA_lat_fifo.v
+NV_NVDLA_CDP_RDMA_REG_single.v
+NV_NVDLA_CDP_RDMA_ro_fifo.v
+NV_NVDLA_CDP_RDMA_REG_dual.v
+NV_NVDLA_DMAIF_rdrsp.v
+NV_NVDLA_CDP_WDMA_dat_fifo.v
+NV_NVDLA_DMAIF_wr.v
+HLS_cdp_ocvt.v
+HLS_cdp_icvt.v
+NV_NVDLA_CDP_DP_data_fifo.v
+NV_NVDLA_CDP_DP_intpinfo_fifo.v
+NV_NVDLA_CDP_DP_sumpd_fifo.v
+int_sum_block_tp1.v
+NV_NVDLA_HLS_shiftrightsu.v
+NV_NVDLA_PDP_CORE_preproc.v
+NV_NVDLA_PDP_WDMA_dat.v
+NV_NVDLA_PDP_CORE_cal2d.v
+NV_NVDLA_PDP_RDMA_cq.v
+NV_NVDLA_PDP_CORE_cal1d.v
+NV_NVDLA_PDP_RDMA_REG_single.v
+NV_NVDLA_PDP_RDMA_eg.v
+NV_NVDLA_PDP_WDMA_cmd.v
+NV_NVDLA_PDP_REG_dual.v
+NV_NVDLA_PDP_REG_single.v
+NV_NVDLA_PDP_RDMA_REG_dual.v
+NV_NVDLA_PDP_RDMA_ig.v
+NV_NVDLA_PDP_RDMA_reg.v
+NV_NVDLA_PDP_RDMA_lat_fifo.v
+NV_NVDLA_PDP_RDMA_ro_fifo.v
+NV_NVDLA_PDP_WDMA_DAT_fifo.v
+NV_NVDLA_PDP_CORE_unit1d.v
+NV_NVDLA_GLB_CSB_reg.v
+NV_NVDLA_sync3d_c.v
+sync3d_c_ppp.v
+NV_NVDLA_cdma.v
+NV_NVDLA_csc.v
+NV_NVDLA_cbuf.v
+NV_NVDLA_CDMA_status.v
+NV_NVDLA_CDMA_regfile.v
+NV_NVDLA_CDMA_cvt.v
+NV_NVDLA_CDMA_dc.v
+NV_NVDLA_CDMA_dma_mux.v
+NV_NVDLA_CDMA_shared_buffer.v
+NV_NVDLA_CDMA_img.v
+NV_NVDLA_CDMA_slcg.v
+NV_NVDLA_CDMA_wt.v
+NV_NVDLA_CDMA_WT_8ATMM_fifo.v
+NV_NVDLA_CDMA_CVT_cell.v
+NV_NVDLA_CDMA_IMG_ctrl.v
+NV_NVDLA_CDMA_IMG_pack.v
+NV_NVDLA_CDMA_IMG_sg.v
+NV_NVDLA_CDMA_single_reg.v
+NV_NVDLA_CDMA_WT_fifo.v
+NV_NVDLA_CDMA_dual_reg.v
+NV_NVDLA_CDMA_DC_fifo.v
+NV_NVDLA_HLS_saturate.v
+NV_NVDLA_CDMA_IMG_fifo.v
+NV_NVDLA_CDMA_IMG_sg2pack_fifo.v
+NV_NVDLA_CSC_regfile.v
+NV_NVDLA_CSC_wl.v
+NV_NVDLA_CSC_WL_dec.v
+NV_NVDLA_CSC_sg.v
+NV_NVDLA_CSC_dl.v
+NV_NVDLA_CSC_slcg.v
+NV_NVDLA_CSC_SG_dat_fifo.v
+NV_NVDLA_CSC_SG_wt_fifo.v
+NV_NVDLA_CSC_dual_reg.v
+NV_NVDLA_CSC_single_reg.v
+NV_NVDLA_CACC_assembly_ctrl.v
+NV_NVDLA_CACC_dual_reg.v
+NV_NVDLA_CMAC_CORE_slcg.v
+NV_NVDLA_CACC_assembly_buffer.v
+NV_NVDLA_CACC_slcg.v
+NV_NVDLA_cacc.v
+NV_NVDLA_CACC_single_reg.v
+NV_NVDLA_CACC_calculator.v
+NV_NVDLA_CMAC_core.v
+NV_NVDLA_CACC_delivery_buffer.v
+NV_NVDLA_CACC_CALC_int8.v
+NV_NVDLA_CACC_regfile.v
+NV_NVDLA_CMAC_CORE_rt_in.v
+NV_NVDLA_CMAC_REG_dual.v
+NV_NVDLA_CACC_delivery_ctrl.v
+NV_NVDLA_CMAC_reg.v
+NV_NVDLA_cmac.v
+NV_NVDLA_CMAC_CORE_active.v
+NV_NVDLA_CMAC_CORE_cfg.v
+NV_NVDLA_CMAC_CORE_mac.v
+NV_NVDLA_CMAC_REG_single.v
+NV_NVDLA_CMAC_CORE_rt_out.v
+NV_NVDLA_sdp.v
+NV_NVDLA_SDP_rdma.v
+NV_NVDLA_SDP_wdma.v
+NV_NVDLA_SDP_reg.v
+NV_NVDLA_SDP_core.v
+NV_NVDLA_SDP_HLS_x1_int.v
+NV_NVDLA_SDP_WDMA_cmd.v
+NV_NVDLA_SDP_RDMA_REG_dual.v
+NV_NVDLA_SDP_RDMA_reg.v
+NV_NVDLA_SDP_CORE_unpack.v
+NV_NVDLA_SDP_REG_dual.v
+NV_NVDLA_SDP_RDMA_pack.v
+NV_NVDLA_SDP_WDMA_gate.v
+NV_NVDLA_SDP_HLS_c.v
+NV_NVDLA_SDP_nrdma.v
+NV_NVDLA_SDP_WDMA_DAT_out.v
+NV_NVDLA_SDP_CORE_pack.v
+NV_NVDLA_SDP_WDMA_intr.v
+NV_NVDLA_SDP_cmux.v
+NV_NVDLA_SDP_CORE_gate.v
+NV_NVDLA_SDP_WDMA_dat.v
+NV_NVDLA_SDP_REG_single.v
+NV_NVDLA_SDP_RDMA_REG_single.v
+NV_NVDLA_SDP_brdma.v
+NV_NVDLA_SDP_WDMA_DAT_in.v
+NV_NVDLA_SDP_mrdma.v
+NV_NVDLA_SDP_HLS_x2_int.v
+NV_NVDLA_SDP_MRDMA_eg.v
+NV_NVDLA_SDP_MRDMA_gate.v
+NV_NVDLA_SDP_NRDMA_gate.v
+NV_NVDLA_SDP_MRDMA_ig.v
+NV_NVDLA_SDP_RDMA_ig.v
+NV_NVDLA_SDP_RDMA_eg.v
+NV_NVDLA_SDP_BRDMA_gate.v
+NV_NVDLA_SDP_RDMA_dmaif.v
+NV_NVDLA_SDP_HLS_X_int_relu.v
+NV_NVDLA_SDP_HLS_C_int.v
+NV_NVDLA_SDP_HLS_X_int_alu.v
+NV_NVDLA_SDP_HLS_X_int_mul.v
+NV_NVDLA_SDP_HLS_X_int_trt.v
+NV_NVDLA_SDP_HLS_relu.v
+NV_NVDLA_SDP_HLS_prelu.v
+NV_NVDLA_SDP_HLS_sync2data.v
+NV_NVDLA_HLS_shiftleftsu.v
+NV_NVDLA_HLS_shiftrightsatsu.v
+NV_NVDLA_SDP_NRDMA_cq_lib.v
+NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v
+NV_NVDLA_SDP_BRDMA_cq_lib.v
+NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v
+NV_NVDLA_SDP_MRDMA_cq_lib.v
+NV_NVDLA_SDP_MRDMA_EG_din.v
+NV_NVDLA_SDP_MRDMA_EG_dout.v
+NV_NVDLA_SDP_MRDMA_EG_cmd.v
+NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v
+NV_NVDLA_SDP_RDMA_unpack.v
+NV_NVDLA_SDP_RDMA_EG_ro.v
+NV_BLKBOX_BUFFER.v
+SDFQD1.v
+RAMDP_128X6_GL_M2_E2.v
+RAMDP_128X11_GL_M2_E2.v
+RAMDP_16X64_GL_M1_E2.v
+RAMPDP_256X64_GL_M2_D2.v
+RAMDP_16X272_GL_M1_E2.v
+RAMDP_16X66_GL_M1_E2.v
+RAMDP_16X256_GL_M1_E2.v
+RAMDP_16X14_GL_M1_E2.v
+RAMDP_16X16_GL_M1_E2.v
+ScanShareSel_JTAG_reg_ext_cg.v
+sync2d_c_pp.v
+p_SDFCNQD1PO4.v
+RAMDP_256X4_GL_M2_E2.v
+RAMDP_256X8_GL_M2_E2.v
+RAMDP_8X66_GL_M1_E2.v
+RAMDP_80X9_GL_M2_E2.v
+RAMPDP_80X17_GL_M2_D2.v
+RAMDP_60X22_GL_M1_E2.v
+RAMPDP_128X18_GL_M2_D2.v
+nv_ram_rws_128x18_logic.v
+nv_ram_rws_128x256_logic.v
+nv_ram_rws_128x64_logic.v
+nv_ram_rws_16x256_logic.v
+nv_ram_rws_16x272_logic.v
+nv_ram_rws_16x64_logic.v
+nv_ram_rws_256x3_logic.v
+nv_ram_rws_256x512_logic.v
+nv_ram_rws_256x64_logic.v
+nv_ram_rws_256x7_logic.v
+nv_ram_rws_32x16_logic.v
+nv_ram_rws_32x512_logic.v
+nv_ram_rws_32x544_logic.v
+nv_ram_rws_32x768_logic.v
+nv_ram_rws_512x256_logic.v
+nv_ram_rws_512x512_logic.v
+nv_ram_rws_512x64_logic.v
+nv_ram_rws_64x1024_logic.v
+nv_ram_rws_64x1088_logic.v
+nv_ram_rws_64x10_logic.v
+nv_ram_rws_64x116_logic.v
+nv_ram_rws_64x18_logic.v
+nv_ram_rwsp_128x11_logic.v
+nv_ram_rwsp_128x6_logic.v
+nv_ram_rwsp_160x16_logic.v
+nv_ram_rwsp_160x514_logic.v
+nv_ram_rwsp_160x65_logic.v
+nv_ram_rwsp_16x14_logic.v
+nv_ram_rwsp_16x16_logic.v
+nv_ram_rwsp_16x65_logic.v
+nv_ram_rwsp_20x289_logic.v
+nv_ram_rwsp_245x514_logic.v
+nv_ram_rwsp_256x11_logic.v
+nv_ram_rwsp_32x32_logic.v
+nv_ram_rwsp_61x514_logic.v
+nv_ram_rwsp_61x64_logic.v
+nv_ram_rwsp_61x65_logic.v
+nv_ram_rwsp_80x14_logic.v
+nv_ram_rwsp_80x16_logic.v
+nv_ram_rwsp_80x256_logic.v
+nv_ram_rwsp_80x514_logic.v
+nv_ram_rwsp_80x65_logic.v
+nv_ram_rwsp_8x65_logic.v
+nv_ram_rwst_256x8_logic.v
+nv_ram_rwsthp_19x32_logic.v
+nv_ram_rwsthp_19x4_logic.v
+nv_ram_rwsthp_19x80_logic.v
+nv_ram_rwsthp_20x4_logic.v
+nv_ram_rwsthp_60x168_logic.v
+nv_ram_rwsthp_60x21_logic.v
+nv_ram_rwsthp_80x15_logic.v
+nv_ram_rwsthp_80x17_logic.v
+nv_ram_rwsthp_80x72_logic.v
+nv_ram_rwsthp_80x9_logic.v
+nv_ram_rws_128x18.v
+nv_ram_rws_128x256.v
+nv_ram_rws_128x64.v
+nv_ram_rws_16x256.v
+nv_ram_rws_16x272.v
+nv_ram_rws_16x64.v
+nv_ram_rws_256x3.v
+nv_ram_rws_256x512.v
+nv_ram_rws_256x64.v
+nv_ram_rws_256x7.v
+nv_ram_rws_32x16.v
+nv_ram_rws_32x512.v
+nv_ram_rws_32x544.v
+nv_ram_rws_32x768.v
+nv_ram_rws_512x256.v
+nv_ram_rws_512x512.v
+nv_ram_rws_512x64.v
+nv_ram_rws_64x1024.v
+nv_ram_rws_64x1088.v
+nv_ram_rws_64x10.v
+nv_ram_rws_64x116.v
+nv_ram_rws_64x18.v
+nv_ram_rwsp_128x11.v
+nv_ram_rwsp_128x6.v
+nv_ram_rwsp_160x16.v
+nv_ram_rwsp_160x514.v
+nv_ram_rwsp_160x65.v
+nv_ram_rwsp_16x14.v
+nv_ram_rwsp_16x16.v
+nv_ram_rwsp_16x65.v
+nv_ram_rwsp_20x289.v
+nv_ram_rwsp_245x514.v
+nv_ram_rwsp_256x11.v
+nv_ram_rwsp_32x32.v
+nv_ram_rwsp_61x514.v
+nv_ram_rwsp_61x64.v
+nv_ram_rwsp_61x65.v
+nv_ram_rwsp_80x14.v
+nv_ram_rwsp_80x16.v
+nv_ram_rwsp_80x256.v
+nv_ram_rwsp_80x514.v
+nv_ram_rwsp_80x65.v
+nv_ram_rwsp_8x65.v
+nv_ram_rwst_256x8.v
+nv_ram_rwsthp_19x32.v
+nv_ram_rwsthp_19x4.v
+nv_ram_rwsthp_19x80.v
+nv_ram_rwsthp_20x4.v
+nv_ram_rwsthp_60x168.v
+nv_ram_rwsthp_60x21.v
+nv_ram_rwsthp_80x15.v
+nv_ram_rwsthp_80x17.v
+nv_ram_rwsthp_80x72.v
+nv_ram_rwsthp_80x9.v
+fakeram45_256x64_dp.v
+
+
+-v NV_NVDLA_XXIF_libs.v

Flows/NanGate45/nvdla/scripts/cadence/run.sh

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+#!/bin/tcsh
+module unload genus
+module load genus/21.1
+module unload innovus
+module load innovus/21.1
+
+mkdir log -p
+genus -overwrite -log log/genus.log -no_gui -files run_genus_iSpatial.tcl
+innovus -64 -files run_invs.tcl -overwrite -log log/innovus.log

Flows/NanGate45/nvdla/scripts/cadence/run_genus.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+
+# set path
+set_db hdl_flatten_complex_port true
+set_db hdl_record_naming_style  %s_%s
+set_db auto_ungroup none
+
+set_db library $list_lib
+set_db init_hdl_search_path [list . ../../../../../Testcases/nvdla/rtl/]
+
+#################################################
+# Load Design and Initialize
+#################################################
+
+read_hdl -f rtl_list.tcl
+
+elaborate $DESIGN
+time_info Elaboration
+
+read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_hdl -generic > ${HANDOFF_PATH}/${DESIGN}_generic.v
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+#write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/NanGate45/nvdla/scripts/cadence/run_genus_iSpatial.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+read_mmmc mmmc_iSpatial_setup.tcl
+
+# set the output directories
+set OUTPUTS_PATH  syn_output
+set REPORTS_PATH  syn_rpt
+set HANDOFF_PATH  syn_handoff
+
+if {![file exists ${OUTPUTS_PATH}]} {
+  file mkdir ${OUTPUTS_PATH}
+}
+
+if {![file exists ${REPORTS_PATH}]} {
+  file mkdir ${REPORTS_PATH}
+}
+
+if {![file exists ${HANDOFF_PATH}]} {
+  file mkdir ${HANDOFF_PATH}
+}
+#
+# set threads
+set_db max_cpus_per_server 16
+set_db super_thread_servers "localhost"
+#
+set list_lib "$libworst"
+set_db invs_temp_dir ${OUTPUTS_PATH}/invs_tmp_dir
+read_physical -lefs $lefs
+
+# Target library
+set link_library $list_lib
+set target_library $list_lib
+set_db init_hdl_search_path [list . $rtl_path]
+
+# set path
+set_db auto_ungroup none
+
+#set_db library $list_lib
+
+
+#################################################
+# Load Design and Initialize
+#################################################
+read_hdl -f rtl_list.tcl
+
+elaborate $DESIGN
+time_info Elaboration
+
+#read_sdc $sdc
+init_design
+
+check_design -unresolved
+
+check_timing_intent
+# reports the physical layout estimation report from lef and QRC tech file
+report_ple > ${REPORTS_PATH}/ple.rpt 
+
+###############################################
+# Read DEF
+###############################################
+read_def $floorplan_def
+check_floorplan -detailed
+
+# keep hierarchy during synthesis
+set_db auto_ungroup none
+
+syn_generic -physical
+time_info GENERIC
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag generic
+write_db  ${OUTPUTS_PATH}/${DESIGN}_generic.db
+
+syn_map -physical
+time_info MAPPED
+
+# generate a summary for the current stage of synthesis
+write_reports -directory ${REPORTS_PATH} -tag map
+write_db  ${OUTPUTS_PATH}/${DESIGN}_map.db
+
+syn_opt -spatial
+time_info OPT 
+write_db ${OUTPUTS_PATH}/${DESIGN}_opt.db
+
+##############################################################################
+# Write reports
+##############################################################################
+
+# summarizes the information, warnings and errors
+report_messages > ${REPORTS_PATH}/${DESIGN}_messages.rpt
+
+# generate PPA reports
+report_gates > ${REPORTS_PATH}/${DESIGN}_gates.rpt
+report_power > ${REPORTS_PATH}/${DESIGN}_power.rpt
+report_area > ${REPORTS_PATH}/${DESIGN}_power.rpt
+write_reports -directory ${REPORTS_PATH} -tag final 
+
+#write_sdc >${HANDOFF_PATH}/${DESIGN}.sdc
+#write_hdl > ${HANDOFF_PATH}/${DESIGN}.v
+write_design -innovus -base_name ${HANDOFF_PATH}/${DESIGN}
+
+exit
+

Flows/NanGate45/nvdla/scripts/cadence/run_invs.tcl

+# This script was written and developed by ABKGroup students at UCSD. However, the underlying commands and reports are copyrighted by Cadence. 
+# We thank Cadence for granting permission to share our research to help promote and foster the next generation of innovators.
+source lib_setup.tcl
+source design_setup.tcl
+source mmmc_setup.tcl
+
+setMultiCpuUsage -localCpu 16
+set util 0.3
+
+set netlist "./syn_handoff/$DESIGN.v"
+set sdc "./syn_handoff/$DESIGN.sdc"
+
+set site "FreePDK45_38x28_10R_NP_162NW_34O"
+
+set rptDir summaryReport/ 
+set encDir enc/
+
+if {![file exists $rptDir/]} {
+    exec mkdir $rptDir/
+}
+
+if {![file exists $encDir/]} {
+    exec mkdir $encDir/
+}
+
+# default settings
+set init_pwr_net VDD
+set init_gnd_net VSS
+
+# default settings
+set init_verilog "$netlist"
+set init_design_netlisttype "Verilog"
+set init_design_settop 1
+set init_top_cell "$DESIGN"
+set init_lef_file "$lefs"
+
+# MCMM setup
+init_design -setup {WC_VIEW} -hold {BC_VIEW}
+set_power_analysis_mode -leakage_power_view WC_VIEW -dynamic_power_view WC_VIEW
+
+set_interactive_constraint_modes {CON}
+setDesignMode -process 45
+
+clearGlobalNets
+globalNetConnect VDD -type pgpin -pin VDD -inst * -override
+globalNetConnect VSS -type pgpin -pin VSS -inst * -override
+globalNetConnect VDD -type tiehi -inst * -override
+globalNetConnect VSS -type tielo -inst * -override
+
+
+setOptMode -powerEffort low -leakageToDynamicRatio 0.5
+setGenerateViaMode -auto true
+generateVias
+
+# basic path groups
+createBasicPathGroups -expanded
+
+## Generate the floorplan ##
+#floorPlan -r 1.0 $util 10 10 10 10
+defIn $floorplan_def 
+
+## Macro Placement ##
+#redirect mp_config.tcl {source gen_mp_config.tcl}
+#proto_design -constraints mp_config.tcl 
+addHaloToBlock -allMacro 5 5 5 5
+place_design -concurrent_macros
+refine_macro_place
+saveDesign ${encDir}/${DESIGN}_floorplan.enc
+
+## Creating Pin Blcokage for lower and upper pin layers ##
+createPinBlkg -name Layer_1 -layer {metal2 metal3 metal9 metal10} -edge 0
+createPinBlkg -name side_top -edge 1
+createPinBlkg -name side_right -edge 2
+createPinBlkg -name side_bottom -edge 3
+
+setPlaceMode -place_detail_legalization_inst_gap 1
+setFillerMode -fitGap true
+setDesignMode -topRoutingLayer 10
+setDesignMode -bottomRoutingLayer 2 
+
+place_opt_design -out_dir $rptDir -prefix place
+saveDesign $encDir/${DESIGN}_placed.enc
+
+set_ccopt_property post_conditioning_enable_routing_eco 1
+set_ccopt_property -cts_def_lock_clock_sinks_after_routing true
+setOptMode -unfixClkInstForOpt false
+
+create_ccopt_clock_tree_spec
+ccopt_design
+
+set_interactive_constraint_modes [all_constraint_modes -active]
+set_propagated_clock [all_clocks]
+set_clock_propagation propagated
+
+# ------------------------------------------------------------------------------
+# Routing
+# ------------------------------------------------------------------------------
+setNanoRouteMode -drouteVerboseViolationSummary 1
+setNanoRouteMode -routeWithSiDriven true
+setNanoRouteMode -routeWithTimingDriven true
+setNanoRouteMode -routeUseAutoVia true
+
+##Recommended by lib owners
+# Prevent router modifying M1 pins shapes
+setNanoRouteMode -routeWithViaInPin "1:1"
+setNanoRouteMode -routeWithViaOnlyForStandardCellPin "1:1"
+
+## limit VIAs to ongrid only for VIA1 (S1)
+setNanoRouteMode -drouteOnGridOnly "via 1:1"
+setNanoRouteMode -drouteAutoStop false
+setNanoRouteMode -drouteExpAdvancedMarFix true
+setNanoRouteMode -routeExpAdvancedTechnology true
+
+#SM suggestion for solving long extraction runtime during GR
+setNanoRouteMode -grouteExpWithTimingDriven false
+
+routeDesign
+#route_opt_design
+saveDesign ${encDir}/${DESIGN}_route.enc
+defOut -netlist -floorplan -routing ${DESIGN}_route.def
+
+summaryReport -noHtml -outfile summaryReport/post_route.sum
+saveDesign ${encDir}/${DESIGN}.enc
+defOut -netlist -floorplan -routing ${DESIGN}.def
+
+exit

Testcases/nvdla/rtl/AN2D4PO4.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: AN2D4PO4.v
+module AN2D4PO4(
+A1,
+A2,
+Z
+);
+input A1,A2;
+output Z;
+assign Z = A1 & A2;
+endmodule

Testcases/nvdla/rtl/CKLNQD12.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: CKLNQD12.v
+module CKLNQD12 (
+  TE
+ ,E
+ ,CP
+ ,Q
+ );
+input TE ;
+input E ;
+input CP ;
+output Q ;
+reg qd;
+always @(negedge CP)
+    qd <= TE | E;
+assign Q = CP & qd;
+//PREICG_X1N_A7P5PP60TR_C8 uicg(.E (E), .CK (CP), .SE (TE), .ECK (Q));
+endmodule

Testcases/nvdla/rtl/CKLNQD12PO4.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: CKLNQD12PO4.v
+module CKLNQD12PO4 (
+  TE
+ ,E
+ ,CP
+ ,Q
+ );
+input TE ;
+input E ;
+input CP ;
+output Q ;
+reg qd;
+always @(negedge CP)
+    qd <= TE | E;
+assign Q = CP & qd;
+endmodule

Testcases/nvdla/rtl/LNQD1PO4.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: LNQD1PO4.v
+module LNQD1PO4 (
+  D
+ ,EN
+ ,Q
+ );
+input D ;
+input EN ;
+output Q ;
+reg Q;
+always @(negedge EN)
+    Q <= D;
+endmodule

Testcases/nvdla/rtl/MUX2D4.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: MUX2D4.v
+module MUX2D4 (
+  I0
+ ,I1
+ ,S
+ ,Z
+ );
+input I0 ;
+input I1 ;
+input S ;
+output Z ;
+assign Z = S ? I1 : I0;
+endmodule

Testcases/nvdla/rtl/MUX2HDD2.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: MUX2HDD2.v
+module MUX2HDD2 (
+  I0
+ ,I1
+ ,S
+ ,Z
+ );
+input I0 ;
+input I1 ;
+input S ;
+output Z ;
+assign Z = S ? I1 : I0;
+endmodule

Testcases/nvdla/rtl/NV_BLKBOX_BUFFER.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_BLKBOX_BUFFER.v
+module NV_BLKBOX_BUFFER (
+  Y
+ ,A
+ );
+output Y ;
+input A ;
+assign Y = A;
+endmodule

Testcases/nvdla/rtl/NV_BLKBOX_SINK.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_BLKBOX_SINK.v
+module NV_BLKBOX_SINK (
+  A
+ );
+input A ;
+endmodule

Testcases/nvdla/rtl/NV_BLKBOX_SRC0.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_BLKBOX_SRC0.v
+module NV_BLKBOX_SRC0 (
+  Y
+ );
+output Y ;
+assign Y = 1'b0;
+endmodule

Testcases/nvdla/rtl/NV_BLKBOX_SRC0_X.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_BLKBOX_SRC0_X.v
+module NV_BLKBOX_SRC0_X(
+Y
+);
+output Y;
+assign Y = 1'b0;
+endmodule

Testcases/nvdla/rtl/NV_CLK_gate_power.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_CLK_gate_power.v
+module NV_CLK_gate_power (clk, reset_, clk_en, clk_gated);
+input clk, reset_, clk_en;
+output clk_gated;
+`ifdef VLIB_BYPASS_POWER_CG
+assign clk_gated = clk;
+`else
+CKLNQD12 p_clkgate (.TE(1'b0), .CP(clk), .E(clk_en), .Q(clk_gated));
+`endif // VLIB_BYPASS_POWER_CG
+// the gated clk better not be x after reset
+//
+`ifdef VERILINT
+`else
+// synopsys translate_off
+reg disable_asserts; initial disable_asserts = $test$plusargs( "disable_nv_clk_gate_asserts" ) != 0;
+nv_assert_no_x #(0, 1, 0, "clk_gated is X after reset" )
+    clk_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_gated ) );
+// Above assert is not reliable for catching X on clk_en. See bug 872824.
+nv_assert_no_x #(0, 1, 0, "clk_en is X after reset" )
+    clk_en_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_en ) );
+// synopsys translate_on
+`endif
+endmodule // NV_CLK_gate

Testcases/nvdla/rtl/NV_DW02_tree.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_DW02_tree.v
+module NV_DW02_tree( INPUT, OUT0, OUT1 );
+parameter num_inputs = 8;
+parameter input_width = 8;
+input [num_inputs*input_width-1 : 0] INPUT;
+output [input_width-1:0] OUT0, OUT1;
+reg [input_width-1 : 0] input_array [num_inputs-1 : 0];
+reg [input_width-1 : 0] temp_array [num_inputs-1 : 0];
+reg [input_width-1 : 0] input_slice;
+integer num_in;
+integer i, j;
+always @ (INPUT) begin
+    for (i=0 ; i < num_inputs ; i=i+1) begin
+        for (j=0 ; j < input_width ; j=j+1) begin
+            input_slice[j] = INPUT[i*input_width+j];
+        end
+        input_array[i] = input_slice;
+    end
+    for (num_in = num_inputs; num_in > 2 ; num_in = num_in - (num_in/3)) begin
+        for (i=0 ; i < (num_in/3) ; i = i+1) begin
+            temp_array[i*2] = input_array[i*3] ^ input_array[i*3+1] ^ input_array[i*3+2]; //get partial sum
+            temp_array[i*2+1] = ((input_array[i*3] & input_array[i*3+1]) |(input_array[i*3+1] & input_array[i*3+2]) | (input_array[i*3] & input_array[i*3+2])) << 1; //get shift carry
+        end
+        if ((num_in % 3) > 0) begin
+            for (i=0 ; i < (num_in % 3) ; i = i + 1)
+                temp_array[2 * (num_in/3) + i] = input_array[3 * (num_in/3) + i];
+        end
+        for (i=0 ; i < num_in ; i = i + 1)
+             input_array[i] = temp_array[i]; //update input array.
+    end
+end
+assign OUT0 = input_array[0];
+assign OUT1 = input_array[1];
+endmodule

Testcases/nvdla/rtl/NV_DW_lsd.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_DW_lsd.v
+module NV_DW_lsd (a, dec, enc);
+  parameter a_width = 8;
+  parameter b_width = a_width-1;
+  localparam enc_width = ((a_width>16)?((a_width>64)?((a_width>128)?8:7):((a_width>32)?6:5)):((a_width>4)?((a_width>8)?4:3):((a_width>2)?2:1)));
+  input [a_width-1:0] a;
+  output [a_width-1:0] dec;
+  output [enc_width-1:0] enc;
+//get the encoded output: the number of sign bits.
+function [enc_width-1:0] DWF_lsd_enc (input [a_width-1:0] A);
+  reg [enc_width-1:0] temp_enc;
+  reg [enc_width-1:0] i;
+  reg done;
+  begin
+  done =0;
+  temp_enc = a_width-1;
+  for (i=a_width-2; done==0; i=i-1) begin
+    if (A[i+1] != A[i]) begin
+      temp_enc = a_width - i -2;
+      done =1;
+    end
+    else if(i==0) begin
+        temp_enc = a_width-1;
+        done =1;
+    end
+  end
+  DWF_lsd_enc = temp_enc;
+  end
+endfunction
+//get the sign bit position of input.
+function [a_width-1:0] DWF_lsd (input [a_width-1:0] A);
+  reg [enc_width-1:0] temp_enc;
+  reg [a_width-1:0] temp_dec;
+  reg [enc_width-1:0] temp;
+  temp_enc = DWF_lsd_enc (A);
+  temp_dec = {a_width{1'b0}};
+  temp = b_width - temp_enc;
+  temp_dec[temp] = 1'b1;
+  DWF_lsd = temp_dec;
+endfunction
+assign enc = DWF_lsd_enc (a);
+assign dec = DWF_lsd (a);
+endmodule

Testcases/nvdla/rtl/NV_DW_minmax.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_DW_minmax.v
+module NV_DW_minmax (a ,tc ,min_max ,value ,index);
+  parameter width = 8;
+  parameter num_inputs = 2;
+  localparam index_width = ((num_inputs>8)? ((num_inputs> 32)? 6 : ((num_inputs>16)? 5 : 4)) : ((num_inputs>4)? 3 : ((num_inputs>2)? 2 : 1)));
+  input [num_inputs*width-1 : 0] a;
+  input tc; //dangle, only support unsigned.
+  input min_max;
+  output [width-1 : 0] value;
+  output [index_width-1 : 0] index;
+  reg [width-1 : 0] value;
+  reg [index_width-1 : 0] index;
+  wire tc_NC;
+// synoff nets
+// monitor nets
+// debug nets
+// tie high nets
+// tie low nets
+// no connect nets
+// not all bits used nets
+// todo nets
+  assign tc_NC = tc;
+  function [width-1 : 0] max_unsigned_value;
+    input [num_inputs*width-1 : 0] a;
+    reg [width-1 : 0] a_v;
+    reg [width-1 : 0] value_v;
+    reg [index_width : 0] k;
+    begin
+ value_v = {width{1'b0}};
+ for (k = 0; k < num_inputs; k = k+1) begin
+     a_v = a[width-1 : 0];
+     a = a >> width;
+     if (a_v >= value_v) begin
+         value_v = a_v;
+     end
+ end
+ max_unsigned_value = value_v;
+    end
+  endfunction
+    function [index_width-1 : 0] max_unsigned_index;
+        input [num_inputs*width-1 : 0] a;
+        reg [width-1 : 0] a_v;
+        reg [index_width-1 : 0] index_v;
+        reg [width-1 : 0] value_v;
+        reg [index_width : 0] k;
+        begin
+     value_v = {width{1'b0}};
+     index_v = {index_width{1'b0}};
+     for (k = 0; k < num_inputs; k = k+1) begin
+         a_v = a[width-1 : 0];
+         a = a >> width;
+         if (a_v >= value_v) begin
+             value_v = a_v;
+             index_v = k[index_width-1 : 0];
+         end
+     end
+     max_unsigned_index = index_v;
+        end
+    endfunction
+  function [width-1 : 0] min_unsigned_value;
+    input [num_inputs*width-1 : 0] a;
+    reg [width-1 : 0] a_v;
+    reg [width-1 : 0] value_v;
+    reg [index_width : 0] k;
+ begin
+    value_v = {width{1'b1}};
+ for (k = 0; k < num_inputs; k = k+1) begin
+     a_v = a[width-1 : 0];
+     a = a >> width;
+     if (a_v < value_v) begin
+         value_v = a_v;
+     end
+ end
+ min_unsigned_value = value_v;
+    end
+  endfunction
+  function [index_width-1 : 0] min_unsigned_index;
+    input [num_inputs*width-1 : 0] a;
+    reg [width-1 : 0] a_v;
+    reg [width-1 : 0] value_v;
+    reg [index_width-1 : 0] index_v;
+    reg [index_width : 0] k;
+ begin
+    value_v = {width{1'b1}};
+ index_v = {index_width{1'b0}};
+ for (k = 0; k < num_inputs; k = k+1) begin
+     a_v = a[width-1 : 0];
+     a = a >> width;
+     if (a_v < value_v) begin
+         value_v = a_v;
+         index_v = k[index_width-1 : 0];
+     end
+ end
+ min_unsigned_index = index_v;
+    end
+  endfunction
+  always @(a or min_max) begin
+        if (min_max == 1'b0) begin
+         value = min_unsigned_value (a);
+         index = min_unsigned_index (a);
+        end
+     else begin
+         value = max_unsigned_value (a);
+         index = max_unsigned_index (a);
+        end
+  end
+endmodule

Testcases/nvdla/rtl/NV_HWACC_NVDLA_tick_defines.vh

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_HWACC_NVDLA_tick_defines.vh
+//`include "NV_HWACC_common_tick_defines.vh"
+`ifndef NV_HWACC_NVDLA_tick_defines_vh
+`define NV_HWACC_NVDLA_tick_defines_vh
+//this section contains IP specific defines
+`ifdef NV_FPGA_SYSTEM
+`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU
+`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU
+`endif
+`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA
+`define NV_HWACC_NVDLA_SFPGA_UFPGA
+`endif
+`ifndef NV_HWACC_NVDLA_SFPGA_EMU
+`define NV_HWACC_NVDLA_SFPGA_EMU
+`endif
+`endif
+`ifdef NV_FPGA_UNIT
+`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU
+`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU
+`endif
+`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA
+`define NV_HWACC_NVDLA_SFPGA_UFPGA
+`endif
+`ifndef NV_HWACC_NVDLA_UFPGA_EMU
+`define NV_HWACC_NVDLA_UFPGA_EMU
+`endif
+`endif
+`ifdef NV_EMULATION
+`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU
+`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU
+`endif
+`ifndef NV_HWACC_NVDLA_SFPGA_EMU
+`define NV_HWACC_NVDLA_SFPGA_EMU
+`endif
+`ifndef NV_HWACC_NVDLA_UFPGA_EMU
+`define NV_HWACC_NVDLA_UFPGA_EMU
+`endif
+`endif
+//DEFINES
+//defines shared between system fpga and unit fpga and emulation
+`ifdef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU
+//add defines here
+`endif
+//defines shared between system fpga and unit fpga
+`ifdef NV_HWACC_NVDLA_SFPGA_UFPGA
+//add defines here
+`endif
+//defines shared between system fpga and emulation
+`ifdef NV_HWACC_NVDLA_SFPGA_EMU
+//add defines here
+`endif
+//defines shared between unit fpga and emulation
+`ifdef NV_HWACC_NVDLA_UFPGA_EMU
+//add defines here
+`endif
+//defines used only in system fpga
+`ifdef NV_FPGA_SYSTEM
+//add defines here
+`endif
+//defines used only in unit fpga
+`ifdef NV_FPGA_UNIT
+//add defines here
+`endif
+//defines used only in emulation
+`ifdef NV_EMULATION
+//add defines here
+`endif
+`endif //NV_HWACC_NVDLA_tick_defines_vh

Testcases/nvdla/rtl/NV_NVDLA_CACC_CALC_int8.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CACC_CALC_int8.v
+module NV_NVDLA_CACC_CALC_int8 (
+   nvdla_core_clk
+  ,nvdla_core_rstn
+  ,cfg_truncate
+  ,in_data
+  ,in_op
+  ,in_op_valid
+  ,in_sel
+  ,in_valid
+  ,out_final_data
+  ,out_final_sat
+  ,out_final_valid
+  ,out_partial_data
+  ,out_partial_valid
+  );
+input [4:0] cfg_truncate;
+input [21:0] in_data;
+input [33:0] in_op;
+input in_op_valid;
+input in_sel;
+input in_valid;
+output [31:0] out_final_data;
+output out_final_sat;
+output out_final_valid;
+output [33:0] out_partial_data;
+output out_partial_valid;
+input nvdla_core_clk;
+input nvdla_core_rstn;
+reg [32:0] i_sat_bits;
+reg i_sat_sel;
+reg i_sat_vld;
+reg [34:0] i_sum_pd;
+reg [31:0] out_final_data;
+reg out_final_sat;
+reg out_final_valid;
+reg [33:0] out_partial_data;
+reg out_partial_valid;
+wire [21:0] di_pd;
+wire [31:0] i_final_result;
+wire i_final_vld;
+wire i_guide;
+wire [33:0] i_partial_result;
+wire i_partial_vld;
+wire i_point5;
+wire [31:0] i_pos_pd;
+wire [33:0] i_pre_sft_pd;
+wire [33:0] i_sat_pd;
+wire i_sat_sign;
+wire i_sel;
+wire [31:0] i_sft_max;
+wire i_sft_need_sat;
+wire [33:0] i_sft_pd;
+wire [14:0] i_stick;
+wire i_sum_msb;
+wire [34:0] i_sum_pd_nxt;
+wire i_sum_sign;
+wire [31:0] i_tru_pd;
+wire i_vld;
+wire [33:0] in_mask_op;
+wire mon_pos_pd_c;
+wire [33:0] oi_pd;
+assign i_sel = in_sel;
+assign i_vld = in_valid;
+assign in_mask_op = in_op_valid ? in_op[33:0] : 34'b0;
+assign di_pd = in_data[21:0];
+assign oi_pd = in_mask_op[33:0];
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    i_sat_vld <= 1'b0;
+  end else begin
+  i_sat_vld <= i_vld;
+  end
+end
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    i_sat_sel <= 1'b0;
+  end else begin
+  if ((i_vld) == 1'b1) begin
+    i_sat_sel <= i_sel;
+// VCS coverage off
+  end else if ((i_vld) == 1'b0) begin
+  end else begin
+    i_sat_sel <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number)
+// VCS coverage on
+  end
+  end
+end
+//====================
+// Addition
+//====================
+assign i_sum_pd_nxt[34:0] = $signed(di_pd) + $signed(oi_pd);
+always @(posedge nvdla_core_clk) begin
+  if ((i_vld) == 1'b1) begin
+    i_sum_pd <= i_sum_pd_nxt;
+// VCS coverage off
+  end else if ((i_vld) == 1'b0) begin
+  end else begin
+    i_sum_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number)
+// VCS coverage on
+  end
+end
+//====================
+// narrow down to 34bit, and need satuation only
+//====================
+assign i_sum_sign = i_sum_pd[34 +1 -1];
+assign i_sum_msb = i_sum_pd[34 +1 -2];
+assign i_sat_sign = i_sum_sign;
+always @(
+  i_sum_sign
+  or i_sum_msb
+  or i_sum_pd
+  ) begin
+    if (i_sum_sign ^ i_sum_msb) begin // overflow, need satuation
+        i_sat_bits = {33{~i_sum_sign}};
+    end else begin
+        i_sat_bits = i_sum_pd[32:0];
+    end
+end
+assign i_sat_pd = {i_sat_sign,i_sat_bits};
+assign i_partial_result = i_sat_pd;
+//====================
+// narrow down to 32bit, and need rounding and satuation
+//====================
+assign i_pre_sft_pd = i_sat_sel ? i_sat_pd[33:0] : {34{1'b0}};
+assign {i_sft_pd[33:0], i_guide, i_stick[14:0]} = ($signed({i_pre_sft_pd, 16'b0}) >>> cfg_truncate);
+assign i_sft_need_sat = (i_sat_sign & ~(&i_sft_pd[32:31])) |
+                        (~i_sat_sign & (|i_sft_pd[32:31])) |
+                        (~i_sat_sign & (&{i_sft_pd[30:0], i_point5}));
+assign i_sft_max = i_sat_sign ? {1'b1, 31'b0} : ~{1'b1, 31'b0};
+assign i_point5 = i_sat_sel & i_guide & (~i_sat_sign | (|i_stick));
+assign {mon_pos_pd_c, i_pos_pd[31:0]} = i_sft_pd[31:0] + i_point5;
+assign i_tru_pd = i_pos_pd;
+assign i_final_result = i_sft_need_sat ? i_sft_max : i_tru_pd;
+assign i_partial_vld = i_sat_vld & ~i_sat_sel;
+assign i_final_vld = i_sat_vld & i_sat_sel;
+//====================
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    out_partial_valid <= 1'b0;
+  end else begin
+  out_partial_valid <= i_partial_vld;
+  end
+end
+// spyglass disable_block STARC05-3.3.1.4b
+always @(posedge nvdla_core_clk) begin
+  if ((i_partial_vld) == 1'b1) begin
+    out_partial_data <= i_partial_result;
+// VCS coverage off
+  end else if ((i_partial_vld) == 1'b0) begin
+  end else begin
+    out_partial_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number)
+// VCS coverage on
+  end
+end
+// spyglass enable_block STARC05-3.3.1.4b
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    out_final_valid <= 1'b0;
+  end else begin
+  out_final_valid <= i_final_vld;
+  end
+end
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    out_final_sat <= 1'b0;
+  end else begin
+  out_final_sat <= i_final_vld & i_sft_need_sat;
+  end
+end
+// spyglass disable_block STARC05-3.3.1.4b
+always @(posedge nvdla_core_clk) begin
+  if ((i_final_vld) == 1'b1) begin
+    out_final_data <= i_final_result;
+// VCS coverage off
+  end else if ((i_final_vld) == 1'b0) begin
+  end else begin
+    out_final_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number)
+// VCS coverage on
+  end
+end
+// spyglass enable_block STARC05-3.3.1.4b
+//VCS coverage off
+`ifndef DISABLE_FUNCPOINT
+  `ifdef ENABLE_FUNCPOINT
+    reg funcpoint_cover_off;
+    initial begin
+        if ( $test$plusargs( "cover_off" ) ) begin
+            funcpoint_cover_off = 1'b1;
+        end else begin
+            funcpoint_cover_off = 1'b0;
+        end
+    end
+    property cacc_calc_int8__partial_sum_need_sat__0_cov;
+        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
+        @(posedge nvdla_core_clk)
+        i_sum_sign ^ i_sum_msb;
+    endproperty
+// Cover 0 : "i_sum_sign ^ i_sum_msb"
+    FUNCPOINT_cacc_calc_int8__partial_sum_need_sat__0_COV : cover property (cacc_calc_int8__partial_sum_need_sat__0_cov);
+  `endif
+`endif
+//VCS coverage on
+//VCS coverage off
+`ifndef DISABLE_FUNCPOINT
+  `ifdef ENABLE_FUNCPOINT
+    property cacc_calc_int8__out32_need_sat_pos__1_cov;
+        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
+        @(posedge nvdla_core_clk)
+        i_sft_need_sat & ~i_sat_sign & ~i_point5;
+    endproperty
+// Cover 1 : "i_sft_need_sat & ~i_sat_sign & ~i_point5"
+    FUNCPOINT_cacc_calc_int8__out32_need_sat_pos__1_COV : cover property (cacc_calc_int8__out32_need_sat_pos__1_cov);
+  `endif
+`endif
+//VCS coverage on
+//VCS coverage off
+`ifndef DISABLE_FUNCPOINT
+  `ifdef ENABLE_FUNCPOINT
+    property cacc_calc_int8__out32_round_need_sat_pos__2_cov;
+        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
+        @(posedge nvdla_core_clk)
+        i_sft_need_sat & ~i_sat_sign & i_point5;
+    endproperty
+// Cover 2 : "i_sft_need_sat & ~i_sat_sign & i_point5"
+    FUNCPOINT_cacc_calc_int8__out32_round_need_sat_pos__2_COV : cover property (cacc_calc_int8__out32_round_need_sat_pos__2_cov);
+  `endif
+`endif
+//VCS coverage on
+//VCS coverage off
+`ifndef DISABLE_FUNCPOINT
+  `ifdef ENABLE_FUNCPOINT
+    property cacc_calc_int8__out32_round_need_sat_neg__3_cov;
+        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
+        @(posedge nvdla_core_clk)
+        i_sft_need_sat & i_sat_sign;
+    endproperty
+// Cover 3 : "i_sft_need_sat & i_sat_sign"
+    FUNCPOINT_cacc_calc_int8__out32_round_need_sat_neg__3_COV : cover property (cacc_calc_int8__out32_round_need_sat_neg__3_cov);
+  `endif
+`endif
+//VCS coverage on
+endmodule // NV_NVDLA_CACC_CALC_int8

Testcases/nvdla/rtl/NV_NVDLA_CACC_assembly_buffer.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CACC_assembly_buffer.v
+// ================================================================
+// NVDLA Open Source Project
+// 
+// Copyright(c) 2016 - 2017 NVIDIA Corporation.  Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with 
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CACC.h
+module NV_NVDLA_CACC_assembly_buffer (
+   nvdla_core_clk //|< i
+  ,nvdla_core_rstn //|< i
+  ,abuf_rd_addr //|< i
+  ,abuf_rd_en //|< i
+  ,abuf_wr_addr //|< i
+  ,abuf_wr_data //|< i
+  ,abuf_wr_en //|< i
+  ,pwrbus_ram_pd //|< i
+  ,abuf_rd_data //|> o
+  );
+input nvdla_core_clk;
+input nvdla_core_rstn;
+input [3 +1 -1:0] abuf_rd_addr;
+input abuf_rd_en;
+input [3 +1 -1:0] abuf_wr_addr;
+input [34*8 -1:0] abuf_wr_data;
+input abuf_wr_en;
+input [31:0] pwrbus_ram_pd;
+output [34*8 -1:0] abuf_rd_data;
+// spyglass disable_block NoWidthInBasedNum-ML
+// instance SRAM
+wire [34*8 -1:0] abuf_rd_data_ecc;
+wire [3 +1 -1:0] abuf_rd_addr;
+//: my $dep= 8*2;
+//: my $wid= 34*8;
+//: print qq(
+//: nv_ram_rws_${dep}x${wid} u_accu_abuf_0 (
+//: .clk (nvdla_core_clk) //|< i
+//: ,.ra (abuf_rd_addr) //|< i
+//: ,.re (abuf_rd_en) //|< i
+//: ,.dout (abuf_rd_data_ecc) //|> w
+//: ,.wa (abuf_wr_addr) //|< r
+//: ,.we (abuf_wr_en) //|< r
+//: ,.di (abuf_wr_data) //|< r
+//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
+//: );
+//: );
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+
+nv_ram_rws_16x272 u_accu_abuf_0 (
+.clk (nvdla_core_clk) //|< i
+,.ra (abuf_rd_addr) //|< i
+,.re (abuf_rd_en) //|< i
+,.dout (abuf_rd_data_ecc) //|> w
+,.wa (abuf_wr_addr) //|< r
+,.we (abuf_wr_en) //|< r
+,.di (abuf_wr_data) //|< r
+,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
+);
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+// 1 pipe for sram read data.
+//: &eperl::flop("-q abuf_rd_en_d1 -d \"abuf_rd_en\" -clk nvdla_core_clk -rst nvdla_core_rstn");
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+reg  abuf_rd_en_d1;
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       abuf_rd_en_d1 <= 'b0;
+   end else begin
+       abuf_rd_en_d1 <= abuf_rd_en;
+   end
+end
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+wire [34*8 -1:0] abuf_rd_raw_data = abuf_rd_data_ecc;
+// spygalss disable_block STARC-2.10.1.6
+// spyglass disable_block STARC05-3.3.1.4b
+//: my $kk=34*8;
+//: &eperl::flop("-wid ${kk} -norst -q abuf_rd_raw_data_d1 -en \"abuf_rd_en_d1\" -d \"abuf_rd_raw_data\" -clk nvdla_core_clk");
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+reg [271:0] abuf_rd_raw_data_d1;
+always @(posedge nvdla_core_clk) begin
+       if ((abuf_rd_en_d1) == 1'b1) begin
+           abuf_rd_raw_data_d1 <= abuf_rd_raw_data;
+       // VCS coverage off
+       end else if ((abuf_rd_en_d1) == 1'b0) begin
+       end else begin
+           abuf_rd_raw_data_d1 <= 'bx;
+       // VCS coverage on
+       end
+end
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+// spyglass enable_block NoWidthInBasedNum-ML
+// spyglass enable_block STARC-2.10.1.6
+// spyglass enable_block STARC05-3.3.1.4b
+assign abuf_rd_data = abuf_rd_raw_data_d1;
+endmodule // NV_NVDLA_CACC_assembly_buffer

Testcases/nvdla/rtl/NV_NVDLA_CACC_delivery_buffer.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CACC_delivery_buffer.v
+// ================================================================
+// NVDLA Open Source Project
+// 
+// Copyright(c) 2016 - 2017 NVIDIA Corporation.  Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with 
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CACC.h
+module NV_NVDLA_CACC_delivery_buffer (
+   nvdla_core_clk //|< i
+  ,nvdla_core_rstn //|< i
+  ,cacc2sdp_ready //|< i
+  ,dbuf_rd_addr //|< i
+  ,dbuf_rd_en //|< i
+  ,dbuf_rd_layer_end //|< i
+  ,dbuf_wr_addr //|< i
+  ,dbuf_wr_data //|< i
+  ,dbuf_wr_en //|< i
+  ,pwrbus_ram_pd //|< i
+  ,cacc2glb_done_intr_pd //|> o
+  ,cacc2sdp_pd //|> o
+  ,cacc2sdp_valid //|> o
+  ,dbuf_rd_ready //|> o
+  ,accu2sc_credit_size //|> o
+  ,accu2sc_credit_vld //|> o
+  );
+input nvdla_core_clk;
+input nvdla_core_rstn;
+input cacc2sdp_ready;
+input [3 +1 -1:0] dbuf_rd_addr;
+input dbuf_rd_en;
+input dbuf_rd_layer_end;
+input [3 +1 -1:0] dbuf_wr_addr;
+input [32*8 -1:0] dbuf_wr_data;
+input dbuf_wr_en;
+input [31:0] pwrbus_ram_pd;
+output [1:0] cacc2glb_done_intr_pd;
+output [32*1 +2 -1:0] cacc2sdp_pd;
+output cacc2sdp_valid;
+output dbuf_rd_ready;
+output [2:0] accu2sc_credit_size;
+output accu2sc_credit_vld;
+// Instance RAMs
+wire [32*8 -1:0] dbuf_rd_data;
+reg [(32*8)/(32*1)-1:0] data_left_mask;
+wire dbuf_rd_en_new = ~(|data_left_mask) & dbuf_rd_en;
+// spyglass disable_block NoWidthInBasedNum-ML
+//: my $dep= 8*2;
+//: my $wid= 32*8;
+//: print qq(
+//: nv_ram_rws_${dep}x${wid} u_accu_dbuf (
+//: .clk (nvdla_core_clk) //|< i
+//: ,.ra (dbuf_rd_addr) //|< r
+//: ,.re (dbuf_rd_en_new) //|< r
+//: ,.dout (dbuf_rd_data) //|> w
+//: ,.wa (dbuf_wr_addr) //|< r
+//: ,.we (dbuf_wr_en) //|< r
+//: ,.di (dbuf_wr_data) //|< r
+//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
+//: );
+//: );
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+
+nv_ram_rws_16x256 u_accu_dbuf (
+.clk (nvdla_core_clk) //|< i
+,.ra (dbuf_rd_addr) //|< r
+,.re (dbuf_rd_en_new) //|< r
+,.dout (dbuf_rd_data) //|> w
+,.wa (dbuf_wr_addr) //|< r
+,.we (dbuf_wr_en) //|< r
+,.di (dbuf_wr_data) //|< r
+,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
+);
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+//get signal for SDP
+//: &eperl::flop("-q  dbuf_rd_valid  -d \"dbuf_rd_en_new\" -clk nvdla_core_clk -rst nvdla_core_rstn ");
+//: my $kk=(32*8)/(32*1);
+//: print qq(
+//: reg [${kk}-1:0] rd_data_mask; //which data to be fetched by sdp.
+//: wire [${kk}-1:0] rd_data_mask_pre; );
+//: if(${kk}>=2){
+//: print "assign rd_data_mask_pre = cacc2sdp_valid & cacc2sdp_ready ? {rd_data_mask[${kk}-2:0],rd_data_mask[${kk}-1]} : rd_data_mask; \n";
+//: } else {
+//: print "assign rd_data_mask_pre = rd_data_mask; \n";
+//:}
+//: &eperl::flop("-nodeclare -q rd_data_mask -d rd_data_mask_pre -rval \" 'b1\" ");
+//: print qq(
+//: wire [${kk}-1:0] data_left_mask_pre = dbuf_rd_en_new ? {${kk}{1'b1}} : (cacc2sdp_valid & cacc2sdp_ready) ? (data_left_mask<<1'b1) : data_left_mask;
+//: );
+//: &eperl::flop("-nodeclare -q data_left_mask   -d data_left_mask_pre ");
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+reg  dbuf_rd_valid;
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       dbuf_rd_valid <= 'b0;
+   end else begin
+       dbuf_rd_valid <= dbuf_rd_en_new;
+   end
+end
+
+reg [8-1:0] rd_data_mask; //which data to be fetched by sdp.
+wire [8-1:0] rd_data_mask_pre; assign rd_data_mask_pre = cacc2sdp_valid & cacc2sdp_ready ? {rd_data_mask[8-2:0],rd_data_mask[8-1]} : rd_data_mask; 
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       rd_data_mask <=  'b1;
+   end else begin
+       rd_data_mask <= rd_data_mask_pre;
+   end
+end
+
+wire [8-1:0] data_left_mask_pre = dbuf_rd_en_new ? {8{1'b1}} : (cacc2sdp_valid & cacc2sdp_ready) ? (data_left_mask<<1'b1) : data_left_mask;
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       data_left_mask <= 'b0;
+   end else begin
+       data_left_mask <= data_left_mask_pre;
+   end
+end
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+wire cacc2sdp_valid = (|data_left_mask);
+wire dbuf_rd_ready = ~(|data_left_mask);
+//: my $t1="";
+//: my $kk= 32*1;
+//: print "wire [${kk}-1:0] cacc2sdp_pd_data= ";
+//: for (my $i=0; $i<(32*8)/(32*1); $i++){
+//: $t1 .= "dbuf_rd_data[($i+1)*${kk}-1:$i*${kk}]&{${kk}{rd_data_mask[${i}]}} |";
+//: }
+//: my $t2= "{${kk}{1'b0}}";
+//: print "$t1"."$t2".";\n";
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+wire [32-1:0] cacc2sdp_pd_data= dbuf_rd_data[(0+1)*32-1:0*32]&{32{rd_data_mask[0]}} |dbuf_rd_data[(1+1)*32-1:1*32]&{32{rd_data_mask[1]}} |dbuf_rd_data[(2+1)*32-1:2*32]&{32{rd_data_mask[2]}} |dbuf_rd_data[(3+1)*32-1:3*32]&{32{rd_data_mask[3]}} |dbuf_rd_data[(4+1)*32-1:4*32]&{32{rd_data_mask[4]}} |dbuf_rd_data[(5+1)*32-1:5*32]&{32{rd_data_mask[5]}} |dbuf_rd_data[(6+1)*32-1:6*32]&{32{rd_data_mask[6]}} |dbuf_rd_data[(7+1)*32-1:7*32]&{32{rd_data_mask[7]}} |{32{1'b0}};
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+//layer_end handle
+reg dbuf_rd_layer_end_latch;
+wire dbuf_rd_layer_end_latch_w = dbuf_rd_layer_end? 1'b1 : ~(|data_left_mask) ? 1'b0 : dbuf_rd_layer_end_latch;
+//: &eperl::flop("-q dbuf_rd_layer_end_latch -d dbuf_rd_layer_end_latch_w -nodeclare");
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       dbuf_rd_layer_end_latch <= 'b0;
+   end else begin
+       dbuf_rd_layer_end_latch <= dbuf_rd_layer_end_latch_w;
+   end
+end
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+////regout to SDP
+////: my $kk=CACC_SDP_DATA_WIDTH;
+////: &eperl::flop("-q cacc2sdp_valid -d cacc2sdp_valid_w");
+////: &eperl::flop("-wid ${kk} -q cacc2sdp_pd_data -d cacc2sdp_pd_data_w");
+wire last_data;
+wire cacc2sdp_batch_end = 1'b0;
+wire cacc2sdp_layer_end = dbuf_rd_layer_end_latch&last_data&cacc2sdp_valid&cacc2sdp_ready; //data_left_mask=0;
+assign cacc2sdp_pd[32*1 -1:0] = cacc2sdp_pd_data;
+assign cacc2sdp_pd[32*1 +2 -2] = cacc2sdp_batch_end;
+assign cacc2sdp_pd[32*1 +2 -1] = cacc2sdp_layer_end;
+// generate CACC done interrupt
+wire [1:0] cacc_done_intr_w;
+reg intr_sel;
+wire cacc_done = cacc2sdp_valid & cacc2sdp_ready & cacc2sdp_layer_end;
+assign cacc_done_intr_w[0] = cacc_done & ~intr_sel;
+assign cacc_done_intr_w[1] = cacc_done & intr_sel;
+wire intr_sel_w = cacc_done ? ~intr_sel : intr_sel;
+//: &eperl::flop("-nodeclare -q  intr_sel  -d \"intr_sel_w \" -clk nvdla_core_clk -rst nvdla_core_rstn ");
+//: &eperl::flop(" -q  cacc_done_intr  -d \"cacc_done_intr_w \" -wid 2  -clk nvdla_core_clk -rst nvdla_core_rstn ");
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       intr_sel <= 'b0;
+   end else begin
+       intr_sel <= intr_sel_w ;
+   end
+end
+reg [1:0] cacc_done_intr;
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       cacc_done_intr <= 'b0;
+   end else begin
+       cacc_done_intr <= cacc_done_intr_w ;
+   end
+end
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+assign cacc2glb_done_intr_pd = cacc_done_intr;
+///// generate credit signal
+assign accu2sc_credit_size = 3'h1;
+assign last_data = (data_left_mask=={1'b1,{(32*8)/(32*1)-1{1'b0}}});
+//: &eperl::flop(" -q  accu2sc_credit_vld  -d \"cacc2sdp_valid & cacc2sdp_ready & last_data\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0");
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+reg  accu2sc_credit_vld;
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+   if (!nvdla_core_rstn) begin
+       accu2sc_credit_vld <= 'b0;
+   end else begin
+       accu2sc_credit_vld <= cacc2sdp_valid & cacc2sdp_ready & last_data;
+   end
+end
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+// spyglass enable_block NoWidthInBasedNum-ML
+endmodule // NV_NVDLA_CACC_delivery_buffer

Testcases/nvdla/rtl/NV_NVDLA_CACC_single_reg.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CACC_single_reg.v
+module NV_NVDLA_CACC_single_reg (
+   reg_rd_data
+  ,reg_offset
+// verilint 498 off
+// leda UNUSED_DEC off
+  ,reg_wr_data
+// verilint 498 on
+// leda UNUSED_DEC on
+  ,reg_wr_en
+  ,nvdla_core_clk
+  ,nvdla_core_rstn
+  ,producer
+  ,consumer
+  ,status_0
+  ,status_1
+  );
+wire [31:0] nvdla_cacc_s_pointer_0_out;
+wire [31:0] nvdla_cacc_s_status_0_out;
+wire [11:0] reg_offset_rd_int;
+wire [31:0] reg_offset_wr;
+// Register control interface
+output [31:0] reg_rd_data;
+input [11:0] reg_offset;
+input [31:0] reg_wr_data; //(UNUSED_DEC)
+input reg_wr_en;
+input nvdla_core_clk;
+input nvdla_core_rstn;
+// Writable register flop/trigger outputs
+output producer;
+// Read-only register inputs
+input consumer;
+input [1:0] status_0;
+input [1:0] status_1;
+// wr_mask register inputs
+// rstn register inputs
+// leda FM_2_23 off
+reg arreggen_abort_on_invalid_wr;
+reg arreggen_abort_on_rowr;
+reg arreggen_dump;
+// leda FM_2_23 on
+reg producer;
+reg [31:0] reg_rd_data;
+assign reg_offset_wr = {20'b0 , reg_offset};
+// SCR signals
+// Address decode
+wire nvdla_cacc_s_pointer_0_wren = (reg_offset_wr == (32'h9004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
+wire nvdla_cacc_s_status_0_wren = (reg_offset_wr == (32'h9000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
+assign nvdla_cacc_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer };
+assign nvdla_cacc_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 };
+assign reg_offset_rd_int = reg_offset;
+// Output mux
+//spyglass disable_block W338, W263
+always @(
+  reg_offset_rd_int
+  or nvdla_cacc_s_pointer_0_out
+  or nvdla_cacc_s_status_0_out
+  ) begin
+  case (reg_offset_rd_int)
+     (32'h9004 & 32'h00000fff): begin
+                            reg_rd_data = nvdla_cacc_s_pointer_0_out ;
+                            end
+     (32'h9000 & 32'h00000fff): begin
+                            reg_rd_data = nvdla_cacc_s_status_0_out ;
+                            end
+    default: reg_rd_data = {32{1'b0}};
+  endcase
+end
+//spyglass enable_block W338, W263
+// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443
+// Register flop declarations
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    producer <= 1'b0;
+  end else begin
+// Not generating flops for read-only field NVDLA_CACC_S_POINTER_0::consumer
+// Register: NVDLA_CACC_S_POINTER_0 Field: producer
+  if (nvdla_cacc_s_pointer_0_wren) begin
+    producer <= reg_wr_data[0];
+  end
+// Not generating flops for read-only field NVDLA_CACC_S_STATUS_0::status_0
+// Not generating flops for read-only field NVDLA_CACC_S_STATUS_0::status_1
+  end
+end
+// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443
+// synopsys translate_off
+// VCS coverage off
+initial begin
+  arreggen_dump = $test$plusargs("arreggen_dump_wr");
+  arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr");
+  arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr");
+`ifdef VERILATOR
+`else
+  $timeformat(-9, 2, "ns", 15);
+`endif
+end
+always @(posedge nvdla_core_clk) begin
+  if (reg_wr_en) begin
+    case(reg_offset)
+      (32'h9004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_s_pointer_0_out, nvdla_cacc_s_pointer_0_out);
+      (32'h9000 & 32'h00000fff): begin
+          if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CACC_S_STATUS_0 = 0x%h", $time, reg_wr_data);
+          if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end
+        end
+      default: begin
+          if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data);
+          if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end
+        end
+    endcase
+  end
+end
+// VCS coverage on
+// synopsys translate_on
+endmodule // NV_NVDLA_CACC_single_reg

Testcases/nvdla/rtl/NV_NVDLA_CDMA_WT_sp_arb.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CDMA_WT_sp_arb.v
+`include "simulate_x_tick.vh"
+module NV_NVDLA_CDMA_WT_sp_arb (
+   req0
+  ,req1
+  ,gnt_busy
+  ,gnt0
+  ,gnt1
+  );
+//Declaring ports
+input req0;
+input req1;
+input gnt_busy;
+output gnt0;
+output gnt1;
+//Declaring registers and wires
+reg [1:0] gnt;
+reg [1:0] gnt_pre;
+wire [1:0] req;
+assign req = {
+ req1
+,req0
+};
+assign {
+ gnt1
+,gnt0
+} = gnt;
+always @(
+  gnt_busy
+  or gnt_pre
+  ) begin
+    gnt = {2{!gnt_busy}} & gnt_pre;
+end
+// verilint 69 off - Case statement without default clause, but all the cases are covered
+// verilint 71 off - Case statement without default clause
+// verilint 264 off - Not all possible cases covered
+always @(
+  req
+  ) begin
+    gnt_pre = 2'd0;
+    casez (req)
+        2'b?1: begin
+            gnt_pre[0] = 1'b1;
+        end
+        2'b10: begin
+            gnt_pre[1] = 1'b1;
+        end
+        2'b00: begin
+            gnt_pre = 2'd0;
+        end
+//VCS coverage off
+            default : begin
+                        gnt_pre[1:0] = {2{`x_or_0}};
+                      end
+//VCS coverage on
+    endcase
+end
+// verilint 69 on - Case statement without default clause, but all the cases are covered
+// verilint 71 on - Case statement without default clause
+// verilint 264 on - Not all possible cases covered
+endmodule // NV_NVDLA_CDMA_WT_sp_arb

Testcases/nvdla/rtl/NV_NVDLA_CDMA_single_reg.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CDMA_single_reg.v
+module NV_NVDLA_CDMA_single_reg (
+   reg_rd_data
+  ,reg_offset
+// verilint 498 off
+// leda UNUSED_DEC off
+  ,reg_wr_data
+// verilint 498 on
+// leda UNUSED_DEC on
+  ,reg_wr_en
+  ,nvdla_core_clk
+  ,nvdla_core_rstn
+  ,arb_weight
+  ,arb_wmb
+  ,producer
+  ,flush_done
+  ,consumer
+  ,status_0
+  ,status_1
+  );
+wire [31:0] nvdla_cdma_s_arbiter_0_out;
+wire [31:0] nvdla_cdma_s_cbuf_flush_status_0_out;
+wire [31:0] nvdla_cdma_s_pointer_0_out;
+wire [31:0] nvdla_cdma_s_status_0_out;
+wire [11:0] reg_offset_rd_int;
+wire [31:0] reg_offset_wr;
+// Register control interface
+output [31:0] reg_rd_data;
+input [11:0] reg_offset;
+input [31:0] reg_wr_data; //(UNUSED_DEC)
+input reg_wr_en;
+input nvdla_core_clk;
+input nvdla_core_rstn;
+// Writable register flop/trigger outputs
+output [3:0] arb_weight;
+output [3:0] arb_wmb;
+output producer;
+// Read-only register inputs
+input flush_done;
+input consumer;
+input [1:0] status_0;
+input [1:0] status_1;
+// wr_mask register inputs
+// rstn register inputs
+reg [3:0] arb_weight;
+reg [3:0] arb_wmb;
+// leda FM_2_23 off
+reg arreggen_abort_on_invalid_wr;
+reg arreggen_abort_on_rowr;
+reg arreggen_dump;
+// leda FM_2_23 on
+reg producer;
+reg [31:0] reg_rd_data;
+assign reg_offset_wr = {20'b0 , reg_offset};
+// SCR signals
+// Address decode
+wire nvdla_cdma_s_arbiter_0_wren = (reg_offset_wr == (32'h5008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
+wire nvdla_cdma_s_cbuf_flush_status_0_wren = (reg_offset_wr == (32'h500c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
+wire nvdla_cdma_s_pointer_0_wren = (reg_offset_wr == (32'h5004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
+wire nvdla_cdma_s_status_0_wren = (reg_offset_wr == (32'h5000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
+assign nvdla_cdma_s_arbiter_0_out[31:0] = { 12'b0, arb_wmb, 12'b0, arb_weight };
+assign nvdla_cdma_s_cbuf_flush_status_0_out[31:0] = { 31'b0, flush_done };
+assign nvdla_cdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer };
+assign nvdla_cdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 };
+assign reg_offset_rd_int = reg_offset;
+// Output mux
+//spyglass disable_block W338, W263
+always @(
+  reg_offset_rd_int
+  or nvdla_cdma_s_arbiter_0_out
+  or nvdla_cdma_s_cbuf_flush_status_0_out
+  or nvdla_cdma_s_pointer_0_out
+  or nvdla_cdma_s_status_0_out
+  ) begin
+  case (reg_offset_rd_int)
+     (32'h5008 & 32'h00000fff): begin
+                            reg_rd_data = nvdla_cdma_s_arbiter_0_out ;
+                            end
+     (32'h500c & 32'h00000fff): begin
+                            reg_rd_data = nvdla_cdma_s_cbuf_flush_status_0_out ;
+                            end
+     (32'h5004 & 32'h00000fff): begin
+                            reg_rd_data = nvdla_cdma_s_pointer_0_out ;
+                            end
+     (32'h5000 & 32'h00000fff): begin
+                            reg_rd_data = nvdla_cdma_s_status_0_out ;
+                            end
+    default: reg_rd_data = {32{1'b0}};
+  endcase
+end
+//spyglass enable_block W338, W263
+// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443
+// Register flop declarations
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    arb_weight[3:0] <= 4'b1111;
+    arb_wmb[3:0] <= 4'b0011;
+    producer <= 1'b0;
+  end else begin
+// Register: NVDLA_CDMA_S_ARBITER_0 Field: arb_weight
+  if (nvdla_cdma_s_arbiter_0_wren) begin
+    arb_weight[3:0] <= reg_wr_data[3:0];
+  end
+// Register: NVDLA_CDMA_S_ARBITER_0 Field: arb_wmb
+  if (nvdla_cdma_s_arbiter_0_wren) begin
+    arb_wmb[3:0] <= reg_wr_data[19:16];
+  end
+// Not generating flops for read-only field NVDLA_CDMA_S_CBUF_FLUSH_STATUS_0::flush_done
+// Not generating flops for read-only field NVDLA_CDMA_S_POINTER_0::consumer
+// Register: NVDLA_CDMA_S_POINTER_0 Field: producer
+  if (nvdla_cdma_s_pointer_0_wren) begin
+    producer <= reg_wr_data[0];
+  end
+// Not generating flops for read-only field NVDLA_CDMA_S_STATUS_0::status_0
+// Not generating flops for read-only field NVDLA_CDMA_S_STATUS_0::status_1
+  end
+end
+// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443
+// synopsys translate_off
+// VCS coverage off
+initial begin
+  arreggen_dump = $test$plusargs("arreggen_dump_wr");
+  arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr");
+  arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr");
+`ifdef VERILATOR
+`else
+  $timeformat(-9, 2, "ns", 15);
+`endif
+end
+always @(posedge nvdla_core_clk) begin
+  if (reg_wr_en) begin
+    case(reg_offset)
+      (32'h5008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_S_ARBITER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_s_arbiter_0_out, nvdla_cdma_s_arbiter_0_out);
+      (32'h500c & 32'h00000fff): begin
+          if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_S_CBUF_FLUSH_STATUS_0 = 0x%h", $time, reg_wr_data);
+          if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end
+        end
+      (32'h5004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_s_pointer_0_out, nvdla_cdma_s_pointer_0_out);
+      (32'h5000 & 32'h00000fff): begin
+          if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data);
+          if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end
+        end
+      default: begin
+          if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data);
+          if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end
+        end
+    endcase
+  end
+end
+// VCS coverage on
+// synopsys translate_on
+endmodule // NV_NVDLA_CDMA_single_reg

Testcases/nvdla/rtl/NV_NVDLA_CDP_DP_INTP_unit.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CDP_DP_INTP_unit.v
+module NV_NVDLA_CDP_DP_INTP_unit (
+   nvdla_core_clk
+  ,nvdla_core_rstn
+  ,interp_in0_pd
+  ,interp_in1_pd
+  ,interp_in_pd
+  ,interp_in_scale
+  ,interp_in_shift
+  ,interp_in_vld
+  ,interp_out_rdy
+  ,interp_in_rdy
+  ,interp_out_pd
+  ,interp_out_vld
+  );
+/////////////////////////////////////////////////////////////////
+input nvdla_core_clk;
+input nvdla_core_rstn;
+input [38:0] interp_in0_pd;
+input [37:0] interp_in1_pd;
+input [16:0] interp_in_pd;
+input [16:0] interp_in_scale;
+input [5:0] interp_in_shift;
+input interp_in_vld;
+input interp_out_rdy;
+output interp_in_rdy;
+output [16:0] interp_out_pd;
+output interp_out_vld;
+/////////////////////////////////////////////////////////////////
+reg [88:0] int_add;
+reg [56:0] int_mul;
+reg [57:0] int_mul_for_Rshift;
+reg [39:0] int_sub;
+reg int_vld_d0;
+reg int_vld_d1;
+reg int_vld_d2;
+reg [16:0] interp_in0_pd_d0;
+reg [16:0] interp_in0_pd_d1;
+reg [16:0] interp_in_offset_d0;
+reg [5:0] interp_in_shift_d0;
+reg [5:0] interp_in_shift_d1;
+wire int_in_load;
+wire int_in_load_d0;
+wire int_in_load_d1;
+wire int_in_rdy;
+wire int_in_vld;
+wire [15:0] int_interp_out_pd;
+wire [87:0] int_mul_rs;
+wire [31:0] int_mul_shift_frac;
+wire [87:0] int_mul_shift_int;
+wire int_rdy_d0;
+wire int_rdy_d1;
+wire int_rdy_d2;
+wire [5:0] interp_in_shift_abs;
+wire [4:0] intp_in_shift_inv;
+wire [5:0] intp_in_shift_inv_inc;
+/////////////////////////////////////////////////////////////////
+///////////////////////////////////////////
+//interp_in_vld
+assign interp_in_rdy = int_in_rdy;
+///////////////////////////////////////////
+assign int_in_vld = interp_in_vld;
+assign int_in_rdy = ~int_vld_d0 | int_rdy_d0;
+assign int_in_load = int_in_vld & int_in_rdy;
+///////////////////
+//X1-X0
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    int_sub[39:0] <= {40{1'b0}};
+    interp_in0_pd_d0 <= {17{1'b0}};
+    interp_in_offset_d0 <= {17{1'b0}};
+    interp_in_shift_d0 <= {6{1'b0}};
+  end else begin
+    if(int_in_load) begin
+        int_sub[39:0] <= $signed({interp_in1_pd[37],interp_in1_pd[37:0]}) - $signed(interp_in0_pd[38:0]);
+        interp_in0_pd_d0 <= interp_in_pd[16:0];
+        interp_in_offset_d0 <= interp_in_scale[16:0];
+        interp_in_shift_d0 <= interp_in_shift[5:0];
+    end
+  end
+end
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    int_vld_d0 <= 1'b0;
+  end else begin
+    if(int_in_vld)
+        int_vld_d0 <= 1'b1;
+    else if(int_rdy_d0)
+        int_vld_d0 <= 1'b0;
+  end
+end
+assign int_rdy_d0 = ~int_vld_d1 | int_rdy_d1;
+assign int_in_load_d0 = int_vld_d0 & int_rdy_d0;
+///////////////////
+//(X1-X0)*frac
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    int_mul[56:0] <= {57{1'b0}};
+    interp_in0_pd_d1 <= {17{1'b0}};
+    interp_in_shift_d1 <= {6{1'b0}};
+  end else begin
+    if(int_in_load_d0) begin
+        int_mul[56:0] <= $signed(int_sub[39:0]) * $signed(interp_in_offset_d0);
+        interp_in0_pd_d1 <= interp_in0_pd_d0[16:0];
+        interp_in_shift_d1 <= interp_in_shift_d0[5:0];
+    end
+  end
+end
+//>>16 proc for ((X1-X0)*frac) >>16
+assign intp_in_shift_inv[4:0] = ~interp_in_shift_d1[4:0];
+assign intp_in_shift_inv_inc[5:0] = intp_in_shift_inv[4:0] + 5'd1;
+assign interp_in_shift_abs[5:0] = interp_in_shift_d1[5] ? intp_in_shift_inv_inc[5:0]: interp_in_shift_d1[5:0];
+`ifdef SPYGLASS_ASSERT_ON
+`else
+// spyglass disable_block NoWidthInBasedNum-ML
+// spyglass disable_block STARC-2.10.3.2a
+// spyglass disable_block STARC05-2.1.3.1
+// spyglass disable_block STARC-2.1.4.6
+// spyglass disable_block W116
+// spyglass disable_block W154
+// spyglass disable_block W239
+// spyglass disable_block W362
+// spyglass disable_block WRN_58
+// spyglass disable_block WRN_61
+`endif // SPYGLASS_ASSERT_ON
+`ifdef ASSERT_ON
+`ifdef FV_ASSERT_ON
+`define ASSERT_RESET nvdla_core_rstn
+`else
+`ifdef SYNTHESIS
+`define ASSERT_RESET nvdla_core_rstn
+`else
+`ifdef ASSERT_OFF_RESET_IS_X
+`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
+`else
+`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
+`endif // ASSERT_OFF_RESET_IS_X
+`endif // SYNTHESIS
+`endif // FV_ASSERT_ON
+// VCS coverage off
+  nv_assert_never #(0,0,"CDP_out of range shifter abs shouldn't out of data range of signed-int6") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, int_in_load_d1 & ((interp_in_shift_d1[5] & (interp_in_shift_abs > 6'd32)) | ((~interp_in_shift_d1[5]) & (interp_in_shift_abs > 6'd31)))); // spyglass disable W504 SelfDeterminedExpr-ML 
+// VCS coverage on
+`undef ASSERT_RESET
+`endif // ASSERT_ON
+`ifdef SPYGLASS_ASSERT_ON
+`else
+// spyglass enable_block NoWidthInBasedNum-ML
+// spyglass enable_block STARC-2.10.3.2a
+// spyglass enable_block STARC05-2.1.3.1
+// spyglass enable_block STARC-2.1.4.6
+// spyglass enable_block W116
+// spyglass enable_block W154
+// spyglass enable_block W239
+// spyglass enable_block W362
+// spyglass enable_block WRN_58
+// spyglass enable_block WRN_61
+`endif // SPYGLASS_ASSERT_ON
+assign {int_mul_shift_int[87:0],int_mul_shift_frac[31:0]} = interp_in_shift_d1[5] ? {{{31{int_mul[56]}}, int_mul[56:0]},32'd0} << interp_in_shift_abs[5:0] : {{{31{int_mul[56]}}, int_mul[56:0]},32'd0} >> interp_in_shift_abs[5:0];
+//rounding process for right shift
+always @(
+  int_mul_shift_int
+  or int_mul_shift_frac
+  ) begin
+//if(int_mul_shift_int[55]) begin
+    if(int_mul_shift_int[56]) begin
+        if(int_mul_shift_frac[31]) begin
+            if(~(|int_mul_shift_frac[30:0]))
+                int_mul_for_Rshift = {int_mul_shift_int[56],int_mul_shift_int[56:0]};
+            else
+                int_mul_for_Rshift = $signed(int_mul_shift_int[56:0]) + $signed({56'd0,1'b1});
+        end else begin
+            int_mul_for_Rshift = {int_mul_shift_int[56],int_mul_shift_int[56:0]};
+        end
+    end else begin
+        int_mul_for_Rshift = $signed(int_mul_shift_int[56:0]) + $signed({56'd0,int_mul_shift_frac[31]});
+    end
+end
+assign int_mul_rs[87:0] = interp_in_shift_d1[5] ? int_mul_shift_int[87:0] : ({{30{int_mul_for_Rshift[57]}}, int_mul_for_Rshift[57:0]});
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    int_vld_d1 <= 1'b0;
+  end else begin
+    if(int_vld_d0)
+        int_vld_d1 <= 1'b1;
+    else if(int_rdy_d1)
+        int_vld_d1 <= 1'b0;
+  end
+end
+assign int_rdy_d1 = ~int_vld_d2 | int_rdy_d2;
+assign int_in_load_d1 = int_vld_d1 & int_rdy_d1;
+//Xo = X0+[(X1-X0)*frac>>16]
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    int_add[88:0] <= {89{1'b0}};
+  end else begin
+    if(int_in_load_d1) begin
+        int_add[88:0] <= $signed(int_mul_rs[87:0]) + $signed({{71{interp_in0_pd_d1[16]}}, interp_in0_pd_d1[16:0]});
+    end
+  end
+end
+assign int_interp_out_pd[15:0] = int_add[88] ? (&int_add[88:15] ? {int_add[88],int_add[14:0]} : 16'h8000) : (|int_add[88:15] ? 16'h7fff : int_add[15:0]);
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    int_vld_d2 <= 1'b0;
+  end else begin
+    if(int_vld_d1)
+        int_vld_d2 <= 1'b1;
+    else if(int_rdy_d2)
+        int_vld_d2 <= 1'b0;
+  end
+end
+assign int_rdy_d2 = interp_out_rdy;
+//////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////
+assign interp_out_vld = int_vld_d2;
+assign interp_out_pd[16:0] = {int_interp_out_pd[15],int_interp_out_pd[15:0]};
+///////////////////////////////////////////
+endmodule // NV_NVDLA_CDP_DP_INTP_unit

Testcases/nvdla/rtl/NV_NVDLA_CDP_DP_LUT_ctrl.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CDP_DP_LUT_ctrl.v
+// ================================================================
+// NVDLA Open Source Project
+// 
+// Copyright(c) 2016 - 2017 NVIDIA Corporation.  Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with 
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CDP_define.h
+///////////////////////////////////////////////////
+//#ifdef NVDLA_FEATURE_DATA_TYPE_INT8
+//#if ( NVDLA_CDP_THROUGHPUT  ==  8 )
+//    #define LARGE_FIFO_RAM
+//#endif
+//#if ( NVDLA_CDP_THROUGHPUT == 1 )
+//    #define SMALL_FIFO_RAM
+//#endif
+//#endif
+module NV_NVDLA_CDP_DP_LUT_ctrl (
+   nvdla_core_clk //|< i
+  ,nvdla_core_rstn //|< i
+  ,dp2lut_prdy //|< i
+  ,reg2dp_lut_le_function //|< i
+  ,reg2dp_lut_le_index_offset //|< i
+  ,reg2dp_lut_le_index_select //|< i
+  ,reg2dp_lut_le_start_high //|< i
+  ,reg2dp_lut_le_start_low //|< i
+  ,reg2dp_lut_lo_index_select //|< i
+  ,reg2dp_lut_lo_start_high //|< i
+  ,reg2dp_lut_lo_start_low //|< i
+  ,reg2dp_sqsum_bypass //|< i
+  ,sum2itp_pd //|< i
+  ,sum2itp_pvld //|< i
+  ,sum2sync_prdy //|< i
+//: my $k = 1;
+//: foreach my $m (0..$k-1) {
+//: print qq(
+//: ,dp2lut_X_entry_${m}
+//: ,dp2lut_Xinfo_${m}
+//: ,dp2lut_Y_entry_${m}
+//: ,dp2lut_Yinfo_${m}
+//: );
+//: }
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+
+,dp2lut_X_entry_0
+,dp2lut_Xinfo_0
+,dp2lut_Y_entry_0
+,dp2lut_Yinfo_0
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+  ,dp2lut_pvld //|> o
+  ,sum2itp_prdy //|> o
+  ,sum2sync_pd //|> o
+  ,sum2sync_pvld //|> o
+  );
+////////////////////////////////////////////////////////////////////////////////////////
+//parameter pINT8_BW = 9;//int8 bitwidth after icvt
+//parameter pPP_BW = (pINT8_BW + pINT8_BW) -1 + 4;
+////////////////////////////////////////////////////////////////////////////////////////
+input nvdla_core_clk;
+input nvdla_core_rstn;
+input reg2dp_lut_le_function;
+input [7:0] reg2dp_lut_le_index_offset;
+input [7:0] reg2dp_lut_le_index_select;
+input [5:0] reg2dp_lut_le_start_high;
+input [31:0] reg2dp_lut_le_start_low;
+input [7:0] reg2dp_lut_lo_index_select;
+input [5:0] reg2dp_lut_lo_start_high;
+input [31:0] reg2dp_lut_lo_start_low;
+input reg2dp_sqsum_bypass;
+//: my $tp=1;
+//: my $icvto=(8 +1);
+//: my $sqsumo = $icvto *2 -1+4; ##(${tp}*2) -1 is for x^2, +4 is after 9 lrn
+//: print "input  [${tp}*${sqsumo}-1:0] sum2itp_pd;  \n";
+//: print "output [${tp}*${sqsumo}-1:0] sum2sync_pd; \n";
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+input  [1*21-1:0] sum2itp_pd;  
+output [1*21-1:0] sum2sync_pd; 
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+input sum2itp_pvld;
+output sum2itp_prdy;
+//: my $k = 1;
+//: foreach my $m (0..$k-1) {
+//: print qq(
+//: output [9:0] dp2lut_X_entry_${m};
+//: output [17:0] dp2lut_Xinfo_${m};
+//: output [9:0] dp2lut_Y_entry_${m};
+//: output [17:0] dp2lut_Yinfo_${m};
+//: );
+//: }
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+
+output [9:0] dp2lut_X_entry_0;
+output [17:0] dp2lut_Xinfo_0;
+output [9:0] dp2lut_Y_entry_0;
+output [17:0] dp2lut_Yinfo_0;
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+output dp2lut_pvld;
+input dp2lut_prdy;
+output sum2sync_pvld;
+input sum2sync_prdy;
+////////////////////////////////////////////////////////////////////////////////////////
+//: my $tp=1;
+//: my $icvto=(8 +1);
+//: my $sqsumo = $icvto *2 -1+4;
+//: foreach my $m (0..${tp}-1) {
+//: print qq(
+//: wire [17:0] dp2lut_X_info_$m;
+//: wire [9:0] dp2lut_X_pd_$m;
+//: wire [17:0] dp2lut_Y_info_$m;
+//: wire [9:0] dp2lut_Y_pd_$m;
+//: wire [${sqsumo}-1:0] sum2itp_pd_$m;
+//: );
+//: }
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+
+wire [17:0] dp2lut_X_info_0;
+wire [9:0] dp2lut_X_pd_0;
+wire [17:0] dp2lut_Y_info_0;
+wire [9:0] dp2lut_Y_pd_0;
+wire [21-1:0] sum2itp_pd_0;
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+wire [1 -1:0] dp2lut_rdy;
+wire [1 -1:0] dp2lut_vld;
+wire [1 -1:0] sum2itp_rdy;
+wire [1 -1:0] sum2itp_vld;
+////////////////////////////////////////////////////////////////////////////////////////
+assign sum2itp_prdy = (&sum2itp_rdy) & sum2sync_prdy;
+//////////////////////////////////////////////////////////////////////
+//from intp_ctrl input port to sync fifo for interpolation
+assign sum2sync_pvld = sum2itp_pvld & (&sum2itp_rdy);
+assign sum2sync_pd = sum2itp_pd;
+///////////////////////////////////////////
+//: my $tp=1;
+//: my $icvto=(8 +1);
+//: my $sqsumo = $icvto *2 -1+4;
+//: foreach my $m (0..${tp} -1) {
+//: print qq(
+//: assign sum2itp_vld[$m] = sum2itp_pvld & sum2sync_prdy
+//: );
+//: foreach my $j (0..${tp} -1) {
+//: if(${j} != ${m}) {
+//: print qq(
+//: & sum2itp_rdy[$j]
+//: );
+//: }
+//: }
+//: print qq(
+//: ;
+//: );
+//: print qq(
+//: assign sum2itp_pd_${m} = sum2itp_pd[${sqsumo}*${m}+${sqsumo}-1:${sqsumo}*${m}];
+//: NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit$m (
+//: .nvdla_core_clk (nvdla_core_clk)
+//: ,.nvdla_core_rstn (nvdla_core_rstn)
+//: ,.sum2itp_pd (sum2itp_pd_${m})
+//: ,.sum2itp_pvld (sum2itp_vld[${m}])
+//: ,.sum2itp_prdy (sum2itp_rdy[${m}])
+//: ,.reg2dp_lut_le_function (reg2dp_lut_le_function)
+//: ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
+//: ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
+//: ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
+//: ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
+//: ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
+//: ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
+//: ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
+//: ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
+//: ,.dp2lut_X_info (dp2lut_X_info_${m})
+//: ,.dp2lut_X_pd (dp2lut_X_pd_${m})
+//: ,.dp2lut_Y_info (dp2lut_Y_info_${m})
+//: ,.dp2lut_Y_pd (dp2lut_Y_pd_${m})
+//: ,.dp2lut_pvld (dp2lut_vld[${m}])
+//: ,.dp2lut_prdy (dp2lut_rdy[${m}])
+//: );
+//: );
+//: }
+//: my $k = 1;
+//: foreach my $m (0..$k -1) {
+//: print qq(
+//: assign dp2lut_X_entry_$m = dp2lut_X_pd_$m;
+//: assign dp2lut_Y_entry_$m = dp2lut_Y_pd_$m;
+//: assign dp2lut_Xinfo_$m = dp2lut_X_info_$m;
+//: assign dp2lut_Yinfo_$m = dp2lut_Y_info_$m;
+//: );
+//: }
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+
+assign sum2itp_vld[0] = sum2itp_pvld & sum2sync_prdy
+
+;
+
+assign sum2itp_pd_0 = sum2itp_pd[21*0+21-1:21*0];
+NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit0 (
+.nvdla_core_clk (nvdla_core_clk)
+,.nvdla_core_rstn (nvdla_core_rstn)
+,.sum2itp_pd (sum2itp_pd_0)
+,.sum2itp_pvld (sum2itp_vld[0])
+,.sum2itp_prdy (sum2itp_rdy[0])
+,.reg2dp_lut_le_function (reg2dp_lut_le_function)
+,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
+,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
+,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
+,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
+,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
+,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
+,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
+,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
+,.dp2lut_X_info (dp2lut_X_info_0)
+,.dp2lut_X_pd (dp2lut_X_pd_0)
+,.dp2lut_Y_info (dp2lut_Y_info_0)
+,.dp2lut_Y_pd (dp2lut_Y_pd_0)
+,.dp2lut_pvld (dp2lut_vld[0])
+,.dp2lut_prdy (dp2lut_rdy[0])
+);
+
+assign dp2lut_X_entry_0 = dp2lut_X_pd_0;
+assign dp2lut_Y_entry_0 = dp2lut_Y_pd_0;
+assign dp2lut_Xinfo_0 = dp2lut_X_info_0;
+assign dp2lut_Yinfo_0 = dp2lut_Y_info_0;
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+assign dp2lut_pvld = &dp2lut_vld;
+//: my $k = 1;
+//: foreach my $m (0..$k -1) {
+//: print qq(
+//: assign dp2lut_rdy[${m}] = dp2lut_prdy
+//: );
+//: foreach my $j (0..$k -1) {
+//: if(${j} != ${m}) {
+//: print qq(
+//: & dp2lut_vld[$j]
+//: );
+//: }
+//: }
+//: print qq(
+//: ;
+//: );
+//: }
+//| eperl: generated_beg (DO NOT EDIT BELOW)
+
+assign dp2lut_rdy[0] = dp2lut_prdy
+
+;
+
+//| eperl: generated_end (DO NOT EDIT ABOVE)
+///////////////////////////////////////////
+endmodule // NV_NVDLA_CDP_DP_LUT_ctrl

Testcases/nvdla/rtl/NV_NVDLA_CDP_DP_MUL_unit.v

+// ================================================================
+// NVDLA Open Source Project
+//
+// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
+// NVDLA Open Hardware License; Check "LICENSE" which comes with
+// this distribution for more information.
+// ================================================================
+// File Name: NV_NVDLA_CDP_DP_MUL_unit.v
+module NV_NVDLA_CDP_DP_MUL_unit (
+   nvdla_core_clk
+  ,nvdla_core_rstn
+  ,mul_ina_pd
+  ,mul_inb_pd
+  ,mul_unit_rdy
+  ,mul_vld
+  ,mul_rdy
+  ,mul_unit_pd
+  ,mul_unit_vld
+  );
+//////////////////////////////////////////////////////////////////////////
+parameter pINA_BW = 9;
+parameter pINB_BW = 16;
+//////////////////////////////////////////////////////////////////////////
+input nvdla_core_clk;
+input nvdla_core_rstn;
+input mul_vld;
+output mul_rdy;
+input [pINA_BW-1:0] mul_ina_pd;
+input [pINB_BW-1:0] mul_inb_pd;
+output mul_unit_vld;
+input mul_unit_rdy;
+output [pINA_BW+pINB_BW-1:0] mul_unit_pd;
+//////////////////////////////////////////////////////////////////////////
+reg mul_unit_vld;
+reg [pINA_BW+pINB_BW-1:0] mul_unit_pd;
+//////////////////////////////////////////////////////////////////////////
+assign mul_rdy = ~mul_unit_vld | mul_unit_rdy;
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    mul_unit_pd <= {(pINA_BW+pINB_BW){1'b0}};
+  end else begin
+    if(mul_vld & mul_rdy) begin
+        mul_unit_pd <= $signed(mul_inb_pd[pINB_BW-1:0]) * $signed(mul_ina_pd[pINA_BW-1:0]);
+    end
+  end
+end
+always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
+  if (!nvdla_core_rstn) begin
+    mul_unit_vld <= 1'b0;
+  end else begin
+    if(mul_vld)
+        mul_unit_vld <= 1'b1;
+    else if(mul_unit_rdy)
+        mul_unit_vld <= 1'b0;
+  end
+end
+///////////////////////////////////////////
+endmodule // NV_NVDLA_CDP_DP_MUL_unit