Commit e8f459d8 by Alan Mishchenko

Extending Verilog parser to handle 'default' in the case-statement (bug fix).

parent 64afe6e9
...@@ -1085,7 +1085,10 @@ startword: ...@@ -1085,7 +1085,10 @@ startword:
if ( fDefaultFound ) if ( fDefaultFound )
{ {
int EntryLast = Vec_IntEntryLast( p->vFanins ); int EntryLast = Vec_IntEntryLast( p->vFanins );
Vec_IntFillExtra( p->vFanins, nValues + 1, EntryLast ); if (nValues != Vec_IntSize(p->vFanins)-2)
Vec_IntFillExtra( p->vFanins, nValues + 1, EntryLast );
else
Vec_IntPop(p->vFanins);
// get next line and check its opening character // get next line and check its opening character
pStart = Wlc_PrsStr(p, Vec_IntEntry(p->vStarts, ++i)); pStart = Wlc_PrsStr(p, Vec_IntEntry(p->vStarts, ++i));
pStart = Wlc_PrsSkipSpaces( pStart ); pStart = Wlc_PrsSkipSpaces( pStart );
......
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