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abc
Commit 20c2b197 by Alan Mishchenko
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Version abc51007

parent d401cfa6
Showing with 733 additions and 115 deletions
abc.dsp
......@@ -42,7 +42,7 @@ RSC=rc.exe
# PROP Ignore_Export_Lib 0
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /c
# ADD CPP /nologo /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /c
# ADD BASE RSC /l 0x409 /d "NDEBUG"
# ADD RSC /l 0x409 /d "NDEBUG"
BSC32=bscmake.exe
......@@ -66,7 +66,7 @@ LINK32=link.exe
# PROP Ignore_Export_Lib 0
# PROP Target_Dir ""
# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /GZ /c
# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR /YX /FD /GZ /c
# SUBTRACT CPP /X
# ADD BASE RSC /l 0x409 /d "_DEBUG"
# ADD RSC /l 0x409 /d "_DEBUG"
......@@ -266,6 +266,10 @@ SOURCE=.\src\base\abci\abcVanEijk.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcVanImp.c
# End Source File
# Begin Source File
SOURCE=.\src\base\abci\abcVerify.c
# End Source File
# End Group
......@@ -898,7 +902,7 @@ SOURCE=.\src\sat\msat\msatMem.c
# End Source File
# Begin Source File
SOURCE=.\src\sat\msat\msatOrderJ.c
SOURCE=.\src\sat\msat\msatOrderH.c
# End Source File
# Begin Source File
......@@ -1198,6 +1202,10 @@ SOURCE=.\src\opt\sim\simSat.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\sim\simSeq.c
# End Source File
# Begin Source File
SOURCE=.\src\opt\sim\simSupp.c
# End Source File
# Begin Source File
......@@ -1688,26 +1696,6 @@ SOURCE=.\src\misc\vec\vecVec.h
# Begin Group "npn"
# PROP Default_Filter ""
# Begin Source File
SOURCE=.\src\misc\npn\npn.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\npn\npn.h
# End Source File
# Begin Source File
SOURCE=.\src\misc\npn\npnGenStr.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\npn\npnTruth.c
# End Source File
# Begin Source File
SOURCE=.\src\misc\npn\npnUtil.c
# End Source File
# End Group
# End Group
# End Group
......
abc.opt
No preview for this file type
abc.plg
......@@ -6,15 +6,13 @@
--------------------Configuration: abc - Win32 Release--------------------
</h3>
<h3>Command Lines</h3>
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1362.tmp" with contents
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP194C.tmp" with contents
[
/nologo /ML /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"Release/" /Fp"Release/abc.pch" /YX /Fo"Release/" /Fd"Release/" /FD /c
"C:\_projects\abc\src\base\abci\abcFraig.c"
"C:\_projects\abc\src\base\abci\abcVanEijk.c"
"C:\_projects\abc\src\sat\fraig\fraigApi.c"
/nologo /ML /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"Release/" /Fp"Release/abc.pch" /YX /Fo"Release/" /Fd"Release/" /FD /c
"C:\_projects\abc\src\base\abci\abcVanImp.c"
]
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1362.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1363.tmp" with contents
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP194C.tmp"
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP194D.tmp" with contents
[
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /incremental:no /pdb:"Release/abc.pdb" /machine:I386 /out:"_TEST/abc.exe"
.\Release\abcAig.obj
......@@ -180,7 +178,6 @@ kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32
.\Release\msatClause.obj
.\Release\msatClauseVec.obj
.\Release\msatMem.obj
.\Release\msatOrderJ.obj
.\Release\msatQueue.obj
.\Release\msatRead.obj
.\Release\msatSolverApi.obj
......@@ -323,19 +320,16 @@ kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32
.\Release\mvcPrint.obj
.\Release\mvcSort.obj
.\Release\mvcUtils.obj
.\Release\npn.obj
.\Release\npnGenStr.obj
.\Release\npnTruth.obj
.\Release\npnUtil.obj
.\Release\abcVanImp.obj
.\Release\simSeq.obj
.\Release\msatOrderH.obj
]
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1363.tmp"
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP194D.tmp"
<h3>Output Window</h3>
Compiling...
abcFraig.c
abcVanEijk.c
fraigApi.c
abcVanImp.c
Linking...
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1365.tmp" with contents
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP194F.tmp" with contents
[
/nologo /o"Release/abc.bsc"
.\Release\abcAig.sbr
......@@ -501,7 +495,6 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1365.tmp" with cont
.\Release\msatClause.sbr
.\Release\msatClauseVec.sbr
.\Release\msatMem.sbr
.\Release\msatOrderJ.sbr
.\Release\msatQueue.sbr
.\Release\msatRead.sbr
.\Release\msatSolverApi.sbr
......@@ -644,11 +637,10 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1365.tmp" with cont
.\Release\mvcPrint.sbr
.\Release\mvcSort.sbr
.\Release\mvcUtils.sbr
.\Release\npn.sbr
.\Release\npnGenStr.sbr
.\Release\npnTruth.sbr
.\Release\npnUtil.sbr]
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1365.tmp"
.\Release\abcVanImp.sbr
.\Release\simSeq.sbr
.\Release\msatOrderH.sbr]
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP194F.tmp"
Creating browse info file...
<h3>Output Window</h3>
......
abc.rc
......@@ -24,6 +24,7 @@ alias f fraig
alias fs fraig_sweep
alias ft fraig_trust
alias mu renode -m
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
......
src/base/abc/abc.h
......@@ -536,6 +536,7 @@ extern void Abc_NtkAddDummyPiNames( Abc_Ntk_t * pNtk );
extern void Abc_NtkAddDummyPoNames( Abc_Ntk_t * pNtk );
extern void Abc_NtkAddDummyLatchNames( Abc_Ntk_t * pNtk );
extern void Abc_NtkShortNames( Abc_Ntk_t * pNtk );
extern stmm_table * Abc_NtkNamesToTable( Vec_Ptr_t * vNodes );
/*=== abcNetlist.c ==========================================================*/
extern Abc_Ntk_t * Abc_NtkNetlistToLogic( Abc_Ntk_t * pNtk );
extern Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk );
......
src/base/abc/abcNames.c
......@@ -547,6 +547,28 @@ void Abc_NtkShortNames( Abc_Ntk_t * pNtk )
Abc_NtkAddDummyLatchNames( pNtk );
}
/**Function*************************************************************
Synopsis [Returns the hash table with these names.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
stmm_table * Abc_NtkNamesToTable( Vec_Ptr_t * vNodes )
{
stmm_table * tTable;
Abc_Obj_t * pObj;
int i;
tTable = stmm_init_table(strcmp, stmm_strhash);
Vec_PtrForEachEntry( vNodes, pObj, i )
stmm_insert( tTable, Abc_ObjName(pObj), (char *)pObj );
return tTable;
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
......
src/base/abci/abc.c
......@@ -2293,7 +2293,7 @@ int Abc_CommandFrames( Abc_Frame_t * pAbc, int argc, char ** argv )
}
nFrames = atoi(argv[util_optind]);
util_optind++;
if ( nFrames < 0 )
if ( nFrames <= 0 )
goto usage;
break;
case 'i':
......@@ -5114,8 +5114,10 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
int c;
int nFrames;
int fExdc;
int fImp;
int fVerbose;
extern Abc_Ntk_t * Abc_NtkVanEijk( Abc_Ntk_t * pNtk, int nFrames, int fExdc, int fVerbose );
extern Abc_Ntk_t * Abc_NtkVanImp( Abc_Ntk_t * pNtk, int nFrames, int fExdc, int fVerbose );
pNtk = Abc_FrameReadNet(pAbc);
pOut = Abc_FrameReadOut(pAbc);
......@@ -5124,9 +5126,10 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
// set defaults
nFrames = 1;
fExdc = 1;
fImp = 0;
fVerbose = 1;
util_getopt_reset();
while ( ( c = util_getopt( argc, argv, "Fevh" ) ) != EOF )
while ( ( c = util_getopt( argc, argv, "Feivh" ) ) != EOF )
{
switch ( c )
{
......@@ -5138,12 +5141,15 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
}
nFrames = atoi(argv[util_optind]);
util_optind++;
if ( nFrames < 0 )
if ( nFrames <= 0 )
goto usage;
break;
case 'e':
fExdc ^= 1;
break;
case 'i':
fImp ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
......@@ -5179,7 +5185,10 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
}
// get the new network
pNtkRes = Abc_NtkVanEijk( pNtk, nFrames, fExdc, fVerbose );
if ( fImp )
pNtkRes = Abc_NtkVanImp( pNtk, nFrames, fExdc, fVerbose );
else
pNtkRes = Abc_NtkVanEijk( pNtk, nFrames, fExdc, fVerbose );
if ( pNtkRes == NULL )
{
fprintf( pErr, "Sequential FPGA mapping has failed.\n" );
......@@ -5190,10 +5199,11 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
fprintf( pErr, "usage: seq_sweep [-F num] [-vh]\n" );
fprintf( pErr, "usage: seq_sweep [-F num] [-eivh]\n" );
fprintf( pErr, "\t performs sequential sweep using van Eijk's method\n" );
fprintf( pErr, "\t-F num : number of time frames in the base case [default = %d]\n", nFrames );
fprintf( pErr, "\t-e : toggle writing EXDC network [default = %s]\n", fExdc? "yes": "no" );
fprintf( pErr, "\t-i : toggle computing implications [default = %s]\n", fImp? "yes": "no" );
fprintf( pErr, "\t-v : toggle verbose output [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pErr, "\t-h : print the command usage\n");
return 1;
......@@ -5342,7 +5352,7 @@ int Abc_CommandSec( Abc_Frame_t * pAbc, int argc, char ** argv )
}
nFrames = atoi(argv[util_optind]);
util_optind++;
if ( nFrames < 0 )
if ( nFrames <= 0 )
goto usage;
break;
case 'T':
......
src/base/abci/abcUnreach.c
......@@ -285,7 +285,7 @@ Abc_Ntk_t * Abc_NtkConstructExdc( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * bUn
// start the new network
pNtkNew = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_BDD );
pNtkNew->pName = util_strsav("exdc");
pNtkNew->pName = util_strsav( "exdc" );
pNtkNew->pSpec = NULL;
// create PIs corresponding to LOs
......
src/base/abci/abcVanEijk.c
......@@ -35,10 +35,12 @@ static int Abc_NtkVanEijkClassesRefine( Abc_Ntk_t * pNtk, Vec_Ptr_t *
static void Abc_NtkVanEijkClassesOrder( Vec_Ptr_t * vClasses );
static int Abc_NtkVanEijkClassesCountPairs( Vec_Ptr_t * vClasses );
static void Abc_NtkVanEijkClassesTest( Abc_Ntk_t * pNtkSingle, Vec_Ptr_t * vClasses );
static Abc_Ntk_t * Abc_NtkVanEijkFrames( Abc_Ntk_t * pNtk, Vec_Ptr_t * vCorresp, int nFrames, int fAddLast, int fShortNames );
static void Abc_NtkVanEijkAddFrame( Abc_Ntk_t * pNtkFrames, Abc_Ntk_t * pNtk, int iFrame, Vec_Ptr_t * vCorresp, Vec_Ptr_t * vOrder, int fShortNames );
static Fraig_Man_t * Abc_NtkVanEijkFraig( Abc_Ntk_t * pMulti, int fInit );
static Abc_Ntk_t * Abc_NtkVanEijkDeriveExdc( Abc_Ntk_t * pNtkInit, Abc_Ntk_t * pNtk, Vec_Ptr_t * vClasses );
extern Abc_Ntk_t * Abc_NtkVanEijkFrames( Abc_Ntk_t * pNtk, Vec_Ptr_t * vCorresp, int nFrames, int fAddLast, int fShortNames );
extern void Abc_NtkVanEijkAddFrame( Abc_Ntk_t * pNtkFrames, Abc_Ntk_t * pNtk, int iFrame, Vec_Ptr_t * vCorresp, Vec_Ptr_t * vOrder, int fShortNames );
extern Fraig_Man_t * Abc_NtkVanEijkFraig( Abc_Ntk_t * pMulti, int fInit );
static Abc_Ntk_t * Abc_NtkVanEijkDeriveExdc( Abc_Ntk_t * pNtk, Vec_Ptr_t * vClasses );
////////////////////////////////////////////////////////////////////////
/// INLINED FUNCTIONS ///
......@@ -99,6 +101,7 @@ Abc_Ntk_t * Abc_NtkVanEijk( Abc_Ntk_t * pNtk, int nFrames, int fExdc, int fVerbo
Fraig_ParamsSetDefaultFull( &Params );
pNtkSingle = Abc_NtkFraig( pNtk, &Params, 0, 0 );
Abc_AigSetNodePhases( pNtkSingle );
Abc_NtkCleanNext(pNtkSingle);
// get the equivalence classes
vClasses = Abc_NtkVanEijkClasses( pNtkSingle, nFrames, fVerbose );
......@@ -109,7 +112,7 @@ Abc_Ntk_t * Abc_NtkVanEijk( Abc_Ntk_t * pNtk, int nFrames, int fExdc, int fVerbo
// pNtkNew = Abc_NtkDup( pNtkSingle );
// derive the EXDC network if asked
if ( fExdc )
pNtkNew->pExdc = Abc_NtkVanEijkDeriveExdc( pNtk, pNtkSingle, vClasses );
pNtkNew->pExdc = Abc_NtkVanEijkDeriveExdc( pNtkSingle, vClasses );
}
else
pNtkNew = Abc_NtkDup( pNtkSingle );
......@@ -137,23 +140,23 @@ Vec_Ptr_t * Abc_NtkVanEijkClasses( Abc_Ntk_t * pNtkSingle, int nFrames, int fVer
Abc_Ntk_t * pNtkMulti;
Vec_Ptr_t * vCorresp, * vClasses;
int nIter, RetValue;
int nAddFrames = 0;
if ( fVerbose )
printf( "The number of ANDs after FRAIGing = %d.\n", Abc_NtkNodeNum(pNtkSingle) );
// get the AIG of the base case
vCorresp = Vec_PtrAlloc( 100 );
Abc_NtkCleanNext(pNtkSingle);
pNtkMulti = Abc_NtkVanEijkFrames( pNtkSingle, vCorresp, nFrames, 0, 0 );
pNtkMulti = Abc_NtkVanEijkFrames( pNtkSingle, vCorresp, nFrames + nAddFrames, 0, 0 );
if ( fVerbose )
printf( "The number of ANDs in %d timeframes = %d.\n", nFrames, Abc_NtkNodeNum(pNtkMulti) );
printf( "The number of ANDs in %d timeframes = %d.\n", nFrames + nAddFrames, Abc_NtkNodeNum(pNtkMulti) );
// FRAIG the initialized frames (labels the nodes of pNtkMulti with FRAIG nodes to be used as hash keys)
pFraig = Abc_NtkVanEijkFraig( pNtkMulti, 1 );
Fraig_ManFree( pFraig );
// find initial equivalence classes
vClasses = Abc_NtkVanEijkClassesDeriveBase( pNtkSingle, vCorresp, nFrames );
vClasses = Abc_NtkVanEijkClassesDeriveBase( pNtkSingle, vCorresp, nFrames + nAddFrames );
if ( fVerbose )
printf( "The number of classes in the base case = %5d. Pairs = %8d.\n", Vec_PtrSize(vClasses), Abc_NtkVanEijkClassesCountPairs(vClasses) );
Abc_NtkDelete( pNtkMulti );
......@@ -192,6 +195,12 @@ Vec_Ptr_t * Abc_NtkVanEijkClasses( Abc_Ntk_t * pNtkSingle, int nFrames, int fVer
for ( pObj = pClass; pObj; pObj = pObj->pNext )
Counter++;
printf( " %d", Counter );
/*
printf( " = {" );
for ( pObj = pClass; pObj; pObj = pObj->pNext )
printf( " %d", pObj->Id );
printf( " } " );
*/
}
printf( "\n" );
}
......@@ -541,7 +550,9 @@ Abc_Ntk_t * Abc_NtkVanEijkFrames( Abc_Ntk_t * pNtk, Vec_Ptr_t * vCorresp, int nF
pLatch->pNext = NULL;
}
// remove dangling nodes
Abc_AigCleanup( pNtkFrames->pManFunc );
// Abc_AigCleanup( pNtkFrames->pManFunc );
// otherwise some external nodes may have dandling pointers
// make sure that everything is okay
if ( !Abc_NtkCheck( pNtkFrames ) )
printf( "Abc_NtkVanEijkFrames: The network check has failed.\n" );
......@@ -699,7 +710,7 @@ Fraig_Man_t * Abc_NtkVanEijkFraig( Abc_Ntk_t * pMulti, int fInit )
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkVanEijkDeriveExdc( Abc_Ntk_t * pNtkInit, Abc_Ntk_t * pNtk, Vec_Ptr_t * vClasses )
Abc_Ntk_t * Abc_NtkVanEijkDeriveExdc( Abc_Ntk_t * pNtk, Vec_Ptr_t * vClasses )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pClass, * pNode, * pRepr, * pObj;
......@@ -707,6 +718,8 @@ Abc_Ntk_t * Abc_NtkVanEijkDeriveExdc( Abc_Ntk_t * pNtkInit, Abc_Ntk_t * pNtk, Ve
Vec_Ptr_t * vCone;
int i, k;
assert( Abc_NtkIsStrash(pNtk) );
// start the network
pNtkNew = Abc_NtkAlloc( pNtk->ntkType, pNtk->ntkFunc );
pNtkNew->pName = util_strsav("exdc");
......@@ -716,7 +729,7 @@ Abc_Ntk_t * Abc_NtkVanEijkDeriveExdc( Abc_Ntk_t * pNtkInit, Abc_Ntk_t * pNtk, Ve
Abc_AigConst1(pNtk->pManFunc)->pCopy = Abc_AigConst1(pNtkNew->pManFunc);
// for each CI, create PI
Abc_NtkForEachCi( pNtk, pObj, i )
Abc_NtkLogicStoreName( pObj->pCopy = Abc_NtkCreatePi(pNtkNew), Abc_ObjName( Abc_NtkCi(pNtkInit,i) ) );
Abc_NtkLogicStoreName( pObj->pCopy = Abc_NtkCreatePi(pNtkNew), Abc_ObjName(pObj) );
// cannot add latches here because pLatch->pCopy pointers are used
// create the cones for each pair of nodes in an equivalence class
......@@ -756,9 +769,9 @@ Abc_Ntk_t * Abc_NtkVanEijkDeriveExdc( Abc_Ntk_t * pNtkInit, Abc_Ntk_t * pNtk, Ve
// for each CO, create PO (skip POs equal to CIs because of name conflict)
Abc_NtkForEachPo( pNtk, pObj, i )
if ( !Abc_ObjIsCi(Abc_ObjFanin0(pObj)) )
Abc_NtkLogicStoreName( pObj->pCopy = Abc_NtkCreatePo(pNtkNew), Abc_ObjName( Abc_NtkPo(pNtkInit,i) ) );
Abc_NtkLogicStoreName( pObj->pCopy = Abc_NtkCreatePo(pNtkNew), Abc_ObjName(pObj) );
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_NtkLogicStoreName( pObj->pCopy = Abc_NtkCreatePo(pNtkNew), Abc_ObjNameSuffix( Abc_NtkLatch(pNtkInit,i), "_in") );
Abc_NtkLogicStoreName( pObj->pCopy = Abc_NtkCreatePo(pNtkNew), Abc_ObjNameSuffix( pObj, "_in") );
// link to the POs of the network
Abc_NtkForEachPo( pNtk, pObj, i )
......
src/misc/vec/vecInt.h
......@@ -52,6 +52,10 @@ struct Vec_Int_t_
for ( i = 0; (i < Vec_IntSize(vVec)) && (((Entry) = Vec_IntEntry(vVec, i)), 1); i++ )
#define Vec_IntForEachEntryStart( vVec, Entry, i, Start ) \
for ( i = Start; (i < Vec_IntSize(vVec)) && (((Entry) = Vec_IntEntry(vVec, i)), 1); i++ )
#define Vec_IntForEachEntryStartStop( vVec, Entry, i, Start, Stop ) \
for ( i = Start; (i < Stop) && (((Entry) = Vec_IntEntry(vVec, i)), 1); i++ )
#define Vec_IntForEachEntryReverse( vVec, pEntry, i ) \
for ( i = Vec_IntSize(vVec) - 1; (i >= 0) && (((pEntry) = Vec_IntEntry(vVec, i)), 1); i-- )
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFITIONS ///
......
src/opt/sim/sim.h
......@@ -17,7 +17,7 @@
Revision [$Id: sim.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#ifndef __SIM_H__
#define __SIM_H__
......@@ -162,6 +162,7 @@ struct Sim_Pat_t_
#define Sim_SuppFunHasVar(vSupps,Output,v) Sim_HasBit((unsigned*)(vSupps)->pArray[Output],(v))
#define Sim_SimInfoSetVar(vSupps,pNode,v) Sim_SetBit((unsigned*)(vSupps)->pArray[(pNode)->Id],(v))
#define Sim_SimInfoHasVar(vSupps,pNode,v) Sim_HasBit((unsigned*)(vSupps)->pArray[(pNode)->Id],(v))
#define Sim_SimInfoGet(vInfo,pNode) ((unsigned *)((vInfo)->pArray[(pNode)->Id]))
////////////////////////////////////////////////////////////////////////
/// FUNCTION DECLARATIONS ///
......@@ -176,6 +177,9 @@ extern void Sim_ManStop( Sim_Man_t * p );
extern void Sim_ManPrintStats( Sim_Man_t * p );
extern Sim_Pat_t * Sim_ManPatAlloc( Sim_Man_t * p );
extern void Sim_ManPatFree( Sim_Man_t * p, Sim_Pat_t * pPat );
/*=== simSeq.c ==========================================================*/
extern Vec_Ptr_t * Sim_SimulateSeqRandom( Abc_Ntk_t * pNtk, int nFrames, int nWords );
extern Vec_Ptr_t * Sim_SimulateSeqModel( Abc_Ntk_t * pNtk, int nFrames, int * pModel );
/*=== simSupp.c ==========================================================*/
extern Vec_Ptr_t * Sim_ComputeStrSupp( Abc_Ntk_t * pNtk );
extern Vec_Ptr_t * Sim_ComputeFunSupp( Abc_Ntk_t * pNtk, int fVerbose );
......@@ -197,10 +201,17 @@ extern void Sim_UtilInfoFlip( Sim_Man_t * p, Abc_Obj_t * pNode );
extern bool Sim_UtilInfoCompare( Sim_Man_t * p, Abc_Obj_t * pNode );
extern void Sim_UtilSimulate( Sim_Man_t * p, bool fFirst );
extern void Sim_UtilSimulateNode( Sim_Man_t * p, Abc_Obj_t * pNode, bool fType, bool fType1, bool fType2 );
extern void Sim_UtilSimulateNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimWords );
extern void Sim_UtilSimulateNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimWords, int nOffset );
extern void Sim_UtilTransferNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimWords, int nOffset, int fShift );
extern int Sim_UtilCountSuppSizes( Sim_Man_t * p, int fStruct );
extern int Sim_UtilCountOnes( unsigned * pSimInfo, int nSimWords );
extern void Sim_UtilGetRandom( unsigned * pPatRand, int nSimWords );
extern Vec_Int_t * Sim_UtilCountOnesArray( Vec_Ptr_t * vInfo, int nSimWords );
extern void Sim_UtilSetRandom( unsigned * pPatRand, int nSimWords );
extern void Sim_UtilSetCompl( unsigned * pPatRand, int nSimWords );
extern void Sim_UtilSetConst( unsigned * pPatRand, int nSimWords, int fConst1 );
extern int Sim_UtilInfoIsEqual( unsigned * pPats1, unsigned * pPats2, int nSimWords );
extern int Sim_UtilInfoIsImp( unsigned * pPats1, unsigned * pPats2, int nSimWords );
extern int Sim_UtilInfoIsClause( unsigned * pPats1, unsigned * pPats2, int nSimWords );
extern int Sim_UtilCountAllPairs( Vec_Ptr_t * vSuppFun, int nSimWords, Vec_Int_t * vCounters );
extern void Sim_UtilCountPairsAll( Sym_Man_t * p );
extern int Sim_UtilMatrsAreDisjoint( Sym_Man_t * p );
......
src/opt/sim/simSeq.c 0 → 100644
/**CFile****************************************************************
FileName [simSeq.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Network and node package.]
Synopsis [Simulation for sequential circuits.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [$Id: simUtils.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
***********************************************************************/
#include "abc.h"
#include "sim.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
static void Sim_SimulateSeqFrame( Vec_Ptr_t * vInfo, Abc_Ntk_t * pNtk, int iFrames, int nWords, int fTransfer );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Simulates sequential circuit.]
Description [Takes sequential circuit (pNtk). Simulates the given number
(nFrames) of the circuit with the given number of machine words (nWords)
of random simulation data, starting from the initial state. If the initial
state of some latches is a don't-care, uses random input for that latch.]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Sim_SimulateSeqRandom( Abc_Ntk_t * pNtk, int nFrames, int nWords )
{
Vec_Ptr_t * vInfo;
Abc_Obj_t * pNode;
int i;
assert( Abc_NtkIsStrash(pNtk) );
vInfo = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), nWords * nFrames, 0 );
// set the constant data
pNode = Abc_AigConst1(pNtk->pManFunc);
Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nWords * nFrames, 1 );
// set the random PI data
Abc_NtkForEachPi( pNtk, pNode, i )
Sim_UtilSetRandom( Sim_SimInfoGet(vInfo,pNode), nWords * nFrames );
// set the initial state data
Abc_NtkForEachLatch( pNtk, pNode, i )
if ( Abc_LatchIsInit0(pNode) )
Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nWords, 0 );
else if ( Abc_LatchIsInit1(pNode) )
Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nWords, 1 );
else
Sim_UtilSetRandom( Sim_SimInfoGet(vInfo,pNode), nWords );
// simulate the nodes for the given number of timeframes
for ( i = 0; i < nFrames; i++ )
Sim_SimulateSeqFrame( vInfo, pNtk, i, nWords, (int)(i < nFrames-1) );
return vInfo;
}
/**Function*************************************************************
Synopsis [Simulates sequential circuit.]
Description [Takes sequential circuit (pNtk). Simulates the given number
(nFrames) of the circuit with the given model. The model is assumed to
contain values of PIs for each frame. The latches are initialized to
the initial state. One word of data is simulated.]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Sim_SimulateSeqModel( Abc_Ntk_t * pNtk, int nFrames, int * pModel )
{
Vec_Ptr_t * vInfo;
Abc_Obj_t * pNode;
unsigned * pUnsigned;
int i, k;
vInfo = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), nFrames, 0 );
// set the constant data
pNode = Abc_AigConst1(pNtk->pManFunc);
Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nFrames, 1 );
// set the random PI data
Abc_NtkForEachPi( pNtk, pNode, i )
{
pUnsigned = Sim_SimInfoGet(vInfo,pNode);
for ( k = 0; k < nFrames; k++ )
pUnsigned[k] = pModel[k * Abc_NtkPiNum(pNtk) + i] ? ~((unsigned)0) : 0;
}
// set the initial state data
Abc_NtkForEachLatch( pNtk, pNode, i )
{
pUnsigned = Sim_SimInfoGet(vInfo,pNode);
if ( Abc_LatchIsInit0(pNode) )
pUnsigned[0] = 0;
else if ( Abc_LatchIsInit1(pNode) )
pUnsigned[0] = ~((unsigned)0);
else
pUnsigned[0] = SIM_RANDOM_UNSIGNED;
}
// simulate the nodes for the given number of timeframes
for ( i = 0; i < nFrames; i++ )
Sim_SimulateSeqFrame( vInfo, pNtk, i, 1, (int)(i < nFrames-1) );
/*
// print the simulated values
for ( i = 0; i < nFrames; i++ )
{
printf( "Frame %d : ", i+1 );
Abc_NtkForEachPi( pNtk, pNode, k )
printf( "%d", Sim_SimInfoGet(vInfo,pNode)[i] > 0 );
printf( " " );
Abc_NtkForEachLatch( pNtk, pNode, k )
printf( "%d", Sim_SimInfoGet(vInfo,pNode)[i] > 0 );
printf( " " );
Abc_NtkForEachPo( pNtk, pNode, k )
printf( "%d", Sim_SimInfoGet(vInfo,pNode)[i] > 0 );
printf( "\n" );
}
printf( "\n" );
*/
return vInfo;
}
/**Function*************************************************************
Synopsis [Simulates one frame of sequential circuit.]
Description [Assumes that the latches and POs are already initialized.
In the end transfers the data to the latches of the next frame.]
SideEffects []
SeeAlso []
***********************************************************************/
void Sim_SimulateSeqFrame( Vec_Ptr_t * vInfo, Abc_Ntk_t * pNtk, int iFrames, int nWords, int fTransfer )
{
Abc_Obj_t * pNode;
int i;
Abc_NtkForEachNode( pNtk, pNode, i )
Sim_UtilSimulateNodeOne( pNode, vInfo, nWords, iFrames * nWords );
Abc_NtkForEachPo( pNtk, pNode, i )
Sim_UtilTransferNodeOne( pNode, vInfo, nWords, iFrames * nWords, 0 );
if ( !fTransfer )
return;
Abc_NtkForEachLatch( pNtk, pNode, i )
Sim_UtilTransferNodeOne( pNode, vInfo, nWords, iFrames * nWords, 1 );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
src/opt/sim/simSwitch.c
......@@ -65,7 +65,7 @@ Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns )
Abc_NtkForEachCi( pNtk, pNode, i )
{
pSimInfo = Vec_PtrEntry(vSimInfo, pNode->Id);
Sim_UtilGetRandom( pSimInfo, nSimWords );
Sim_UtilSetRandom( pSimInfo, nSimWords );
pSwitching[pNode->Id] = Sim_ComputeSwitching( pSimInfo, nSimWords );
}
// simulate the internal nodes
......@@ -73,7 +73,7 @@ Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns )
Vec_PtrForEachEntry( vNodes, pNode, i )
{
pSimInfo = Vec_PtrEntry(vSimInfo, pNode->Id);
Sim_UtilSimulateNodeOne( pNode, vSimInfo, nSimWords );
Sim_UtilSimulateNodeOne( pNode, vSimInfo, nSimWords, 0 );
pSwitching[pNode->Id] = Sim_ComputeSwitching( pSimInfo, nSimWords );
}
Vec_PtrFree( vNodes );
......
src/opt/sim/simSym.c
......@@ -71,7 +71,7 @@ p->timeStruct = clock() - clk;
for ( i = 1; i <= 1000; i++ )
{
// simulate this pattern
Sim_UtilGetRandom( p->uPatRand, p->nSimWords );
Sim_UtilSetRandom( p->uPatRand, p->nSimWords );
Sim_SymmsSimulate( p, p->uPatRand, p->vMatrNonSymms );
if ( i % 50 != 0 )
continue;
......
src/opt/sim/simSymSim.c
......@@ -57,7 +57,7 @@ clk = clock();
{
if ( Abc_NodeIsConst(pNode) )
continue;
Sim_UtilSimulateNodeOne( pNode, p->vSim, p->nSimWords );
Sim_UtilSimulateNodeOne( pNode, p->vSim, p->nSimWords, 0 );
}
p->timeSim += clock() - clk;
// collect info into the CO matrices
......
src/opt/sim/simUtils.c
......@@ -299,7 +299,7 @@ void Sim_UtilSimulateNode( Sim_Man_t * p, Abc_Obj_t * pNode, bool fType, bool fT
SeeAlso []
***********************************************************************/
void Sim_UtilSimulateNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimWords )
void Sim_UtilSimulateNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimWords, int nOffset )
{
unsigned * pSimmNode, * pSimmNode1, * pSimmNode2;
int k, fComp1, fComp2;
......@@ -310,6 +310,9 @@ void Sim_UtilSimulateNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimW
pSimmNode = Vec_PtrEntry(vSimInfo, pNode->Id);
pSimmNode1 = Vec_PtrEntry(vSimInfo, Abc_ObjFaninId0(pNode));
pSimmNode2 = Vec_PtrEntry(vSimInfo, Abc_ObjFaninId1(pNode));
pSimmNode += nOffset;
pSimmNode1 += nOffset;
pSimmNode2 += nOffset;
fComp1 = Abc_ObjFaninC0(pNode);
fComp2 = Abc_ObjFaninC1(pNode);
if ( fComp1 && fComp2 )
......@@ -328,6 +331,36 @@ void Sim_UtilSimulateNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimW
/**Function*************************************************************
Synopsis [Simulates one node.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Sim_UtilTransferNodeOne( Abc_Obj_t * pNode, Vec_Ptr_t * vSimInfo, int nSimWords, int nOffset, int fShift )
{
unsigned * pSimmNode, * pSimmNode1;
int k, fComp1;
// simulate the internal nodes
assert( Abc_ObjIsCo(pNode) );
pSimmNode = Vec_PtrEntry(vSimInfo, pNode->Id);
pSimmNode1 = Vec_PtrEntry(vSimInfo, Abc_ObjFaninId0(pNode));
pSimmNode += nOffset + (fShift > 0)*nSimWords;
pSimmNode1 += nOffset;
fComp1 = Abc_ObjFaninC0(pNode);
if ( fComp1 )
for ( k = 0; k < nSimWords; k++ )
pSimmNode[k] = ~pSimmNode1[k];
else
for ( k = 0; k < nSimWords; k++ )
pSimmNode[k] = pSimmNode1[k];
}
/**Function*************************************************************
Synopsis [Returns 1 if the simulation infos are equal.]
Description []
......@@ -380,10 +413,31 @@ int Sim_UtilCountOnes( unsigned * pSimInfo, int nSimWords )
return nOnes;
}
/**Function*************************************************************
Synopsis [Counts the number of 1's in the bitstring.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Sim_UtilCountOnesArray( Vec_Ptr_t * vInfo, int nSimWords )
{
Vec_Int_t * vCounters;
unsigned * pSimInfo;
int i;
vCounters = Vec_IntStart( Vec_PtrSize(vInfo) );
Vec_PtrForEachEntry( vInfo, pSimInfo, i )
Vec_IntWriteEntry( vCounters, i, Sim_UtilCountOnes(pSimInfo, nSimWords) );
return vCounters;
}
/**Function*************************************************************
Synopsis [Returns the random pattern.]
Synopsis [Returns random patterns.]
Description []
......@@ -392,7 +446,7 @@ int Sim_UtilCountOnes( unsigned * pSimInfo, int nSimWords )
SeeAlso []
***********************************************************************/
void Sim_UtilGetRandom( unsigned * pPatRand, int nSimWords )
void Sim_UtilSetRandom( unsigned * pPatRand, int nSimWords )
{
int k;
for ( k = 0; k < nSimWords; k++ )
......@@ -401,6 +455,104 @@ void Sim_UtilGetRandom( unsigned * pPatRand, int nSimWords )
/**Function*************************************************************
Synopsis [Returns complemented patterns.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Sim_UtilSetCompl( unsigned * pPatRand, int nSimWords )
{
int k;
for ( k = 0; k < nSimWords; k++ )
pPatRand[k] = ~pPatRand[k];
}
/**Function*************************************************************
Synopsis [Returns constant patterns.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Sim_UtilSetConst( unsigned * pPatRand, int nSimWords, int fConst1 )
{
int k;
for ( k = 0; k < nSimWords; k++ )
pPatRand[k] = 0;
if ( fConst1 )
Sim_UtilSetCompl( pPatRand, nSimWords );
}
/**Function*************************************************************
Synopsis [Returns 1 if equal.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Sim_UtilInfoIsEqual( unsigned * pPats1, unsigned * pPats2, int nSimWords )
{
int k;
for ( k = 0; k < nSimWords; k++ )
if ( pPats1[k] != pPats2[k] )
return 0;
return 1;
}
/**Function*************************************************************
Synopsis [Returns 1 if Node1 implies Node2.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Sim_UtilInfoIsImp( unsigned * pPats1, unsigned * pPats2, int nSimWords )
{
int k;
for ( k = 0; k < nSimWords; k++ )
if ( pPats1[k] & ~pPats2[k] )
return 0;
return 1;
}
/**Function*************************************************************
Synopsis [Returns 1 if Node1 v Node2 is always true.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Sim_UtilInfoIsClause( unsigned * pPats1, unsigned * pPats2, int nSimWords )
{
int k;
for ( k = 0; k < nSimWords; k++ )
if ( ~pPats1[k] & ~pPats2[k] )
return 0;
return 1;
}
/**Function*************************************************************
Synopsis [Counts the total number of pairs.]
Description []
......
src/sat/fraig/fraig.h
......@@ -153,6 +153,9 @@ extern void Fraig_ParamsSetDefaultFull( Fraig_Params_t * pParams
extern Fraig_Man_t * Fraig_ManCreate( Fraig_Params_t * pParams );
extern void Fraig_ManFree( Fraig_Man_t * pMan );
extern void Fraig_ManPrintStats( Fraig_Man_t * p );
extern Fraig_NodeVec_t * Fraig_ManGetSimInfo( Fraig_Man_t * p );
extern int Fraig_ManCheckClauseUsingSimInfo( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_Node_t * pNode2 );
extern void Fraig_ManAddClause( Fraig_Man_t * p, Fraig_Node_t ** ppNodes, int nNodes );
/*=== fraigDfs.c =============================================================*/
extern Fraig_NodeVec_t * Fraig_Dfs( Fraig_Man_t * pMan, int fEquiv );
......@@ -168,6 +171,7 @@ extern int Fraig_NodesAreEqual( Fraig_Man_t * p, Fraig_Node_t *
extern int Fraig_NodeIsEquivalent( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t * pNew, int nBTLimit, int nTimeLimit );
extern void Fraig_ManProveMiter( Fraig_Man_t * p );
extern int Fraig_ManCheckMiter( Fraig_Man_t * p );
extern int Fraig_ManCheckClauseUsingSat( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_Node_t * pNode2, int nBTLimit );
/*=== fraigVec.c ===============================================================*/
extern Fraig_NodeVec_t * Fraig_NodeVecAlloc( int nCap );
......
src/sat/fraig/fraigInt.h
......@@ -280,9 +280,9 @@ struct Fraig_NodeStruct_t_
// the vector of nodes
struct Fraig_NodeVecStruct_t_
{
Fraig_Node_t ** pArray; // the array of nodes
int nSize; // the number of entries in the array
int nCap; // the number of allocated entries
int nSize; // the number of entries in the array
Fraig_Node_t ** pArray; // the array of nodes
};
// the hash table
......@@ -381,6 +381,8 @@ extern void Fraig_FeedBackTest( Fraig_Man_t * p );
extern int Fraig_FeedBackCompress( Fraig_Man_t * p );
extern int * Fraig_ManAllocCounterExample( Fraig_Man_t * p );
extern int * Fraig_ManSaveCounterExample( Fraig_Man_t * p, Fraig_Node_t * pNode );
/*=== fraigMan.c =============================================================*/
extern void Fraig_ManCreateSolver( Fraig_Man_t * p );
/*=== fraigMem.c =============================================================*/
extern Fraig_MemFixed_t * Fraig_MemFixedStart( int nEntrySize );
extern void Fraig_MemFixedStop( Fraig_MemFixed_t * p, int fVerbose );
......
src/sat/fraig/fraigMan.c
......@@ -225,6 +225,31 @@ void Fraig_ManFree( Fraig_Man_t * p )
FREE( p );
}
/**Function*************************************************************
Synopsis [Prepares the SAT solver to run on the two nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_ManCreateSolver( Fraig_Man_t * p )
{
extern int timeSelect;
extern int timeAssign;
assert( p->pSat == NULL );
// allocate data for SAT solving
p->pSat = Msat_SolverAlloc( 500, 1, 1, 1, 1, 0 );
p->vVarsInt = Msat_SolverReadConeVars( p->pSat );
p->vAdjacents = Msat_SolverReadAdjacents( p->pSat );
p->vVarsUsed = Msat_SolverReadVarsUsed( p->pSat );
timeSelect = 0;
timeAssign = 0;
}
/**Function*************************************************************
......@@ -264,6 +289,168 @@ void Fraig_ManPrintStats( Fraig_Man_t * p )
// PRT( "Assignment", timeAssign );
}
/**Function*************************************************************
Synopsis [Allocates simulation information for all nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Fraig_NodeVec_t * Fraig_UtilInfoAlloc( int nSize, int nWords, bool fClean )
{
Fraig_NodeVec_t * vInfo;
unsigned * pUnsigned;
int i;
assert( nSize > 0 && nWords > 0 );
vInfo = Fraig_NodeVecAlloc( nSize );
pUnsigned = ALLOC( unsigned, nSize * nWords );
vInfo->pArray[0] = (Fraig_Node_t *)pUnsigned;
if ( fClean )
memset( pUnsigned, 0, sizeof(unsigned) * nSize * nWords );
for ( i = 1; i < nSize; i++ )
vInfo->pArray[i] = (Fraig_Node_t *)(((unsigned *)vInfo->pArray[i-1]) + nWords);
vInfo->nSize = nSize;
return vInfo;
}
/**Function*************************************************************
Synopsis [Returns simulation info of all nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Fraig_NodeVec_t * Fraig_ManGetSimInfo( Fraig_Man_t * p )
{
Fraig_NodeVec_t * vInfo;
Fraig_Node_t * pNode;
unsigned * pUnsigned;
int nRandom, nDynamic;
int i, k, nWords;
nRandom = Fraig_ManReadPatternNumRandom( p );
nDynamic = Fraig_ManReadPatternNumDynamic( p );
nWords = nRandom / 32 + nDynamic / 32;
vInfo = Fraig_UtilInfoAlloc( p->vNodes->nSize, nWords, 0 );
for ( i = 0; i < p->vNodes->nSize; i++ )
{
pNode = p->vNodes->pArray[i];
assert( i == pNode->Num );
pUnsigned = (unsigned *)vInfo->pArray[i];
for ( k = 0; k < nRandom / 32; k++ )
pUnsigned[k] = pNode->puSimR[k];
for ( k = 0; k < nDynamic / 32; k++ )
pUnsigned[nRandom / 32 + k] = pNode->puSimD[k];
}
return vInfo;
}
/**Function*************************************************************
Synopsis [Returns 1 if A v B is always true based on the siminfo.]
Description [A v B is always true iff A' * B' is always false.]
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_ManCheckClauseUsingSimInfo( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_Node_t * pNode2 )
{
int fCompl1, fCompl2, i;
fCompl1 = 1 ^ Fraig_IsComplement(pNode1) ^ Fraig_Regular(pNode1)->fInv;
fCompl2 = 1 ^ Fraig_IsComplement(pNode2) ^ Fraig_Regular(pNode2)->fInv;
pNode1 = Fraig_Regular(pNode1);
pNode2 = Fraig_Regular(pNode2);
assert( pNode1 != pNode2 );
// check the simulation info
if ( fCompl1 && fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( ~pNode1->puSimR[i] & ~pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( ~pNode1->puSimD[i] & ~pNode2->puSimD[i] )
return 0;
return 1;
}
if ( !fCompl1 && fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( pNode1->puSimR[i] & ~pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( pNode1->puSimD[i] & ~pNode2->puSimD[i] )
return 0;
return 1;
}
if ( fCompl1 && !fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( ~pNode1->puSimR[i] & pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( ~pNode1->puSimD[i] & pNode2->puSimD[i] )
return 0;
return 1;
}
// if ( fCompl1 && fCompl2 )
{
for ( i = 0; i < p->nWordsRand; i++ )
if ( pNode1->puSimR[i] & pNode2->puSimR[i] )
return 0;
for ( i = 0; i < p->iWordStart; i++ )
if ( pNode1->puSimD[i] & pNode2->puSimD[i] )
return 0;
return 1;
}
}
/**Function*************************************************************
Synopsis [Adds clauses to the solver.]
Description [This procedure is used to add external clauses to the solver.
The clauses are given by sets of nodes. Each node stands for one literal.
If the node is complemented, the literal is negated.]
SideEffects []
SeeAlso []
***********************************************************************/
void Fraig_ManAddClause( Fraig_Man_t * p, Fraig_Node_t ** ppNodes, int nNodes )
{
Fraig_Node_t * pNode;
int i, fComp, RetValue;
if ( p->pSat == NULL )
Fraig_ManCreateSolver( p );
// create four clauses
Msat_IntVecClear( p->vProj );
for ( i = 0; i < nNodes; i++ )
{
pNode = Fraig_Regular(ppNodes[i]);
fComp = Fraig_IsComplement(ppNodes[i]);
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode->Num, fComp) );
// printf( "%d(%d) ", pNode->Num, fComp );
}
// printf( "\n" );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
}
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
......
src/sat/fraig/fraigSat.c
......@@ -97,7 +97,7 @@ void Fraig_ManProveMiter( Fraig_Man_t * p )
continue;
if ( Fraig_NodeIsEquivalent( p, p->pConst1, pNode, -1, p->nSeconds ) )
{
if ( Fraig_IsComplement(p->vOutputs->pArray[i]) )
if ( Fraig_IsComplement(p->vOutputs->pArray[i]) ^ Fraig_NodeComparePhase(p->pConst1, pNode) )
p->vOutputs->pArray[i] = Fraig_Not(p->pConst1);
else
p->vOutputs->pArray[i] = p->pConst1;
......@@ -180,17 +180,7 @@ int Fraig_NodeIsEquivalent( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t *
// make sure the solver is allocated and has enough variables
if ( p->pSat == NULL )
{
extern int timeSelect;
extern int timeAssign;
// allocate data for SAT solving
p->pSat = Msat_SolverAlloc( 500, 1, 1, 1, 1, 0 );
p->vVarsInt = Msat_SolverReadConeVars( p->pSat );
p->vAdjacents = Msat_SolverReadAdjacents( p->pSat );
p->vVarsUsed = Msat_SolverReadVarsUsed( p->pSat );
timeSelect = 0;
timeAssign = 0;
}
Fraig_ManCreateSolver( p );
// make sure the SAT solver has enough variables
for ( i = Msat_SolverReadVarNum(p->pSat); i < p->vNodes->nSize; i++ )
Msat_SolverAddVar( p->pSat );
......@@ -365,32 +355,12 @@ int Fraig_NodeIsImplication( Fraig_Man_t * p, Fraig_Node_t * pOld, Fraig_Node_t
// make sure the solver is allocated and has enough variables
if ( p->pSat == NULL )
{
extern int timeSelect;
extern int timeAssign;
// allocate data for SAT solving
p->pSat = Msat_SolverAlloc( 500, 1, 1, 1, 1, 0 );
p->vVarsInt = Msat_SolverReadConeVars( p->pSat );
p->vAdjacents = Msat_SolverReadAdjacents( p->pSat );
p->vVarsUsed = Msat_SolverReadVarsUsed( p->pSat );
timeSelect = 0;
timeAssign = 0;
}
Fraig_ManCreateSolver( p );
// make sure the SAT solver has enough variables
for ( i = Msat_SolverReadVarNum(p->pSat); i < p->vNodes->nSize; i++ )
Msat_SolverAddVar( p->pSat );
/*
{
Fraig_Node_t * ppNodes[2] = { pOld, pNew };
extern void Fraig_MappingShowNodes( Fraig_Man_t * pMan, Fraig_Node_t ** ppRoots, int nRoots, char * pFileName );
Fraig_MappingShowNodes( p, ppNodes, 2, "temp_aig" );
}
*/
// get the logic cone
// get the logic cone
clk = clock();
Fraig_OrderVariables( p, pOld, pNew );
// Fraig_PrepareCones( p, pOld, pNew );
......@@ -449,8 +419,8 @@ if ( fVerbose )
PRT( "time", clock() - clk );
}
// record the counter example
// Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pOld, pNew );
// p->nSatCounterImp++;
Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pOld, pNew );
p->nSatCounterImp++;
return 0;
}
else // if ( RetValue1 == MSAT_UNKNOWN )
......@@ -461,6 +431,96 @@ p->time3 += clock() - clk;
}
}
/**Function*************************************************************
Synopsis [Prepares the SAT solver to run on the two nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Fraig_ManCheckClauseUsingSat( Fraig_Man_t * p, Fraig_Node_t * pNode1, Fraig_Node_t * pNode2, int nBTLimit )
{
Fraig_Node_t * pNode1R, * pNode2R;
int RetValue, RetValue1, i, clk;
int fVerbose = 0;
pNode1R = Fraig_Regular(pNode1);
pNode2R = Fraig_Regular(pNode2);
assert( pNode1R != pNode2R );
// make sure the solver is allocated and has enough variables
if ( p->pSat == NULL )
Fraig_ManCreateSolver( p );
// make sure the SAT solver has enough variables
for ( i = Msat_SolverReadVarNum(p->pSat); i < p->vNodes->nSize; i++ )
Msat_SolverAddVar( p->pSat );
// get the logic cone
clk = clock();
Fraig_OrderVariables( p, pNode1R, pNode2R );
// Fraig_PrepareCones( p, pNode1R, pNode2R );
p->timeTrav += clock() - clk;
////////////////////////////////////////////
// prepare the solver to run incrementally on these variables
//clk = clock();
Msat_SolverPrepare( p->pSat, p->vVarsInt );
//p->time3 += clock() - clk;
// solve under assumptions
// A = 1; B = 0 OR A = 1; B = 1
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1R->Num, !Fraig_IsComplement(pNode1)) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2R->Num, !Fraig_IsComplement(pNode2)) );
// run the solver
clk = clock();
RetValue1 = Msat_SolverSolve( p->pSat, p->vProj, nBTLimit, 1000000 );
p->timeSat += clock() - clk;
if ( RetValue1 == MSAT_FALSE )
{
//p->time1 += clock() - clk;
if ( fVerbose )
{
printf( "unsat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// add the clause
Msat_IntVecClear( p->vProj );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode1R->Num, Fraig_IsComplement(pNode1)) );
Msat_IntVecPush( p->vProj, MSAT_VAR2LIT(pNode2R->Num, Fraig_IsComplement(pNode2)) );
RetValue = Msat_SolverAddClause( p->pSat, p->vProj );
assert( RetValue );
// p->nSatProofImp++;
return 1;
}
else if ( RetValue1 == MSAT_TRUE )
{
//p->time2 += clock() - clk;
if ( fVerbose )
{
printf( "sat %d ", Msat_SolverReadBackTracks(p->pSat) );
PRT( "time", clock() - clk );
}
// record the counter example
// Fraig_FeedBack( p, Msat_SolverReadModelArray(p->pSat), p->vVarsInt, pNode1R, pNode2R );
p->nSatCounterImp++;
return 0;
}
else // if ( RetValue1 == MSAT_UNKNOWN )
{
p->time3 += clock() - clk;
p->nSatFailsImp++;
return 0;
}
}
/**Function*************************************************************
......
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