abcFpga.c 9.75 KB
Newer Older
Alan Mishchenko committed
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/**CFile****************************************************************

  FileName    [abcFpga.c]

  SystemName  [ABC: Logic synthesis and verification system.]

  PackageName [Network and node package.]

  Synopsis    [Interface with the FPGA mapping package.]

  Author      [Alan Mishchenko]
  
  Affiliation [UC Berkeley]

  Date        [Ver. 1.0. Started - June 20, 2005.]

  Revision    [$Id: abcFpga.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]

***********************************************************************/

21 22
#include "base/abc/abc.h"
#include "map/fpga/fpgaInt.h"
23 24

#ifdef ABC_USE_CUDD
25
#include "bdd/extrab/extraBdd.h"
26
#endif
Alan Mishchenko committed
27

28 29 30
ABC_NAMESPACE_IMPL_START


Alan Mishchenko committed
31 32 33 34
////////////////////////////////////////////////////////////////////////
///                        DECLARATIONS                              ///
////////////////////////////////////////////////////////////////////////

Alan Mishchenko committed
35
static Fpga_Man_t * Abc_NtkToFpga( Abc_Ntk_t * pNtk, int fRecovery, float * pSwitching, int fLatchPaths, int fVerbose );
Alan Mishchenko committed
36 37 38 39
static Abc_Ntk_t *  Abc_NtkFromFpga( Fpga_Man_t * pMan, Abc_Ntk_t * pNtk );
static Abc_Obj_t *  Abc_NodeFromFpga_rec( Abc_Ntk_t * pNtkNew, Fpga_Node_t * pNodeFpga );
 
////////////////////////////////////////////////////////////////////////
Alan Mishchenko committed
40
///                     FUNCTION DEFINITIONS                         ///
Alan Mishchenko committed
41 42 43 44 45 46 47 48 49 50 51 52 53
////////////////////////////////////////////////////////////////////////

/**Function*************************************************************

  Synopsis    [Interface with the FPGA mapping package.]

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
Alan Mishchenko committed
54
Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fLatchPaths, int fVerbose )
Alan Mishchenko committed
55
{
Alan Mishchenko committed
56
    int fShowSwitching = 1;
Alan Mishchenko committed
57 58
    Abc_Ntk_t * pNtkNew;
    Fpga_Man_t * pMan;
Alan Mishchenko committed
59
    Vec_Int_t * vSwitching = NULL;
Alan Mishchenko committed
60
    float * pSwitching = NULL;
Alan Mishchenko committed
61
    int Num;
Alan Mishchenko committed
62

Alan Mishchenko committed
63
    assert( Abc_NtkIsStrash(pNtk) );
Alan Mishchenko committed
64 65

    // print a warning about choice nodes
Alan Mishchenko committed
66
    if ( (Num = Abc_NtkGetChoiceNum( pNtk )) )
67
        Abc_Print( 0, "Performing LUT mapping with %d choices.\n", Num );
Alan Mishchenko committed
68

Alan Mishchenko committed
69 70 71 72 73 74 75 76 77
    // compute switching activity
    fShowSwitching |= fSwitching;
    if ( fShowSwitching )
    {
        extern Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns );
        vSwitching = Sim_NtkComputeSwitching( pNtk, 4096 );
        pSwitching = (float *)vSwitching->pArray;
    }

Alan Mishchenko committed
78
    // perform FPGA mapping
Alan Mishchenko committed
79
    pMan = Abc_NtkToFpga( pNtk, fRecovery, pSwitching, fLatchPaths, fVerbose );    
Alan Mishchenko committed
80
    if ( pSwitching ) { assert(vSwitching); Vec_IntFree( vSwitching ); }
Alan Mishchenko committed
81 82
    if ( pMan == NULL )
        return NULL;
Alan Mishchenko committed
83
    Fpga_ManSetSwitching( pMan, fSwitching );
Alan Mishchenko committed
84 85 86
    Fpga_ManSetLatchPaths( pMan, fLatchPaths );
    Fpga_ManSetLatchNum( pMan, Abc_NtkLatchNum(pNtk) );
    Fpga_ManSetDelayTarget( pMan, DelayTarget );
Alan Mishchenko committed
87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
    if ( !Fpga_Mapping( pMan ) )
    {
        Fpga_ManFree( pMan );
        return NULL;
    }

    // transform the result of mapping into a BDD network
    pNtkNew = Abc_NtkFromFpga( pMan, pNtk );
    if ( pNtkNew == NULL )
        return NULL;
    Fpga_ManFree( pMan );

    // make the network minimum base
    Abc_NtkMinimumBase( pNtkNew );

Alan Mishchenko committed
102 103 104
    if ( pNtk->pExdc )
        pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );

Alan Mishchenko committed
105
    // make sure that everything is okay
Alan Mishchenko committed
106
    if ( !Abc_NtkCheck( pNtkNew ) )
Alan Mishchenko committed
107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
    {
        printf( "Abc_NtkFpga: The network check has failed.\n" );
        Abc_NtkDelete( pNtkNew );
        return NULL;
    }
    return pNtkNew;
}

/**Function*************************************************************

  Synopsis    [Load the network into FPGA manager.]

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
Alan Mishchenko committed
126
Fpga_Man_t * Abc_NtkToFpga( Abc_Ntk_t * pNtk, int fRecovery, float * pSwitching, int fLatchPaths, int fVerbose )
Alan Mishchenko committed
127 128 129 130 131 132
{
    Fpga_Man_t * pMan;
    ProgressBar * pProgress;
    Fpga_Node_t * pNodeFpga;
    Vec_Ptr_t * vNodes;
    Abc_Obj_t * pNode, * pFanin, * pPrev;
Alan Mishchenko committed
133
    float * pfArrivals;
Alan Mishchenko committed
134 135
    int i;

Alan Mishchenko committed
136
    assert( Abc_NtkIsStrash(pNtk) );
Alan Mishchenko committed
137 138

    // start the mapping manager and set its parameters
Alan Mishchenko committed
139
    pMan = Fpga_ManCreate( Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), fVerbose );
Alan Mishchenko committed
140 141 142
    if ( pMan == NULL )
        return NULL;
    Fpga_ManSetAreaRecovery( pMan, fRecovery );
Alan Mishchenko committed
143
    Fpga_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
Alan Mishchenko committed
144 145 146 147 148 149 150
    pfArrivals = Abc_NtkGetCiArrivalFloats(pNtk);
    if ( fLatchPaths )
    {
        for ( i = 0; i < Abc_NtkPiNum(pNtk); i++ )
            pfArrivals[i] = -FPGA_FLOAT_LARGE;
    }
    Fpga_ManSetInputArrivals( pMan, pfArrivals );
Alan Mishchenko committed
151 152 153

    // create PIs and remember them in the old nodes
    Abc_NtkCleanCopy( pNtk );
Alan Mishchenko committed
154
    Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Fpga_ManReadConst1(pMan);
Alan Mishchenko committed
155
    Abc_NtkForEachCi( pNtk, pNode, i )
Alan Mishchenko committed
156 157 158 159 160 161
    {
        pNodeFpga = Fpga_ManReadInputs(pMan)[i];
        pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
        if ( pSwitching )
            Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
    }
Alan Mishchenko committed
162 163

    // load the AIG into the mapper
Alan Mishchenko committed
164
    vNodes = Abc_AigDfs( pNtk, 0, 0 );
Alan Mishchenko committed
165
    pProgress = Extra_ProgressBarStart( stdout, vNodes->nSize );
166
    Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNode, i )
Alan Mishchenko committed
167 168 169 170 171 172 173 174 175
    {
        Extra_ProgressBarUpdate( pProgress, i, NULL );
        // add the node to the mapper
        pNodeFpga = Fpga_NodeAnd( pMan, 
            Fpga_NotCond( Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode) ),
            Fpga_NotCond( Abc_ObjFanin1(pNode)->pCopy, Abc_ObjFaninC1(pNode) ) );
        assert( pNode->pCopy == NULL );
        // remember the node
        pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
Alan Mishchenko committed
176 177
        if ( pSwitching )
            Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
Alan Mishchenko committed
178
        // set up the choice node
Alan Mishchenko committed
179
        if ( Abc_AigNodeIsChoice( pNode ) )
180
            for ( pPrev = pNode, pFanin = (Abc_Obj_t *)pNode->pData; pFanin; pPrev = pFanin, pFanin = (Abc_Obj_t *)pFanin->pData )
Alan Mishchenko committed
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
            {
                Fpga_NodeSetNextE( (Fpga_Node_t *)pPrev->pCopy, (Fpga_Node_t *)pFanin->pCopy );
                Fpga_NodeSetRepr( (Fpga_Node_t *)pFanin->pCopy, (Fpga_Node_t *)pNode->pCopy );
            }
    }
    Extra_ProgressBarStop( pProgress );
    Vec_PtrFree( vNodes );

    // set the primary outputs without copying the phase
    Abc_NtkForEachCo( pNtk, pNode, i )
        Fpga_ManReadOutputs(pMan)[i] = (Fpga_Node_t *)Abc_ObjFanin0(pNode)->pCopy;
    return pMan;
}

/**Function*************************************************************

  Synopsis    [Creates the mapped network.]

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
Abc_Ntk_t * Abc_NtkFromFpga( Fpga_Man_t * pMan, Abc_Ntk_t * pNtk )
{
    ProgressBar * pProgress;
    Abc_Ntk_t * pNtkNew;
    Abc_Obj_t * pNode, * pNodeNew;
Alan Mishchenko committed
211
    int i, nDupGates;
Alan Mishchenko committed
212
    // create the new network
Alan Mishchenko committed
213
    pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD );
Alan Mishchenko committed
214 215 216 217 218 219
    // make the mapper point to the new network
    Fpga_CutsCleanSign( pMan );
    Fpga_ManCleanData0( pMan );
    Abc_NtkForEachCi( pNtk, pNode, i )
        Fpga_NodeSetData0( Fpga_ManReadInputs(pMan)[i], (char *)pNode->pCopy );
    // set the constant node
Alan Mishchenko committed
220 221
//    if ( Fpga_NodeReadRefs(Fpga_ManReadConst1(pMan)) > 0 )
        Fpga_NodeSetData0( Fpga_ManReadConst1(pMan), (char *)Abc_NtkCreateNodeConst1(pNtkNew) );
Alan Mishchenko committed
222 223 224 225 226 227 228 229 230 231 232 233
    // process the nodes in topological order
    pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCoNum(pNtk) );
    Abc_NtkForEachCo( pNtk, pNode, i )
    {
        Extra_ProgressBarUpdate( pProgress, i, NULL );
        pNodeNew = Abc_NodeFromFpga_rec( pNtkNew, Fpga_ManReadOutputs(pMan)[i] );
        assert( !Abc_ObjIsComplement(pNodeNew) );
        Abc_ObjFanin0(pNode)->pCopy = pNodeNew;
    }
    Extra_ProgressBarStop( pProgress );
    // finalize the new network
    Abc_NtkFinalize( pNtk, pNtkNew );
Alan Mishchenko committed
234 235 236 237
    // remove the constant node if not used
    pNodeNew = (Abc_Obj_t *)Fpga_NodeReadData0(Fpga_ManReadConst1(pMan));
    if ( Abc_ObjFanoutNum(pNodeNew) == 0 )
        Abc_NtkDeleteObj( pNodeNew );
Alan Mishchenko committed
238
    // decouple the PO driver nodes to reduce the number of levels
Alan Mishchenko committed
239 240 241
    nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
    if ( nDupGates && Fpga_ManReadVerbose(pMan) )
        printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
Alan Mishchenko committed
242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276
    return pNtkNew;
}

/**Function*************************************************************

  Synopsis    [Derive one node after FPGA mapping.]

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
Abc_Obj_t * Abc_NodeFromFpga_rec( Abc_Ntk_t * pNtkNew, Fpga_Node_t * pNodeFpga )
{
    Fpga_Cut_t * pCutBest;
    Fpga_Node_t ** ppLeaves; 
    Abc_Obj_t * pNodeNew;
    int i, nLeaves;
    assert( !Fpga_IsComplement(pNodeFpga) );
    // return if the result if known
    pNodeNew = (Abc_Obj_t *)Fpga_NodeReadData0( pNodeFpga );
    if ( pNodeNew )
        return pNodeNew;
    assert( Fpga_NodeIsAnd(pNodeFpga) );
    // get the parameters of the best cut
    pCutBest = Fpga_NodeReadCutBest( pNodeFpga );
    ppLeaves = Fpga_CutReadLeaves( pCutBest );
    nLeaves  = Fpga_CutReadLeavesNum( pCutBest ); 
    // create a new node 
    pNodeNew = Abc_NtkCreateNode( pNtkNew );
    for ( i = 0; i < nLeaves; i++ )
        Abc_ObjAddFanin( pNodeNew, Abc_NodeFromFpga_rec(pNtkNew, ppLeaves[i]) );
    // derive the function of this node
277
    pNodeNew->pData = Fpga_TruthsCutBdd( pNtkNew->pManFunc, pCutBest );   Cudd_Ref( (DdNode *)pNodeNew->pData );
Alan Mishchenko committed
278 279 280 281 282 283 284 285 286
    Fpga_NodeSetData0( pNodeFpga, (char *)pNodeNew );
    return pNodeNew;
}

////////////////////////////////////////////////////////////////////////
///                       END OF FILE                                ///
////////////////////////////////////////////////////////////////////////


287 288
ABC_NAMESPACE_IMPL_END