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abc
Commit 2b85f5ba by Alan Mishchenko
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Version abc50829

parent 3c25decf
Showing with 249 additions and 241 deletions
Makefile
......@@ -10,8 +10,8 @@ MODULES := src/base/abc src/base/cmd src/base/io src/base/main \
src/bdd/cudd src/bdd/dsd src/bdd/epd src/bdd/mtr src/bdd/parse src/bdd/reo \
src/map/fpga src/map/mapper src/map/mio src/map/super \
src/misc/extra src/misc/st src/misc/util src/misc/vec \
src/opt/fxu src/opt/rwr \
src/sat/asat src/sat/fraig src/sat/msat src/sat/sim \
src/opt/cut src/opt/fxu src/opt/rwr \
src/sat/asat src/sat/csat src/sat/msat src/sat/fraig src/sat/sim \
src/seq \
src/sop/ft src/sop/mvc
......
abc.opt
No preview for this file type
abc.rc
......@@ -32,7 +32,7 @@ alias wl write_blif
alias wp write_pla
alias cnf "st; renode -c; write_cnf"
alias prove "st; renode -c; sat"
alias opt "b; renode; sop; b; ps"
alias opt "b; renode; b; ps"
alias share "b; renode -m; fx; b; ps"
alias resyn "b; rwz; rfz; b; rwz; rfz; b; ps"
alias resyn "b; rw; rf; b; rwz; rfz; b; ps"
src/base/abc/abcAig.c
......@@ -294,7 +294,7 @@ bool Abc_AigCheck( Abc_Aig_t * pMan )
Counter++;
if ( Counter != Abc_NtkNodeNum(pMan->pNtkAig) )
{
printf( "Abc_AigCheck: The number of nodes in the structural hashing table is wrong.\n", Counter );
printf( "Abc_AigCheck: The number of nodes in the structural hashing table is wrong.\n" );
return 0;
}
return 1;
......@@ -315,7 +315,7 @@ int Abc_AigGetLevelNum( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, LevelsMax;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// perform the traversal
LevelsMax = 0;
Abc_NtkForEachCo( pNtk, pNode, i )
......@@ -718,12 +718,21 @@ void Abc_AigReplace_int( Abc_Aig_t * pMan )
// such node does not exist - modify the old fanout node
// (this way the change will not propagate all the way to the COs)
assert( Abc_ObjRegular(pFanin1) != Abc_ObjRegular(pFanin2) );
// if the node is in the level structure, remove it
if ( pFanout->fMarkA )
Abc_AigRemoveFromLevelStructure( pMan->vLevels, pFanout );
// if the node is in the level structure, remove it
if ( pFanout->fMarkB )
Abc_AigRemoveFromLevelStructureR( pMan->vLevelsR, pFanout );
// remove the old fanout node from the structural hashing table
Abc_AigAndDelete( pMan, pFanout );
// remove the fanins of the old fanout
Abc_ObjRemoveFanins( pFanout );
// recreate the old fanout with new fanins and add it to the table
Abc_AigAndCreateFrom( pMan, pFanin1, pFanin2, pFanout );
// schedule the updated fanout for updating direct level
assert( pFanout->fMarkA == 0 );
pFanout->fMarkA = 1;
......@@ -732,6 +741,7 @@ void Abc_AigReplace_int( Abc_Aig_t * pMan )
assert( pFanout->fMarkB == 0 );
pFanout->fMarkB = 1;
Vec_VecPush( pMan->vLevelsR, Abc_NodeReadReverseLevel(pFanout), pFanout );
// the fanout has changed, update EXOR status of its fanouts
Abc_ObjForEachFanout( pFanout, pFanoutFanout, v )
if ( Abc_NodeIsAigAnd(pFanoutFanout) )
......
src/base/abc/abcAttach.c
......@@ -64,7 +64,7 @@ int Abc_NtkAttach( Abc_Ntk_t * pNtk )
Mio_Gate_t ** ppGates;
int nGates, nFanins, i;
assert( Abc_NtkIsLogicSop(pNtk) );
assert( Abc_NtkIsSopLogic(pNtk) );
// check that the library is available
pGenlib = Abc_FrameReadLibGen(Abc_FrameGetGlobalFrame());
......@@ -142,7 +142,7 @@ int Abc_NtkAttach( Abc_Ntk_t * pNtk )
// replace SOP representation by the gate representation
Abc_NtkForEachNode( pNtk, pNode, i )
pNode->pData = pNode->pCopy, pNode->pCopy = NULL;
pNtk->Type = ABC_NTK_LOGIC_MAP;
pNtk->ntkFunc = ABC_FUNC_MAP;
Extra_MmFlexStop( pNtk->pManFunc, 0 );
pNtk->pManFunc = pGenlib;
......
src/base/abc/abcBalance.c
......@@ -48,9 +48,9 @@ Abc_Ntk_t * Abc_NtkBalance( Abc_Ntk_t * pNtk, bool fDuplicate )
{
int fCheck = 1;
Abc_Ntk_t * pNtkAig;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// perform balancing
pNtkAig = Abc_NtkStartFrom( pNtk, ABC_NTK_AIG );
pNtkAig = Abc_NtkStartFrom( pNtk, ABC_TYPE_STRASH, ABC_FUNC_AIG );
Abc_NtkBalancePerform( pNtk, pNtkAig, fDuplicate );
Abc_NtkFinalize( pNtk, pNtkAig );
// make sure everything is okay
......
src/base/abc/abcCheck.c
......@@ -57,12 +57,17 @@ bool Abc_NtkCheck( Abc_Ntk_t * pNtk )
Abc_Obj_t * pObj, * pNet, * pNode;
int i;
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsAig(pNtk) && !Abc_NtkIsSeq(pNtk) )
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) && !Abc_NtkIsSeq(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown network type.\n" );
return 0;
}
if ( Abc_NtkIsMapped(pNtk) )
if ( !Abc_NtkHasSop(pNtk) && !Abc_NtkHasBdd(pNtk) && !Abc_NtkHasAig(pNtk) && !Abc_NtkHasMapping(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown functionality type.\n" );
return 0;
}
if ( Abc_NtkHasMapping(pNtk) )
{
if ( pNtk->pManFunc != Abc_FrameReadLibGen(Abc_FrameGetGlobalFrame()) )
{
......@@ -110,9 +115,9 @@ bool Abc_NtkCheck( Abc_Ntk_t * pNtk )
}
// check the nodes
if ( Abc_NtkIsAig(pNtk) || Abc_NtkIsSeq(pNtk) )
if ( Abc_NtkHasAig(pNtk) )
{
if ( Abc_NtkIsAig(pNtk) )
if ( Abc_NtkIsStrash(pNtk) )
Abc_AigCheck( pNtk->pManFunc );
}
else
......@@ -474,7 +479,7 @@ bool Abc_NtkCheckNode( Abc_Ntk_t * pNtk, Abc_Obj_t * pNode )
return 0;
}
// the netlist and SOP logic network should have SOPs
if ( Abc_NtkIsNetlistSop(pNtk) || Abc_NtkIsLogicSop(pNtk) )
if ( Abc_NtkHasSop(pNtk) )
{
if ( !Abc_SopCheck( pNode->pData, Abc_ObjFaninNum(pNode) ) )
{
......@@ -482,7 +487,7 @@ bool Abc_NtkCheckNode( Abc_Ntk_t * pNtk, Abc_Obj_t * pNode )
return 0;
}
}
else if ( Abc_NtkIsLogicBdd(pNtk) )
else if ( Abc_NtkHasBdd(pNtk) )
{
int nSuppSize = Cudd_SupportSize(pNtk->pManFunc, pNode->pData);
if ( nSuppSize > Abc_ObjFaninNum(pNode) )
......@@ -491,7 +496,7 @@ bool Abc_NtkCheckNode( Abc_Ntk_t * pNtk, Abc_Obj_t * pNode )
return 0;
}
}
else if ( !Abc_NtkIsMapped(pNtk) )
else if ( !Abc_NtkHasMapping(pNtk) )
{
assert( 0 );
}
......
src/base/abc/abcCollapse.c
......@@ -49,7 +49,7 @@ Abc_Ntk_t * Abc_NtkCollapse( Abc_Ntk_t * pNtk, int fVerbose )
Abc_Ntk_t * pNtkNew;
DdManager * dd;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// compute the global BDDs
dd = Abc_NtkGlobalBdds( pNtk, 0 );
......@@ -230,7 +230,7 @@ Abc_Ntk_t * Abc_NtkFromGlobalBdds( DdManager * dd, Abc_Ntk_t * pNtk )
Abc_Obj_t * pNode, * pNodeNew;
int i;
// start the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_BDD );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_BDD );
// make sure the new manager has the same number of inputs
Cudd_bddIthVar( pNtkNew->pManFunc, dd->size-1 );
// process the POs
......
src/base/abc/abcCut.c
......@@ -49,7 +49,7 @@ Cut_Man_t * Abc_NtkCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams )
int i;
int clk = clock();
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the manager
pParams->nIdsMax = Abc_NtkObjNumMax( pNtk );
......
src/base/abc/abcDfs.c
......@@ -223,7 +223,7 @@ Vec_Ptr_t * Abc_AigDfs( Abc_Ntk_t * pNtk, int fCollectAll, int fCollectCos )
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode;
int i;
assert( Abc_NtkIsAig(pNtk) || Abc_NtkIsSeq(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// set the traversal ID
Abc_NtkIncrementTravId( pNtk );
// start the array of nodes
......
src/base/abc/abcDsd.c
......@@ -60,7 +60,7 @@ Abc_Ntk_t * Abc_NtkDsdGlobal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool
Abc_Ntk_t * pNtkNew;
DdManager * dd;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// perform FPGA mapping
dd = Abc_NtkGlobalBdds( pNtk, 0 );
......@@ -112,7 +112,7 @@ Abc_Ntk_t * Abc_NtkDsdInternal( DdManager * dd, Abc_Ntk_t * pNtk, bool fVerbose,
return NULL;
// start the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_BDD );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_BDD );
// make sure the new manager has enough inputs
Cudd_bddIthVar( pNtkNew->pManFunc, dd->size-1 );
// put the results into the new network (save new CO drivers in old CO drivers)
......@@ -324,7 +324,7 @@ int Abc_NtkDsdRecursive( Abc_Ntk_t * pNtk, bool fVerbose )
Vec_Ptr_t * vNodes;
int i;
assert( Abc_NtkIsLogicBdd(pNtk) );
assert( Abc_NtkIsBddLogic(pNtk) );
// make the network minimum base
Abc_NtkMinimumBase( pNtk );
......
src/base/abc/abcFpga.c
......@@ -50,7 +50,7 @@ Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, int fRecovery, int fVerbose )
Abc_Ntk_t * pNtkNew;
Fpga_Man_t * pMan;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// print a warning about choice nodes
if ( Abc_NtkCountChoiceNodes( pNtk ) )
......@@ -105,7 +105,7 @@ Fpga_Man_t * Abc_NtkToFpga( Abc_Ntk_t * pNtk, int fRecovery, int fVerbose )
Abc_Obj_t * pNode, * pFanin, * pPrev;
int i;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Fpga_ManCreate( Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), fVerbose );
......@@ -174,7 +174,7 @@ Abc_Ntk_t * Abc_NtkFromFpga( Fpga_Man_t * pMan, Abc_Ntk_t * pNtk )
Abc_Obj_t * pNode, * pNodeNew;
int i, nDupGates;
// create the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_BDD );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_BDD );
// make the mapper point to the new network
Fpga_CutsCleanSign( pMan );
Fpga_ManCleanData0( pMan );
......
src/base/abc/abcFraig.c
......@@ -92,7 +92,7 @@ Fraig_Man_t * Abc_NtkToFraig( Abc_Ntk_t * pNtk, Fraig_Params_t * pParams, int fA
Abc_Obj_t * pNode, * pConst1, * pReset;
int i;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// create the FRAIG manager
pMan = Fraig_ManCreate( pParams );
......@@ -148,7 +148,7 @@ Abc_Ntk_t * Abc_NtkFromFraig( Fraig_Man_t * pMan, Abc_Ntk_t * pNtk )
Abc_Obj_t * pNode;//, * pNodeNew;
int i;
// create the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_AIG );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_STRASH, ABC_FUNC_AIG );
// make the mapper point to the new network
Abc_NtkForEachCi( pNtk, pNode, i )
Fraig_NodeSetData1( Fraig_ManReadIthVar(pMan, i), (Fraig_Node_t *)pNode->pCopy );
......@@ -249,7 +249,7 @@ Abc_Ntk_t * Abc_NtkFraigTrust( Abc_Ntk_t * pNtk )
int fCheck = 1;
Abc_Ntk_t * pNtkNew;
if ( !Abc_NtkIsLogicSop(pNtk) )
if ( !Abc_NtkIsSopLogic(pNtk) )
{
printf( "Abc_NtkFraigTrust: Trust mode works for netlists and logic SOP networks.\n" );
return NULL;
......@@ -262,7 +262,7 @@ Abc_Ntk_t * Abc_NtkFraigTrust( Abc_Ntk_t * pNtk )
}
// perform strashing
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_AIG );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_STRASH, ABC_FUNC_AIG );
Abc_NtkFraigTrustOne( pNtk, pNtkNew );
Abc_NtkFinalize( pNtk, pNtkNew );
......@@ -421,9 +421,9 @@ int Abc_NtkFraigStore( Abc_Ntk_t * pNtk )
Abc_Ntk_t * pStore;
int nAndsOld;
if ( !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsAig(pNtk) )
if ( !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) )
{
printf( "Convert netlist into a logic network before adding to storage.\n" );
printf( "The netlist need to be converted into a logic network before adding it to storage.\n" );
return 0;
}
......
src/base/abc/abcFunc.c
......@@ -48,7 +48,7 @@ int Abc_NtkSopToBdd( Abc_Ntk_t * pNtk )
DdManager * dd;
int nFaninsMax, i;
assert( Abc_NtkIsLogicSop(pNtk) );
assert( Abc_NtkIsSopLogic(pNtk) );
// start the functionality manager
nFaninsMax = Abc_NtkGetFaninMax( pNtk );
......@@ -74,7 +74,7 @@ int Abc_NtkSopToBdd( Abc_Ntk_t * pNtk )
pNtk->pManFunc = dd;
// update the network type
pNtk->Type = ABC_NTK_LOGIC_BDD;
pNtk->ntkFunc = ABC_FUNC_BDD;
return 1;
}
......@@ -152,12 +152,12 @@ int Abc_NtkBddToSop( Abc_Ntk_t * pNtk )
int RetValue, i;
Vec_Str_t * vCube;
assert( Abc_NtkIsLogicBdd(pNtk) );
assert( Abc_NtkIsBddLogic(pNtk) );
Cudd_zddVarsFromBddVars( dd, 2 );
// allocate the new manager
pNtk->pManFunc = Extra_MmFlexStart();
// update the network type
pNtk->Type = ABC_NTK_LOGIC_SOP;
pNtk->ntkFunc = ABC_FUNC_SOP;
// go through the objects
vCube = Vec_StrAlloc( 100 );
......@@ -165,7 +165,6 @@ int Abc_NtkBddToSop( Abc_Ntk_t * pNtk )
{
assert( pNode->pData );
bFunc = pNode->pData;
//Extra_bddPrint( dd, bFunc ); printf( "\n" ); printf( "\n" );
pNode->pData = Abc_ConvertBddToSop( pNtk->pManFunc, dd, bFunc, bFunc, Abc_ObjFaninNum(pNode), vCube, -1 );
if ( pNode->pData == NULL )
return 0;
......@@ -375,7 +374,7 @@ int Abc_ConvertZddToSop( DdManager * dd, DdNode * zCover, char * pSop, int nFani
***********************************************************************/
void Abc_NodeBddToCnf( Abc_Obj_t * pNode, Extra_MmFlex_t * pMmMan, Vec_Str_t * vCube, char ** ppSop0, char ** ppSop1 )
{
assert( Abc_NtkIsLogicBdd(pNode->pNtk) );
assert( Abc_NtkIsBddLogic(pNode->pNtk) );
*ppSop0 = Abc_ConvertBddToSop( pMmMan, pNode->pNtk->pManFunc, pNode->pData, pNode->pData, Abc_ObjFaninNum(pNode), vCube, 0 );
*ppSop1 = Abc_ConvertBddToSop( pMmMan, pNode->pNtk->pManFunc, pNode->pData, pNode->pData, Abc_ObjFaninNum(pNode), vCube, 1 );
}
......
src/base/abc/abcFxu.c
......@@ -54,9 +54,11 @@ bool Abc_NtkFastExtract( Abc_Ntk_t * pNtk, Fxu_Data_t * p )
{
int fCheck = 1;
assert( Abc_NtkIsLogicBdd(pNtk) || Abc_NtkIsLogicSop(pNtk) );
assert( Abc_NtkIsLogic(pNtk) );
// convert nodes to SOPs
if ( Abc_NtkIsLogicBdd(pNtk) )
if ( Abc_NtkIsMappedLogic(pNtk) )
Abc_NtkUnmap(pNtk);
else if ( Abc_NtkIsBddLogic(pNtk) )
Abc_NtkBddToSop(pNtk);
else
{ // to make sure the SOPs are SCC-free
......
src/base/abc/abcMap.c
......@@ -61,7 +61,7 @@ Abc_Ntk_t * Abc_NtkMap( Abc_Ntk_t * pNtk, double DelayTarget, int fRecovery, int
Map_Man_t * pMan;
int clk;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// check that the library is available
if ( Abc_FrameReadLibGen(Abc_FrameGetGlobalFrame()) == NULL )
......@@ -130,7 +130,7 @@ Map_Man_t * Abc_NtkToMap( Abc_Ntk_t * pNtk, double DelayTarget, int fRecovery, i
Abc_Obj_t * pNode, * pFanin, * pPrev;
int i;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Map_ManCreate( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk), Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk), fVerbose );
......@@ -202,7 +202,7 @@ Abc_Ntk_t * Abc_NtkFromMap( Map_Man_t * pMan, Abc_Ntk_t * pNtk )
int i, nDupGates;
// create the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_MAP );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_MAP );
// make the mapper point to the new network
Map_ManCleanData( pMan );
Abc_NtkForEachCi( pNtk, pNode, i )
......@@ -388,11 +388,11 @@ int Abc_NtkUnmap( Abc_Ntk_t * pNtk )
char * pSop;
int i;
assert( Abc_NtkIsLogicMap(pNtk) );
assert( Abc_NtkIsMappedLogic(pNtk) );
// update the functionality manager
assert( pNtk->pManFunc == Abc_FrameReadLibGen(Abc_FrameGetGlobalFrame()) );
pNtk->pManFunc = Extra_MmFlexStart();
pNtk->Type = ABC_NTK_LOGIC_SOP;
pNtk->ntkFunc = ABC_FUNC_SOP;
// update the nodes
Abc_NtkForEachNode( pNtk, pNode, i )
{
......@@ -424,7 +424,7 @@ Abc_Ntk_t * Abc_NtkSuperChoice( Abc_Ntk_t * pNtk )
Map_Man_t * pMan;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// check that the library is available
if ( Abc_FrameReadLibGen(Abc_FrameGetGlobalFrame()) == NULL )
......
src/base/abc/abcMinBase.c
......@@ -45,7 +45,7 @@ int Abc_NtkMinimumBase( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, Counter;
assert( Abc_NtkIsLogicBdd(pNtk) );
assert( Abc_NtkIsBddLogic(pNtk) );
Counter = 0;
Abc_NtkForEachNode( pNtk, pNode, i )
Counter += Abc_NodeMinimumBase( pNode );
......@@ -70,7 +70,7 @@ int Abc_NodeMinimumBase( Abc_Obj_t * pNode )
DdNode * bTemp;
int i, nVars;
assert( Abc_NtkIsLogicBdd(pNode->pNtk) );
assert( Abc_NtkIsBddLogic(pNode->pNtk) );
assert( Abc_ObjIsNode(pNode) );
// compute support
......
src/base/abc/abcMiter.c
......@@ -55,8 +55,8 @@ Abc_Ntk_t * Abc_NtkMiter( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int fComb )
if ( !Abc_NtkCompareSignals( pNtk1, pNtk2, fComb ) )
return NULL;
// make sure the circuits are strashed
fRemove1 = (!Abc_NtkIsAig(pNtk1)) && (pNtk1 = Abc_NtkStrash(pNtk1, 0));
fRemove2 = (!Abc_NtkIsAig(pNtk2)) && (pNtk2 = Abc_NtkStrash(pNtk2, 0));
fRemove1 = (!Abc_NtkIsStrash(pNtk1)) && (pNtk1 = Abc_NtkStrash(pNtk1, 0));
fRemove2 = (!Abc_NtkIsStrash(pNtk2)) && (pNtk2 = Abc_NtkStrash(pNtk2, 0));
if ( pNtk1 && pNtk2 )
pTemp = Abc_NtkMiterInt( pNtk1, pNtk2, fComb );
if ( fRemove1 ) Abc_NtkDelete( pNtk1 );
......@@ -81,11 +81,11 @@ Abc_Ntk_t * Abc_NtkMiterInt( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int fComb )
char Buffer[100];
Abc_Ntk_t * pNtkMiter;
assert( Abc_NtkIsAig(pNtk1) );
assert( Abc_NtkIsAig(pNtk2) );
assert( Abc_NtkIsStrash(pNtk1) );
assert( Abc_NtkIsStrash(pNtk2) );
// start the new network
pNtkMiter = Abc_NtkAlloc( ABC_NTK_AIG );
pNtkMiter = Abc_NtkAlloc( ABC_TYPE_STRASH, ABC_FUNC_AIG );
sprintf( Buffer, "%s_%s_miter", pNtk1->pName, pNtk2->pName );
pNtkMiter->pName = util_strsav(Buffer);
......@@ -317,13 +317,13 @@ Abc_Ntk_t * Abc_NtkMiterOne( Abc_Ntk_t * pNtk, int Out, int In1, int In2 )
Abc_Ntk_t * pNtkMiter;
Abc_Obj_t * pRoot, * pOutput1, * pOutput2, * pMiter;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
assert( Out < Abc_NtkCoNum(pNtk) );
assert( In1 < Abc_NtkCiNum(pNtk) );
assert( In2 < Abc_NtkCiNum(pNtk) );
// start the new network
pNtkMiter = Abc_NtkAlloc( ABC_NTK_AIG );
pNtkMiter = Abc_NtkAlloc( ABC_TYPE_STRASH, ABC_FUNC_AIG );
sprintf( Buffer, "%s_%s_miter", pNtk->pName, Abc_ObjName(Abc_NtkCo(pNtk, Out)) );
pNtkMiter->pName = util_strsav(Buffer);
......@@ -387,7 +387,7 @@ int Abc_NtkMiterIsConstant( Abc_Ntk_t * pMiter )
{
Abc_Obj_t * pNodePo, * pChild;
int i;
assert( Abc_NtkIsAig(pMiter) );
assert( Abc_NtkIsStrash(pMiter) );
Abc_NtkForEachPo( pMiter, pNodePo, i )
{
pChild = Abc_ObjChild0( Abc_NtkPo(pMiter,i) );
......@@ -478,9 +478,9 @@ Abc_Ntk_t * Abc_NtkFrames( Abc_Ntk_t * pNtk, int nFrames, int fInitial )
Abc_Obj_t * pLatch, * pLatchNew;
int i, Counter;
assert( nFrames > 0 );
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the new network
pNtkFrames = Abc_NtkAlloc( ABC_NTK_AIG );
pNtkFrames = Abc_NtkAlloc( ABC_TYPE_STRASH, ABC_FUNC_AIG );
sprintf( Buffer, "%s_%d_frames", pNtk->pName, nFrames );
pNtkFrames->pName = util_strsav(Buffer);
// create new latches (or their initial values) and remember them in the new latches
......
src/base/abc/abcNetlist.c
......@@ -47,10 +47,10 @@ Abc_Ntk_t * Abc_NtkNetlistToLogic( Abc_Ntk_t * pNtk )
int i, k;
assert( Abc_NtkIsNetlist(pNtk) );
// start the network
if ( Abc_NtkIsNetlistSop(pNtk) )
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_SOP );
if ( !Abc_NtkHasMapping(pNtk) )
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_SOP );
else
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_MAP );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_MAP );
// duplicate the nodes
Abc_NtkForEachNode( pNtk, pObj, i )
Abc_NtkDupObj(pNtkNew, pObj);
......@@ -84,8 +84,8 @@ Abc_Ntk_t * Abc_NtkNetlistToLogic( Abc_Ntk_t * pNtk )
Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew, * pNtkTemp;
assert( Abc_NtkIsLogic(pNtk) || Abc_NtkIsAig(pNtk) || Abc_NtkIsSeq(pNtk) );
if ( Abc_NtkIsAig(pNtk) )
assert( Abc_NtkIsLogic(pNtk) || Abc_NtkIsStrash(pNtk) || Abc_NtkIsSeq(pNtk) );
if ( Abc_NtkIsStrash(pNtk) )
{
pNtkTemp = Abc_NtkAigToLogicSop(pNtk);
pNtkNew = Abc_NtkLogicSopToNetlist( pNtkTemp );
......@@ -97,7 +97,7 @@ Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk )
pNtkNew = Abc_NtkLogicSopToNetlist( pNtkTemp );
Abc_NtkDelete( pNtkTemp );
}
else if ( Abc_NtkIsLogicBdd(pNtk) )
else if ( Abc_NtkIsBddLogic(pNtk) )
{
Abc_NtkBddToSop(pNtk);
pNtkNew = Abc_NtkLogicSopToNetlist( pNtk );
......@@ -122,7 +122,7 @@ Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk )
Abc_Ntk_t * Abc_NtkLogicToNetlistBench( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew, * pNtkTemp;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
pNtkTemp = Abc_NtkAigToLogicSopBench( pNtk );
pNtkNew = Abc_NtkLogicSopToNetlist( pNtkTemp );
Abc_NtkDelete( pNtkTemp );
......@@ -152,14 +152,17 @@ Abc_Ntk_t * Abc_NtkLogicSopToNetlist( Abc_Ntk_t * pNtk )
char * pNameCo;
int i, k;
assert( Abc_NtkIsLogicSop(pNtk) || Abc_NtkIsLogicMap(pNtk) );
assert( Abc_NtkIsLogic(pNtk) );
assert( Abc_NtkLogicHasSimpleCos(pNtk) );
if ( Abc_NtkIsBddLogic(pNtk) )
Abc_NtkBddToSop(pNtk);
// start the netlist by creating PI/PO/Latch objects
if ( Abc_NtkIsLogicSop(pNtk) )
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_NETLIST_SOP );
if ( Abc_NtkIsSopLogic(pNtk) )
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_NETLIST, ABC_FUNC_SOP );
else
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_NETLIST_MAP );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_NETLIST, ABC_FUNC_BDD );
// create the CI nets and remember them in the new CI nodes
Abc_NtkForEachCi( pNtk, pObj, i )
{
......@@ -233,9 +236,9 @@ Abc_Ntk_t * Abc_NtkAigToLogicSop( Abc_Ntk_t * pNtk )
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj, * pFanin, * pNodeNew;
int i, k;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_SOP );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_SOP );
// create the constant node
Abc_NtkDupConst1( pNtk, pNtkNew );
// duplicate the nodes and create node functions
......@@ -281,7 +284,7 @@ Abc_Ntk_t * Abc_NtkAigToLogicSop( Abc_Ntk_t * pNtk )
// duplicate the EXDC Ntk
if ( pNtk->pExdc )
{
if ( Abc_NtkIsAig(pNtk->pExdc) )
if ( Abc_NtkIsStrash(pNtk->pExdc) )
pNtkNew->pExdc = Abc_NtkAigToLogicSop( pNtk->pExdc );
else
pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
......@@ -309,11 +312,11 @@ Abc_Ntk_t * Abc_NtkAigToLogicSopBench( Abc_Ntk_t * pNtk )
Abc_Obj_t * pObj, * pFanin;
Vec_Ptr_t * vNodes;
int i, k;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
if ( Abc_NtkCountChoiceNodes(pNtk) )
printf( "Warning: Choice nodes are skipped.\n" );
// start the network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_SOP );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_SOP );
// create the constant node
Abc_NtkDupConst1( pNtk, pNtkNew );
// collect the nodes to be used (marks all nodes with current TravId)
......
src/base/abc/abcPrint.c
......@@ -57,7 +57,7 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
fprintf( pFile, " net = %5d", Abc_NtkNetNum(pNtk) );
fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) );
}
else if ( Abc_NtkIsAig(pNtk) )
else if ( Abc_NtkIsStrash(pNtk) )
{
fprintf( pFile, " and = %5d", Abc_NtkNodeNum(pNtk) );
if ( Num = Abc_NtkCountChoiceNodes(pNtk) )
......@@ -70,26 +70,26 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
else
fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) );
if ( Abc_NtkIsLogicSop(pNtk) || Abc_NtkIsNetlistSop(pNtk) )
if ( Abc_NtkHasSop(pNtk) )
{
fprintf( pFile, " cube = %5d", Abc_NtkGetCubeNum(pNtk) );
// fprintf( pFile, " lit(sop) = %5d", Abc_NtkGetLitNum(pNtk) );
if ( fFactored )
fprintf( pFile, " lit(fac) = %5d", Abc_NtkGetLitFactNum(pNtk) );
}
else if ( Abc_NtkIsLogicBdd(pNtk) )
else if ( Abc_NtkHasBdd(pNtk) )
fprintf( pFile, " bdd = %5d", Abc_NtkGetBddNodeNum(pNtk) );
else if ( Abc_NtkIsLogicMap(pNtk) || Abc_NtkIsNetlistMap(pNtk) )
else if ( Abc_NtkHasMapping(pNtk) )
{
fprintf( pFile, " area = %5.2f", Abc_NtkGetMappedArea(pNtk) );
fprintf( pFile, " delay = %5.2f", Abc_NtkDelayTrace(pNtk) );
}
else if ( !Abc_NtkIsAig(pNtk) && !Abc_NtkIsSeq(pNtk) )
else if ( !Abc_NtkHasAig(pNtk) )
{
assert( 0 );
}
if ( Abc_NtkIsAig(pNtk) )
if ( Abc_NtkIsStrash(pNtk) )
fprintf( pFile, " lev = %3d", Abc_AigGetLevelNum(pNtk) );
else if ( !Abc_NtkIsSeq(pNtk) )
fprintf( pFile, " lev = %3d", Abc_NtkGetLevelNum(pNtk) );
......@@ -180,7 +180,7 @@ void Abc_NtkPrintLatch( FILE * pFile, Abc_Ntk_t * pNtk )
continue;
}
// count the number of cases when the constant is equal to the initial value
if ( Abc_NtkIsAig(pNtk) )
if ( Abc_NtkIsStrash(pNtk) )
{
if ( Abc_LatchIsInit1(pLatch) == !Abc_ObjFaninC0(pLatch) )
Counter2++;
......@@ -314,7 +314,7 @@ void Abc_NtkPrintFactor( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i;
assert( Abc_NtkIsLogicSop(pNtk) );
assert( Abc_NtkIsSopLogic(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
Abc_NodePrintFactor( pFile, pNode );
}
......@@ -369,7 +369,7 @@ void Abc_NtkPrintLevel( FILE * pFile, Abc_Ntk_t * pNtk, int fProfile )
int i, Length;
// print the delay profile
if ( fProfile && Abc_NtkIsMapped(pNtk) )
if ( fProfile && Abc_NtkHasMapping(pNtk) )
{
int nIntervals = 12;
float DelayMax, DelayCur, DelayDelta;
......@@ -407,7 +407,7 @@ void Abc_NtkPrintLevel( FILE * pFile, Abc_Ntk_t * pNtk, int fProfile )
int LevelMax, * pLevelCounts;
int nOutsSum, nOutsTotal;
if ( !Abc_NtkIsAig(pNtk) )
if ( !Abc_NtkIsStrash(pNtk) )
Abc_NtkGetLevelNum(pNtk);
LevelMax = 0;
......@@ -430,7 +430,7 @@ void Abc_NtkPrintLevel( FILE * pFile, Abc_Ntk_t * pNtk, int fProfile )
free( pLevelCounts );
return;
}
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// find the longest name
Length = 0;
......
src/base/abc/abcReconv.c
......@@ -472,7 +472,7 @@ void Abc_NodeCollectTfoCands( Abc_Ntk_t * pNtk, Abc_Obj_t * pRoot,
Vec_Ptr_t * vVec;
Abc_Obj_t * pNode, * pFanout;
int i, k, v, LevelMin;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// assuming that the structure is clean
Vec_VecForEachLevel( vLevels, vVec, i )
......
src/base/abc/abcRefactor.c
......@@ -94,7 +94,7 @@ int Abc_NtkRefactor( Abc_Ntk_t * pNtk, int nNodeSizeMax, int nConeSizeMax, bool
int i, nNodes;
int clk, clkStart = clock();
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the managers
pManCut = Abc_NtkManCutStart( nNodeSizeMax, nConeSizeMax );
pManRef = Abc_NtkManRefStart( nNodeSizeMax, nConeSizeMax, fUseDcs, fVerbose );
......
src/base/abc/abcRefs.c
......@@ -167,16 +167,17 @@ int Abc_NodeRefDeref( Abc_Obj_t * pNode, bool fReference, bool fLabel, Vec_Ptr_t
***********************************************************************/
void Abc_NodeUpdate( Abc_Obj_t * pNode, Vec_Ptr_t * vFanins, Vec_Int_t * vForm, int nGain )
{
Abc_Ntk_t * pNtk = pNode->pNtk;
Abc_Obj_t * pNodeNew;
int nNodesNew, nNodesOld;
nNodesOld = Abc_NtkNodeNum(pNode->pNtk);
nNodesOld = Abc_NtkNodeNum(pNtk);
// create the new structure of nodes
assert( vForm->nSize == 1 || Vec_PtrSize(vFanins) < Vec_IntSize(vForm) );
pNodeNew = Abc_NodeStrashDec( pNode->pNtk->pManFunc, vFanins, vForm );
pNodeNew = Abc_NodeStrashDec( pNtk->pManFunc, vFanins, vForm );
// remove the old nodes
Abc_AigReplace( pNode->pNtk->pManFunc, pNode, pNodeNew );
Abc_AigReplace( pNtk->pManFunc, pNode, pNodeNew );
// compare the gains
nNodesNew = Abc_NtkNodeNum(pNode->pNtk);
nNodesNew = Abc_NtkNodeNum(pNtk);
assert( nGain <= nNodesOld - nNodesNew );
}
......
src/base/abc/abcRenode.c
......@@ -55,7 +55,7 @@ Abc_Ntk_t * Abc_NtkRenode( Abc_Ntk_t * pNtk, int nThresh, int nFaninMax, int fCn
int fCheck = 1;
Abc_Ntk_t * pNtkNew;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
assert( nThresh >= 0 );
assert( nFaninMax > 1 );
......@@ -74,7 +74,7 @@ Abc_Ntk_t * Abc_NtkRenode( Abc_Ntk_t * pNtk, int nThresh, int nFaninMax, int fCn
Abc_NtkRenodeSetBounds( pNtk, nThresh, nFaninMax );
// perform renoding for this boundary
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_BDD );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_BDD );
Abc_NtkRenodeInt( pNtk, pNtkNew );
Abc_NtkFinalize( pNtk, pNtkNew );
......
src/base/abc/abcRewrite.c
......@@ -55,7 +55,7 @@ int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUseZeros, int fVerbose )
int i, nNodes, nGain;
int clk, clkStart = clock();
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the rewriting manager
pManRwr = Rwr_ManStart( 0 );
if ( pManRwr == NULL )
......
src/base/abc/abcSat.c
......@@ -48,7 +48,7 @@ bool Abc_NtkMiterSat( Abc_Ntk_t * pNtk, int fVerbose )
lbool status;
int clk;
assert( Abc_NtkIsLogicBdd(pNtk) );
assert( Abc_NtkIsBddLogic(pNtk) );
assert( Abc_NtkLatchNum(pNtk) == 0 );
if ( Abc_NtkPoNum(pNtk) > 1 )
......@@ -110,7 +110,7 @@ solver * Abc_NtkMiterSatCreate( Abc_Ntk_t * pNtk )
char * pSop0, * pSop1;
int i;
assert( Abc_NtkIsLogicBdd(pNtk) );
assert( Abc_NtkIsBddLogic(pNtk) );
// start the data structures
pSat = solver_new();
......
src/base/abc/abcSeq.c
......@@ -67,9 +67,9 @@ Abc_Ntk_t * Abc_NtkAigToSeq( Abc_Ntk_t * pNtk )
Abc_Obj_t * pObj, * pConst, * pFanout, * pFaninNew, * pLatch;
int i, k, fChange, Counter;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// start the network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_SEQ );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_SEQ, ABC_FUNC_AIG );
pManNew = pNtkNew->pManFunc;
// set mapping of the constant nodes
......@@ -200,7 +200,7 @@ Abc_Ntk_t * Abc_NtkSeqToLogicSop( Abc_Ntk_t * pNtk )
int i, k, c;
assert( Abc_NtkIsSeq(pNtk) );
// start the network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC_SOP );
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_TYPE_LOGIC, ABC_FUNC_SOP );
// create the constant and reset nodes
Abc_NtkDupConst1( pNtk, pNtkNew );
Abc_NtkDupReset( pNtk, pNtkNew );
......
src/base/abc/abcShow.c
......@@ -60,7 +60,7 @@ void Abc_NodePrintBdd( Abc_Obj_t * pNode )
char * pProgGsViewName;
int RetValue;
assert( Abc_NtkIsLogicBdd(pNode->pNtk) );
assert( Abc_NtkIsBddLogic(pNode->pNtk) );
#ifdef WIN32
pProgDotName = "dot.exe";
......
src/base/abc/abcStrash.c
......@@ -56,16 +56,13 @@ Abc_Ntk_t * Abc_NtkStrash( Abc_Ntk_t * pNtk, bool fAllNodes )
int nNodes;
assert( !Abc_NtkIsNetlist(pNtk) );
if ( Abc_NtkIsLogicBdd(pNtk) )
{
// printf( "Converting node functions from BDD to SOP.\n" );
if ( Abc_NtkIsBddLogic(pNtk) )
Abc_NtkBddToSop(pNtk);
}
// print warning about choice nodes
if ( Abc_NtkCountChoiceNodes( pNtk ) )
printf( "Warning: The choice nodes in the initial AIG are removed by strashing.\n" );
// perform strashing
pNtkAig = Abc_NtkStartFrom( pNtk, ABC_NTK_AIG );
pNtkAig = Abc_NtkStartFrom( pNtk, ABC_TYPE_STRASH, ABC_FUNC_AIG );
Abc_NtkStrashPerform( pNtk, pNtkAig, fAllNodes );
Abc_NtkFinalize( pNtk, pNtkAig );
// print warning about self-feed latches
......@@ -106,13 +103,10 @@ int Abc_NtkAppend( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2 )
Abc_Obj_t * pObj;
int i;
// the first network should be an AIG
assert( Abc_NtkIsAig(pNtk1) );
assert( Abc_NtkIsLogic(pNtk2) || Abc_NtkIsAig(pNtk2) );
if ( Abc_NtkIsLogicBdd(pNtk2) )
{
// printf( "Converting node functions from BDD to SOP.\n" );
assert( Abc_NtkIsStrash(pNtk1) );
assert( Abc_NtkIsLogic(pNtk2) || Abc_NtkIsStrash(pNtk2) );
if ( Abc_NtkIsBddLogic(pNtk2) )
Abc_NtkBddToSop(pNtk2);
}
// check that the networks have the same PIs
// reorder PIs of pNtk2 according to pNtk1
if ( !Abc_NtkCompareSignals( pNtk1, pNtk2, 1 ) )
......@@ -192,7 +186,7 @@ Abc_Obj_t * Abc_NodeStrash( Abc_Aig_t * pMan, Abc_Obj_t * pNode )
assert( Abc_ObjIsNode(pNode) );
// consider the case when the graph is an AIG
if ( Abc_NtkIsAig(pNode->pNtk) )
if ( Abc_NtkIsStrash(pNode->pNtk) )
{
// Abc_Obj_t * pChild0, * pChild1;
// pChild0 = Abc_ObjFanin0(pNode);
......@@ -203,7 +197,7 @@ Abc_Obj_t * Abc_NodeStrash( Abc_Aig_t * pMan, Abc_Obj_t * pNode )
}
// get the SOP of the node
if ( Abc_NtkIsLogicMap(pNode->pNtk) )
if ( Abc_NtkHasMapping(pNode->pNtk) )
pSop = Mio_GateReadSop(pNode->pData);
else
pSop = pNode->pData;
......
src/base/abc/abcSweep.c
......@@ -58,7 +58,7 @@ bool Abc_NtkFraigSweep( Abc_Ntk_t * pNtk, int fUseInv, int fVerbose )
Fraig_Man_t * pMan;
stmm_table * tEquiv;
assert( !Abc_NtkIsAig(pNtk) );
assert( !Abc_NtkIsStrash(pNtk) );
// derive the AIG
pNtkAig = Abc_NtkStrash( pNtk, 0 );
......@@ -194,7 +194,7 @@ void Abc_NtkFraigTransform( Abc_Ntk_t * pNtk, stmm_table * tEquiv, int fUseInv,
// assign levels to the nodes of the network
Abc_NtkGetLevelNum( pNtk );
// merge nodes in the classes
if ( Abc_NtkIsLogicMap( pNtk ) )
if ( Abc_NtkHasMapping( pNtk ) )
{
Abc_NtkDelayTrace( pNtk );
stmm_foreach_item( tEquiv, gen, (char **)&pList, NULL )
......@@ -403,7 +403,7 @@ int Abc_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose )
}
Vec_PtrFree( vNodes );
// if it is an AIG, also mark the constant 1 node
if ( Abc_NtkIsAig(pNtk) )
if ( Abc_NtkIsStrash(pNtk) )
Abc_AigConst1(pNtk->pManFunc)->fMarkA = 1;
// remove the non-marked nodes
Counter = 0;
......
src/base/abc/abcTiming.c
......@@ -553,7 +553,7 @@ float Abc_NtkDelayTrace( Abc_Ntk_t * pNtk )
float tArrivalMax;
int i;
assert( Abc_NtkIsLogicMap(pNtk) );
assert( Abc_NtkIsMappedLogic(pNtk) );
Abc_NtkTimePrepare( pNtk );
vNodes = Abc_NtkDfs( pNtk, 1 );
......@@ -647,7 +647,7 @@ void Abc_NtkStartReverseLevels( Abc_Ntk_t * pNtk )
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanout;
int i, k, nLevelsCur;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
// remember the maximum number of direct levels
pNtk->LevelMax = Abc_AigGetLevelNum(pNtk);
// start the reverse levels
......@@ -701,7 +701,7 @@ void Abc_NtkStopReverseLevels( Abc_Ntk_t * pNtk )
void Abc_NodeSetReverseLevel( Abc_Obj_t * pObj, int LevelR )
{
Abc_Ntk_t * pNtk = pObj->pNtk;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
assert( pNtk->vLevelsR );
Vec_IntFillExtra( pNtk->vLevelsR, pObj->Id + 1, 0 );
Vec_IntWriteEntry( pNtk->vLevelsR, pObj->Id, LevelR );
......@@ -722,7 +722,7 @@ void Abc_NodeSetReverseLevel( Abc_Obj_t * pObj, int LevelR )
int Abc_NodeReadReverseLevel( Abc_Obj_t * pObj )
{
Abc_Ntk_t * pNtk = pObj->pNtk;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
assert( pNtk->vLevelsR );
Vec_IntFillExtra( pNtk->vLevelsR, pObj->Id + 1, 0 );
return Vec_IntEntry(pNtk->vLevelsR, pObj->Id);
......@@ -743,7 +743,7 @@ int Abc_NodeReadReverseLevel( Abc_Obj_t * pObj )
int Abc_NodeReadRequiredLevel( Abc_Obj_t * pObj )
{
Abc_Ntk_t * pNtk = pObj->pNtk;
assert( Abc_NtkIsAig(pNtk) );
assert( Abc_NtkIsStrash(pNtk) );
assert( pNtk->vLevelsR );
return pNtk->LevelMax + 1 - Vec_IntEntry(pNtk->vLevelsR, pObj->Id);
}
......
src/base/abc/abcUnreach.c
......@@ -282,7 +282,7 @@ Abc_Ntk_t * Abc_NtkConstructExdc( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * bUn
int i;
// start the new network
pNtkNew = Abc_NtkAlloc( ABC_NTK_LOGIC_BDD );
pNtkNew = Abc_NtkAlloc( ABC_TYPE_LOGIC, ABC_FUNC_BDD );
// create PIs corresponding to LOs
Abc_NtkForEachLatch( pNtk, pNode, i )
pNode->pCopy = Abc_NtkCreatePi(pNtkNew);
......@@ -308,13 +308,20 @@ Abc_Ntk_t * Abc_NtkConstructExdc( DdManager * dd, Abc_Ntk_t * pNtk, DdNode * bUn
Abc_NtkForEachCo( pNtk, pNode, i )
Abc_ObjAddFanin( Abc_NtkCreatePo(pNtkNew), pNodeNew );
// copy the CI/CO names
// store the PI names of the EXDC network
Abc_NtkForEachLatch( pNtk, pNode, i )
Abc_NtkLogicStoreName( Abc_NtkPi(pNtkNew,i), Abc_ObjName(pNode) );
// store the PO names of the EXDC network
Abc_NtkForEachPo( pNtk, pNode, i )
Abc_NtkLogicStoreName( Abc_NtkPo(pNtkNew,i), Abc_ObjName(pNode) );
Abc_NtkForEachLatch( pNtk, pNode, i )
Abc_NtkLogicStoreName( Abc_NtkCo(pNtkNew,Abc_NtkPoNum(pNtk) + i), Abc_ObjName(pNode) );
Abc_NtkLogicStoreName( Abc_NtkCo(pNtkNew,Abc_NtkPoNum(pNtk) + i), Abc_ObjNameSuffix(pNode, "_in") );
// make the network minimum base
Abc_NtkMinimumBase( pNtkNew );
// fix the problem with complemented and duplicated CO edges
Abc_NtkLogicMakeSimpleCos( pNtkNew, 0 );
// transform the network to the SOP representation
Abc_NtkBddToSop( pNtkNew );
......
src/base/abc/abcUtil.c
......@@ -72,7 +72,7 @@ int Abc_NtkGetCubeNum( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, nCubes = 0;
assert( Abc_NtkIsSop(pNtk) );
assert( Abc_NtkHasSop(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
assert( pNode->pData );
......@@ -96,7 +96,7 @@ int Abc_NtkGetLitNum( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, nLits = 0;
assert( Abc_NtkIsSop(pNtk) );
assert( Abc_NtkHasSop(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
assert( pNode->pData );
......@@ -121,16 +121,14 @@ int Abc_NtkGetLitFactNum( Abc_Ntk_t * pNtk )
Vec_Int_t * vFactor;
Abc_Obj_t * pNode;
int nNodes, i;
assert( Abc_NtkIsSop(pNtk) );
assert( Abc_NtkHasSop(pNtk) );
nNodes = 0;
// Ft_FactorStartMan();
Abc_NtkForEachNode( pNtk, pNode, i )
{
vFactor = Ft_Factor( pNode->pData );
nNodes += Ft_FactorGetNumNodes(vFactor);
Vec_IntFree( vFactor );
}
// Ft_FactorStopMan();
return nNodes;
}
......@@ -149,7 +147,7 @@ int Abc_NtkGetBddNodeNum( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, nNodes = 0;
assert( Abc_NtkIsLogicBdd(pNtk) );
assert( Abc_NtkIsBddLogic(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
assert( pNode->pData );
......@@ -175,7 +173,7 @@ int Abc_NtkGetClauseNum( Abc_Ntk_t * pNtk )
DdNode * bCover, * zCover, * bFunc;
DdManager * dd = pNtk->pManFunc;
int i, nClauses = 0;
assert( Abc_NtkIsLogicBdd(pNtk) );
assert( Abc_NtkIsBddLogic(pNtk) );
Abc_NtkForEachNode( pNtk, pNode, i )
{
assert( pNode->pData );
......@@ -214,7 +212,7 @@ double Abc_NtkGetMappedArea( Abc_Ntk_t * pNtk )
Abc_Obj_t * pNode;
double TotalArea;
int i;
assert( Abc_NtkIsLogicMap(pNtk) );
assert( Abc_NtkHasMapping(pNtk) );
TotalArea = 0.0;
Abc_NtkForEachNode( pNtk, pNode, i )
{
......@@ -367,9 +365,12 @@ int Abc_NtkLogicMakeSimpleCos( Abc_Ntk_t * pNtk, bool fDuplicate )
pDriver = Abc_ObjFanin0(pNode);
if ( Abc_ObjIsCi(pDriver) )
{
// skip the case when the CI deriver has the same name as CO
if ( strcmp(Abc_ObjName(pDriver), Abc_ObjName(pNode)) == 0 )
// skip the case when the driver is a different node with the same name
if ( pDriver != pNode && strcmp(Abc_ObjName(pDriver), Abc_ObjName(pNode)) == 0 )
{
assert( !Abc_ObjFaninC0(pNode) );
continue;
}
}
else
{
......@@ -385,9 +386,9 @@ int Abc_NtkLogicMakeSimpleCos( Abc_Ntk_t * pNtk, bool fDuplicate )
if ( Abc_ObjFaninC0(pNode) )
{
// change polarity of the duplicated driver
if ( Abc_NtkIsLogicSop(pNtk) )
if ( Abc_NtkHasSop(pNtk) )
Abc_SopComplement( pDriverNew->pData );
else if ( Abc_NtkIsLogicBdd(pNtk) )
else if ( Abc_NtkHasBdd(pNtk) )
pDriverNew->pData = Cudd_Not( pDriverNew->pData );
else
assert( 0 );
......@@ -643,7 +644,7 @@ int Abc_NtkCountChoiceNodes( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pNode;
int i, Counter;
if ( !Abc_NtkIsAig(pNtk) )
if ( !Abc_NtkIsStrash(pNtk) )
return 0;
Counter = 0;
Abc_NtkForEachNode( pNtk, pNode, i )
......
src/base/abc/module.make
SRC += src/base/abc/abc.c \
src/base/abc/abcAig.c \
src/base/abc/abcAttach.c \
src/base/abc/abcBalance.c \
src/base/abc/abcCheck.c \
src/base/abc/abcCollapse.c \
src/base/abc/abcCreate.c \
......@@ -19,9 +20,10 @@ SRC += src/base/abc/abc.c \
src/base/abc/abcNames.c \
src/base/abc/abcNetlist.c \
src/base/abc/abcPrint.c \
src/base/abc/abcReconv.c \
src/base/abc/abcRefactor.c \
src/base/abc/abcRefs.c \
src/base/abc/abcRenode.c \
src/base/abc/abcRefactor.c \
src/base/abc/abcRewrite.c \
src/base/abc/abcSat.c \
src/base/abc/abcSeq.c \
......
src/base/cmd/cmd.c
......@@ -1300,7 +1300,7 @@ int CmdCommandSis( Abc_Frame_t * pAbc, int argc, char **argv )
}
fclose( pFile );
if ( Abc_NtkIsLogicBdd(pNtk) )
if ( Abc_NtkIsBddLogic(pNtk) )
Abc_NtkBddToSop(pNtk);
// write out the current network
......@@ -1423,7 +1423,7 @@ int CmdCommandMvsis( Abc_Frame_t * pAbc, int argc, char **argv )
}
fclose( pFile );
if ( Abc_NtkIsLogicBdd(pNtk) )
if ( Abc_NtkIsBddLogic(pNtk) )
Abc_NtkBddToSop(pNtk);
// write out the current network
......
src/base/io/io.c
......@@ -604,7 +604,7 @@ int IoCommandWriteBlif( Abc_Frame_t * pAbc, int argc, char **argv )
FileName = argv[util_optind];
// check the network type
if ( !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsAig(pNtk) && !Abc_NtkIsSeq(pNtk) )
if ( !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) && !Abc_NtkIsSeq(pNtk) )
{
fprintf( pAbc->Out, "Currently can only write logic networks, AIGs, and seq AIGs.\n" );
return 0;
......@@ -670,7 +670,7 @@ int IoCommandWriteBench( Abc_Frame_t * pAbc, int argc, char **argv )
// get the input file name
FileName = argv[util_optind];
if ( !Abc_NtkIsAig(pNtk) )
if ( !Abc_NtkIsStrash(pNtk) )
{
fprintf( pAbc->Out, "The network should be an AIG.\n" );
return 0;
......
src/base/io/ioReadBlif.c
......@@ -292,12 +292,12 @@ Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p )
}
pModelName = vTokens->pArray[1];
// allocate the empty network
p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP );
p->pNtk = Abc_NtkAlloc( ABC_TYPE_NETLIST, ABC_FUNC_SOP );
p->pNtk->pName = util_strsav( pModelName );
p->pNtk->pSpec = util_strsav( p->pFileName );
}
else
p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP );
p->pNtk = Abc_NtkAlloc( ABC_TYPE_NETLIST, ABC_FUNC_SOP );
// read the inputs/outputs
pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p->pReader) );
......@@ -581,8 +581,8 @@ int Io_ReadBlifNetworkGate( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens )
// if this is the first line with gate, update the network type
if ( Abc_NtkNodeNum(p->pNtk) == 0 )
{
assert( p->pNtk->Type = ABC_NTK_NETLIST_SOP );
p->pNtk->Type = ABC_NTK_NETLIST_MAP;
assert( p->pNtk->ntkFunc == ABC_FUNC_SOP );
p->pNtk->ntkFunc = ABC_FUNC_MAP;
Extra_MmFlexStop( p->pNtk->pManFunc, 0 );
p->pNtk->pManFunc = pGenlib;
}
......
src/base/io/ioReadVerilog.c
......@@ -271,7 +271,7 @@ Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p )
pModelName = vTokens->pArray[1];
// allocate the empty network
pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP );
pNtk = Abc_NtkAlloc( ABC_TYPE_NETLIST, ABC_FUNC_SOP );
pNtk->pName = util_strsav( pModelName );
pNtk->pSpec = util_strsav( p->pFileName );
......
src/base/io/ioWriteBench.c
......@@ -46,7 +46,7 @@ int Io_WriteBench( Abc_Ntk_t * pNtk, char * pFileName )
{
Abc_Ntk_t * pExdc;
FILE * pFile;
assert( Abc_NtkIsNetlistSop(pNtk) );
assert( Abc_NtkIsSopNetlist(pNtk) );
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
{
......
src/base/io/ioWriteBlif.c
......@@ -320,7 +320,7 @@ void Io_NtkWriteLatch( FILE * pFile, Abc_Obj_t * pLatch )
***********************************************************************/
void Io_NtkWriteNode( FILE * pFile, Abc_Obj_t * pNode )
{
if ( Abc_NtkIsNetlistMap(pNode->pNtk) )
if ( Abc_NtkHasMapping(pNode->pNtk) )
{
// write the .gate line
fprintf( pFile, ".gate" );
......
src/base/io/ioWriteCnf.c
......@@ -44,9 +44,9 @@ static void Io_WriteCnfInt( FILE * pFile, Abc_Ntk_t * pNtk );
int Io_WriteCnf( Abc_Ntk_t * pNtk, char * pFileName )
{
solver * pSat;
if ( !Abc_NtkIsLogicBdd(pNtk) )
if ( !Abc_NtkIsBddLogic(pNtk) )
{
fprintf( stdout, "Io_WriteCnf(): Currently can process logic networks with BDDs.\n" );
fprintf( stdout, "Io_WriteCnf(): Currently can only process logic networks with BDDs.\n" );
return 0;
}
if ( Abc_NtkPoNum(pNtk) != 1 )
......
src/base/io/ioWritePla.c
......@@ -46,7 +46,7 @@ int Io_WritePla( Abc_Ntk_t * pNtk, char * pFileName )
Abc_Ntk_t * pExdc;
FILE * pFile;
assert( Abc_NtkIsNetlistSop(pNtk) );
assert( Abc_NtkIsSopNetlist(pNtk) );
assert( Abc_NtkGetLevelNum(pNtk) == 1 );
pFile = fopen( pFileName, "w" );
......
src/base/io/module.make
......@@ -2,6 +2,7 @@ SRC += src/base/io/io.c \
src/base/io/ioRead.c \
src/base/io/ioReadBench.c \
src/base/io/ioReadBlif.c \
src/base/io/ioReadEdif.c \
src/base/io/ioReadPla.c \
src/base/io/ioReadVerilog.c \
src/base/io/ioUtil.c \
......
src/base/main/mainFrame.c
......@@ -336,7 +336,7 @@ void Abc_FrameUnmapAllNetworks( Abc_Frame_t * p )
{
Abc_Ntk_t * pNtk;
for ( pNtk = p->pNtkCur; pNtk; pNtk = Abc_NtkBackup(pNtk) )
if ( Abc_NtkIsLogicMap(pNtk) )
if ( Abc_NtkHasMapping(pNtk) )
Abc_NtkUnmap( pNtk );
}
......
src/bdd/dsd/module.make
SRC += bdd\dsd\dsdApi.c \
bdd\dsd\dsdCheck.c \
bdd\dsd\dsdLocal.c \
bdd\dsd\dsdMan.c \
bdd\dsd\dsdProc.c \
bdd\dsd\dsdTree.c
SRC += src/bdd/dsd/dsdApi.c \
src/bdd/dsd/dsdCheck.c \
src/bdd/dsd/dsdLocal.c \
src/bdd/dsd/dsdMan.c \
src/bdd/dsd/dsdProc.c \
src/bdd/dsd/dsdTree.c
src/bdd/reo/module.make
SRC += bdd\reo\reoApi.c \
bdd\reo\reoCore.c \
bdd\reo\reoProfile.c \
bdd\reo\reoSift.c \
bdd\reo\reoSwap.c \
bdd\reo\reoTransfer.c \
bdd\reo\reoUnits.c
SRC += src/bdd/reo/reoApi.c \
src/bdd/reo/reoCore.c \
src/bdd/reo/reoProfile.c \
src/bdd/reo/reoSift.c \
src/bdd/reo/reoSwap.c \
src/bdd/reo/reoTransfer.c \
src/bdd/reo/reoUnits.c
src/map/mapper/mapperCore.c
......@@ -69,7 +69,7 @@ int Map_Mapping( Map_Man_t * p )
Map_MappingTruths( p );
p->timeTruth = clock() - clk;
//////////////////////////////////////////////////////////////////////
PRT( "Truths", clock() - clk );
//PRT( "Truths", clock() - clk );
//////////////////////////////////////////////////////////////////////
// compute the minimum-delay mapping
......
src/misc/extra/extraUtilMisc.c
......@@ -804,7 +804,7 @@ void Extra_Truth3VarN( unsigned ** puCanons, char *** puPhases, char ** ppCounte
*ppCounters = pCounters;
else
free( pCounters );
printf( "The number of 3N-classes = %d.\n", nClasses );
// printf( "The number of 3N-classes = %d.\n", nClasses );
}
/**Function*************************************************************
......@@ -870,7 +870,7 @@ void Extra_Truth4VarN( unsigned short ** puCanons, char *** puPhases, char ** pp
*ppCounters = pCounters;
else
free( pCounters );
printf( "The number of 4N-classes = %d.\n", nClasses );
// printf( "The number of 4N-classes = %d.\n", nClasses );
}
/**Function*************************************************************
......
src/opt/cut/cut.h
......@@ -70,7 +70,7 @@ static inline int Cut_CutReadLeaveNum( Cut_Cut_t * p ) { return p->nLea
static inline int * Cut_CutReadLeaves( Cut_Cut_t * p ) { return p->pLeaves; }
static inline void * Cut_CutReadData( Cut_Cut_t * p ) { return p->pData; }
static inline void * Cut_CutWriteData( Cut_Cut_t * p, void * pData ) { p->pData = pData; }
static inline void Cut_CutWriteData( Cut_Cut_t * p, void * pData ) { p->pData = pData; }
static inline void Cut_CutWriteTruth( Cut_Cut_t * p, unsigned * puTruth ) {
if ( p->nVarsMax == 4 ) { p->uTruth = *puTruth; return; }
p->pLeaves[p->nVarsMax + p->fSeq] = (int)puTruth[0];
......
src/opt/rwr/rwr.h
......@@ -137,7 +137,6 @@ extern void Rwr_ManWriteToArray( Rwr_Man_t * p );
extern void Rwr_ManLoadFromArray( Rwr_Man_t * p, int fVerbose );
extern void Rwr_ManWriteToFile( Rwr_Man_t * p, char * pFileName );
extern void Rwr_ManLoadFromFile( Rwr_Man_t * p, char * pFileName );
extern Vec_Int_t * Rwt_NtkFanoutCounters( Abc_Ntk_t * pNtk );
extern void Rwr_ListAddToTail( Rwr_Node_t ** ppList, Rwr_Node_t * pNode );
extern char * Rwr_ManGetPractical( Rwr_Man_t * p );
......
src/opt/rwr/rwrUtil.c
......@@ -25,8 +25,13 @@
////////////////////////////////////////////////////////////////////////
// precomputed data
#ifdef _WIN32
unsigned short s_RwrPracticalClasses[];
unsigned short s_RwtAigSubgraphs[];
#else
static unsigned short s_RwrPracticalClasses[];
static unsigned short s_RwtAigSubgraphs[];
#endif
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFITIONS ///
......@@ -221,30 +226,6 @@ void Rwr_ManLoadFromFile( Rwr_Man_t * p, char * pFileName )
/**Function*************************************************************
Synopsis [Creates the array of fanout counters.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Rwt_NtkFanoutCounters( Abc_Ntk_t * pNtk )
{
Vec_Int_t * vFanNums;
Abc_Obj_t * pObj;
int i;
vFanNums = Vec_IntAlloc( 0 );
Vec_IntFill( vFanNums, Abc_NtkObjNumMax(pNtk), -1 );
Abc_NtkForEachObj( pNtk, pObj, i )
if ( Abc_ObjIsNode( pObj ) )
Vec_IntWriteEntry( vFanNums, i, Abc_ObjFanoutNum(pObj) );
return vFanNums;
}
/**Function*************************************************************
Synopsis [Adds the node to the end of the list.]
Description []
......
src/sat/csat/csat_apis.c
......@@ -69,7 +69,7 @@ CSAT_Manager CSAT_InitManager()
CSAT_Manager_t * mng;
mng = ALLOC( CSAT_Manager_t, 1 );
memset( mng, 0, sizeof(CSAT_Manager_t) );
mng->pNtk = Abc_NtkAlloc( ABC_NTK_LOGIC_SOP );
mng->pNtk = Abc_NtkAlloc( ABC_TYPE_LOGIC, ABC_FUNC_SOP );
mng->pNtk->pName = util_strsav("csat_network");
mng->tName2Node = stmm_init_table(strcmp, stmm_strhash);
mng->vNodes = Vec_PtrAlloc( 100 );
......
src/sat/csat/module.make 0 → 100644
SRC += src/sat/csat/csat_apis.c
src/sop/ft/ftFactor.c
......@@ -319,10 +319,10 @@ Ft_Node_t * Ft_FactorTrivialTree_rec( Vec_Int_t * vForm, Ft_Node_t ** ppNodes, i
return ppNodes[0];
// split the nodes into two parts
// nNodes1 = nNodes/2;
// nNodes2 = nNodes - nNodes1;
nNodes2 = nNodes/2;
nNodes1 = nNodes - nNodes2;
nNodes1 = nNodes/2;
nNodes2 = nNodes - nNodes1;
// nNodes2 = nNodes/2;
// nNodes1 = nNodes - nNodes2;
// recursively construct the tree for the parts
pNode1 = Ft_FactorTrivialTree_rec( vForm, ppNodes, nNodes1, fAnd );
......
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