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Commit 581d8f0f by lvzhengyang
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add RTL2CDFG

parent 4119eb3d
Showing with 1988 additions and 0 deletions
README 0 → 100644
## e.g. RTL2CDFG
```
cd thirdparty/RTL2CDFG/v2cdfg
./cdfg_generator.sh --yosys /nfs_global/S/lvzhengyang/auto-assumption.misc/thirdparty/oss-cad-suite/bin/yosys ../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v
```
thirdparty/RTL2CDFG/README.md 0 → 100644
# CDFG generator
A Python program that reads Verilog code to generate a control data flow graph.
## configure
### Yosys Installation
Refer to the [yosy installation guide](https://github.com/YosysHQ/yosys?tab=readme-ov-file).
### Python Package
```
pip install -r requirements.txt
```
### Graphviz Download(Optional)
If you want to visualize the results,please download graphviz.
Refer to the [installation guide](https://www.graphviz.org/download/).
## Usage
### Single Run
#### First Way
First, please save the Verilog code in the ***./verilog_data*** directory.
This will generate CDFG for the specified files in the verilog_data directory.
```
cd ./v2cdfg && ./cdfg_generator.sh -nodivide *.v
```
The generated results are saved in ***./v2cdfg/cdfg***.
#### Second Way
This way you can generate cdfg for rtl code in any path.
```
cd ./v2cdfg && python3 cdfg_generator.py rtl_path.
```
The generated results are saved in ***./v2cdfg/cdfg***.
### Batch Run
This will generate CDFG for all Verilog files in the ***verilog_data*** directory.
```
cd ./v2cdfg && python3 gencdfg-multi-thread.py
```
The generated results are saved in ***./log***.
thirdparty/RTL2CDFG/log/log.txt 0 → 100644
test.v : Parser failed
test.v : Parser failed
test.v : Parser failed
test.v : Parser failed
test.v : Yosys failed
test.v : Yosys failed
test.v : Yosys failed
test.v : Yosys failed
test.v : Parser failed
test.v : Ast failed
../verilog_data/ALU.v : Parser failed
../../cases/eth_fifo/rtl/timescale.v : Parser failed
../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v : Ast failed
../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v: AssertionError: Exist if in design!
../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v: AssertionError: Exist if in design!
thirdparty/RTL2CDFG/requirements.txt 0 → 100644
anytree==2.12.1
matplotlib
networkx==2.8.4
thirdparty/RTL2CDFG/v2cdfg/cdfg/75_ast_clean_cdfg.dot 0 → 100644
digraph test {
"Input,1,fifo_rd" [style=filled, color=yellow];
"Input,1,rst_n" [style=filled, color=yellow];
"Output,1,fifo_EF" [style=filled, color=green];
"Output,8,fifo_rdata" [style=filled, color=green];
"Output,1,rfifo_full" [style=filled, color=green];
"Output,6,rfifo_used" [style=filled, color=green];
"Wire,32,_00_" [style=filled, color=orange];
"Wire,1,_01_" [style=filled, color=orange];
"Wire,32,_02_" [style=filled, color=orange];
"Wire,32,_03_" [style=filled, color=orange];
"Wire,32,_04_" [style=filled, color=orange];
"Reg,32,bytes_left" [style=filled, color=orange];
"Reg,1,fifo_rd_d" [style=filled, color=orange];
"Wire,1,new_rom" [style=filled, color=orange];
"Wire,32,num_bytes" [style=filled, color=orange];
"Wire,7,rfifo_entries" [style=filled, color=orange];
"LNot,Null,LNot_1" [style=filled, color=pink];
"Gt,Null,Gt_1" [style=filled, color=pink];
"Const,7,Constant_7'H40" [style=filled, color=grey];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Cond,Null,Cond_2" [style=filled, color=pink];
"Const,32,Constant_32'D0" [style=filled, color=grey];
"Cond,Null,Cond_3" [style=filled, color=pink];
"Const,1,Constant_1'H0" [style=filled, color=grey];
"Sub,Null,Sub_1" [style=filled, color=pink];
"Const,1,Constant_1'H1" [style=filled, color=grey];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_0" [style=filled, color=grey];
"Const,Null,Constant_5" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"PartSelect,Null,PartSelect_2" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Const,Null,Constant_31" [style=filled, color=grey];
"Cond,Null,Cond_4" [style=filled, color=pink];
"Const,32,Constant_32'D64" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_3" [style=filled, color=pink];
"Const,8,Constant_8'H0" [style=filled, color=grey];
"Concat,Null,Concat_3" [style=filled, color=pink];
"Concat,Null,Concat_4" [style=filled, color=pink];
"Input,1,fifo_rd" -> "Cond,Null,Cond_3" [label="2"];
"Input,1,rst_n" -> "Cond,Null,Cond_2" [label="1"];
"Input,1,rst_n" -> "Cond,Null,Cond_3" [label="1"];
"Output,1,rfifo_full" -> "Cond,Null,Cond_4" [label="1"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_1" [label="2"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_3" [label="2"];
"Wire,32,_00_" -> "Reg,32,bytes_left" [label="1"];
"Wire,1,_01_" -> "Reg,1,fifo_rd_d" [label="1"];
"Wire,32,_02_" -> "Cond,Null,Cond_2" [label="2"];
"Wire,32,_03_" -> "Cond,Null,Cond_1" [label="2"];
"Reg,32,bytes_left" -> "LNot,Null,LNot_1" [label="1"];
"Reg,32,bytes_left" -> "Gt,Null,Gt_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_1" [label="3"];
"Reg,32,bytes_left" -> "Sub,Null,Sub_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_4" [label="3"];
"Reg,1,fifo_rd_d" -> "Cond,Null,Cond_1" [label="1"];
"Wire,7,rfifo_entries" -> "PartSelect,Null,PartSelect_3" [label="1"];
"LNot,Null,LNot_1" -> "Output,1,fifo_EF" [label="1"];
"Gt,Null,Gt_1" -> "Output,1,rfifo_full" [label="1"];
"Const,7,Constant_7'H40" -> "Gt,Null,Gt_1" [label="2"];
"Cond,Null,Cond_1" -> "Wire,32,_02_" [label="1"];
"Cond,Null,Cond_2" -> "Wire,32,_00_" [label="1"];
"Const,32,Constant_32'D0" -> "Cond,Null,Cond_2" [label="3"];
"Const,32,Constant_32'D0" -> "Wire,32,num_bytes" [label="1"];
"Cond,Null,Cond_3" -> "Wire,1,_01_" [label="1"];
"Const,1,Constant_1'H0" -> "Cond,Null,Cond_3" [label="3"];
"Const,1,Constant_1'H0" -> "Wire,1,new_rom" [label="1"];
"Sub,Null,Sub_1" -> "Wire,32,_03_" [label="1"];
"Const,1,Constant_1'H1" -> "Sub,Null,Sub_1" [label="2"];
"PartSelect,Null,PartSelect_0" -> "Output,6,rfifo_used" [label="1"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"Const,Null,Constant_5" -> "PartSelect,Null,PartSelect_0" [label="2"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_3" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="3"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="3"];
"PartSelect,Null,PartSelect_2" -> "Concat,Null,Concat_4" [label="1"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_2" [label="3"];
"Const,Null,Constant_31" -> "PartSelect,Null,PartSelect_2" [label="2"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_2" [label="1"];
"Const,32,Constant_32'D64" -> "Cond,Null,Cond_4" [label="2"];
"Concat,Null,Concat_1" -> "Concat,Null,Concat_4" [label="2"];
"PartSelect,Null,PartSelect_3" -> "Concat,Null,Concat_1" [label="1"];
"Const,8,Constant_8'H0" -> "Output,8,fifo_rdata" [label="1"];
"Concat,Null,Concat_3" -> "Wire,7,rfifo_entries" [label="1"];
"Concat,Null,Concat_4" -> "Wire,32,_04_" [label="1"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/Led_ast_clean_cdfg.dot 0 → 100644
digraph test {
"Input,1,rst" [style=filled, color=yellow];
"Output,8,led" [style=filled, color=green];
"Wire,8,_0_" [style=filled, color=orange];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Const,8,Constant_8'H1" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"Const,Null,Constant_0" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Input,1,rst" -> "Cond,Null,Cond_1" [label="1"];
"Output,8,led" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Output,8,led" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Wire,8,_0_" -> "Output,8,led" [label="1"];
"Cond,Null,Cond_1" -> "Wire,8,_0_" [label="1"];
"Const,8,Constant_8'H1" -> "Cond,Null,Cond_1" [label="2"];
"Concat,Null,Concat_1" -> "Cond,Null,Cond_1" [label="3"];
"PartSelect,Null,PartSelect_0" -> "Concat,Null,Concat_1" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_0" [label="2"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_1" [label="2"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_1" [label="3"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/test_ast_clean_cdfg.dot 0 → 100644
digraph test {
"Input,1,fifo_rd" [style=filled, color=yellow];
"Input,1,rst_n" [style=filled, color=yellow];
"Output,1,fifo_EF" [style=filled, color=green];
"Output,8,fifo_rdata" [style=filled, color=green];
"Output,1,rfifo_full" [style=filled, color=green];
"Output,6,rfifo_used" [style=filled, color=green];
"Wire,32,_00_" [style=filled, color=orange];
"Wire,1,_01_" [style=filled, color=orange];
"Wire,32,_02_" [style=filled, color=orange];
"Wire,32,_03_" [style=filled, color=orange];
"Wire,32,_04_" [style=filled, color=orange];
"Reg,32,bytes_left" [style=filled, color=orange];
"Reg,1,fifo_rd_d" [style=filled, color=orange];
"Wire,1,new_rom" [style=filled, color=orange];
"Wire,32,num_bytes" [style=filled, color=orange];
"Wire,7,rfifo_entries" [style=filled, color=orange];
"LNot,Null,LNot_1" [style=filled, color=pink];
"Gt,Null,Gt_1" [style=filled, color=pink];
"Const,7,Constant_7'H40" [style=filled, color=grey];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Cond,Null,Cond_2" [style=filled, color=pink];
"Const,32,Constant_32'D0" [style=filled, color=grey];
"Cond,Null,Cond_3" [style=filled, color=pink];
"Const,1,Constant_1'H0" [style=filled, color=grey];
"Sub,Null,Sub_1" [style=filled, color=pink];
"Const,1,Constant_1'H1" [style=filled, color=grey];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_0" [style=filled, color=grey];
"Const,Null,Constant_5" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"PartSelect,Null,PartSelect_2" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Const,Null,Constant_31" [style=filled, color=grey];
"Cond,Null,Cond_4" [style=filled, color=pink];
"Const,32,Constant_32'D64" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_3" [style=filled, color=pink];
"Const,8,Constant_8'H0" [style=filled, color=grey];
"Concat,Null,Concat_3" [style=filled, color=pink];
"Concat,Null,Concat_4" [style=filled, color=pink];
"Input,1,fifo_rd" -> "Cond,Null,Cond_3" [label="2"];
"Input,1,rst_n" -> "Cond,Null,Cond_2" [label="1"];
"Input,1,rst_n" -> "Cond,Null,Cond_3" [label="1"];
"Output,1,rfifo_full" -> "Cond,Null,Cond_4" [label="1"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_1" [label="2"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_3" [label="2"];
"Wire,32,_00_" -> "Reg,32,bytes_left" [label="1"];
"Wire,1,_01_" -> "Reg,1,fifo_rd_d" [label="1"];
"Wire,32,_02_" -> "Cond,Null,Cond_2" [label="2"];
"Wire,32,_03_" -> "Cond,Null,Cond_1" [label="2"];
"Reg,32,bytes_left" -> "LNot,Null,LNot_1" [label="1"];
"Reg,32,bytes_left" -> "Gt,Null,Gt_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_1" [label="3"];
"Reg,32,bytes_left" -> "Sub,Null,Sub_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_4" [label="3"];
"Reg,1,fifo_rd_d" -> "Cond,Null,Cond_1" [label="1"];
"Wire,7,rfifo_entries" -> "PartSelect,Null,PartSelect_3" [label="1"];
"LNot,Null,LNot_1" -> "Output,1,fifo_EF" [label="1"];
"Gt,Null,Gt_1" -> "Output,1,rfifo_full" [label="1"];
"Const,7,Constant_7'H40" -> "Gt,Null,Gt_1" [label="2"];
"Cond,Null,Cond_1" -> "Wire,32,_02_" [label="1"];
"Cond,Null,Cond_2" -> "Wire,32,_00_" [label="1"];
"Const,32,Constant_32'D0" -> "Cond,Null,Cond_2" [label="3"];
"Const,32,Constant_32'D0" -> "Wire,32,num_bytes" [label="1"];
"Cond,Null,Cond_3" -> "Wire,1,_01_" [label="1"];
"Const,1,Constant_1'H0" -> "Cond,Null,Cond_3" [label="3"];
"Const,1,Constant_1'H0" -> "Wire,1,new_rom" [label="1"];
"Sub,Null,Sub_1" -> "Wire,32,_03_" [label="1"];
"Const,1,Constant_1'H1" -> "Sub,Null,Sub_1" [label="2"];
"PartSelect,Null,PartSelect_0" -> "Output,6,rfifo_used" [label="1"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"Const,Null,Constant_5" -> "PartSelect,Null,PartSelect_0" [label="2"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_3" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="3"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="3"];
"PartSelect,Null,PartSelect_2" -> "Concat,Null,Concat_4" [label="1"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_2" [label="3"];
"Const,Null,Constant_31" -> "PartSelect,Null,PartSelect_2" [label="2"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_2" [label="1"];
"Const,32,Constant_32'D64" -> "Cond,Null,Cond_4" [label="2"];
"Concat,Null,Concat_1" -> "Concat,Null,Concat_4" [label="2"];
"PartSelect,Null,PartSelect_3" -> "Concat,Null,Concat_1" [label="1"];
"Const,8,Constant_8'H0" -> "Output,8,fifo_rdata" [label="1"];
"Concat,Null,Concat_3" -> "Wire,7,rfifo_entries" [label="1"];
"Concat,Null,Concat_4" -> "Wire,32,_04_" [label="1"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/timescale_ast_clean_cdfg.dot 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/cdfg_generator.py 0 → 100644
import argparse
import os
import subprocess
import sys
from anytree.exporter import JsonExporter, UniqueDotExporter
from anytree.importer import JsonImporter
original_stdout = sys.stdout
sys.path.append(os.path.abspath('src'))
import tree
import ast2cdfg
import clean_ast
import ast_from_json
import ast_pre
LOG_FILE = "../log/log.txt"
def arguments():
parser = argparse.ArgumentParser(description="Example program for CLI arguments.")
parser.add_argument('filename', type=str, help="File name to process.", nargs='?')
return parser.parse_args()
def yosys(origin_filename):
name = os.path.splitext(os.path.basename(origin_filename))[0]
output_file = name + "_ast.v"
ast_clean_file = name + "_ast_clean.v"
output_directory = "./tmp/yosys_output_data"
out_path = os.path.join(output_directory, output_file)
# Open source and target files.
with open(origin_filename, 'r') as source_file, open("test.v", 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
# yosys_directory = "/home/wangyipeng/oss-cad-suite/bin/"
# os.system("yosys run_ast.ys".format(yosys_directory))
os.system("yosys run_ast.ys")
# Open source and target files.
with open("test_ast.v", 'r') as source_file, open(out_path, 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
ast_clean_directory = "./tmp/yosys_output_data_clean"
ast_clean_path = os.path.join(ast_clean_directory, ast_clean_file)
clean_ast.vlg_clean(out_path, ast_clean_path)
def parser(origin_filename, input_filename, output_filename):
print(input_filename)
print(output_filename)
# Use absolute paths to ensure correct file reading.
# input_file = os.path.abspath(f"./tmp/yosys_output_data_clean/{input_filename}")
# output_file = os.path.abspath(f"./tmp/s_exp/{output_filename}")
command = [
"../Stagira/stagira.exe",
"-toegg",
f"./tmp/yosys_output_data_clean/{input_filename}",
]
with open(f"./tmp/s_exp/{output_filename}", "w") as output_file:
try:
# Use subprocess.run with a 120-second timeout.
result = subprocess.run(command, timeout=120, check=True, stdout=output_file)
print("S-expression generated successfully.")
except subprocess.TimeoutExpired:
print("Command timed out: exceeded 120 seconds.")
with open(LOG_FILE, "a") as log_file:
log_file.write(f"{origin_filename} : Parser failed (timeout)\n")
except subprocess.CalledProcessError as e:
print(f"{origin_filename} : Parser failed (non-zero exit code {e.returncode})")
with open(LOG_FILE, "a") as log_file:
log_file.write(f"{origin_filename} : Parser failed\n")
def ast(origin_filename, input_filename, output_filename):
input_path = os.path.join("./tmp/s_exp", input_filename)
ast = tree.read_file(input_path, True)
with open("operatorlist.txt", "w+") as file:
operatorlist = list(set(tree.operatorlist))
for operator in operatorlist:
file.write(str(operator) + ',')
output_path = os.path.join("./tmp/ast", output_filename)
with open(output_path, 'w') as f:
sys.stdout = f
exporter = JsonExporter(indent=2, sort_keys=True)
print(exporter.export(ast))
sys.stdout = original_stdout
print("AST JSON file generated.")
dot_filename = f"{origin_filename}_ast_clean.dot"
dot_path = os.path.join("./tmp/ast", dot_filename)
importer = JsonImporter()
with open(output_path, 'r') as file:
root = importer.read(file)
# graphviz needs to be installed for the next line!
# UniqueDotExporter(root).to_picture(output_path2)
# UniqueDotExporter(root).to_dotfile(output_path4)
# subprocess.check_call(['dot', output_path4, '-T', 'png', '-o', output_path2])
UniqueDotExporter(root).to_dotfile(dot_path)
# subprocess.check_call(['dot', output_path4, '-T', 'svg', '-o', output_path2])
sys.stdout = original_stdout
print("AST dot file generated.")
def cdfg(origin_filename, input_filename):
input_path = os.path.join("./tmp/ast", input_filename)
out_path = os.path.join("./cdfg", origin_filename + "_cdfg.dot")
data = ast_from_json.read_json_file(input_path)
ast = ast_from_json.build_tree_from_json(data)
# Preprocess.
ast_pre.pre(ast)
# Extract CDFG; dfg is the extracted graph.
dfg_extractor = ast2cdfg.DFGExtractor()
dfg_extractor.visit(ast)
dfg_extractor.Preprocessing()
dfg_extractor.show_graph(filename=out_path)
def generator(filename):
# Extract file name and extension with os.path.splitext.
name_without_extension = os.path.splitext(os.path.basename(filename))[0]
# Generate new file names based on the extracted name.
filename_s = f"{name_without_extension}.s"
new_filename_v = f"{name_without_extension}_ast_clean.v"
new_filename_s = f"{name_without_extension}_ast_clean.s"
new_filename_j = f"{name_without_extension}_ast_clean.json"
# yosys
yosys(args.filename)
# Parser syntax analysis.
parser(name_without_extension, new_filename_v, new_filename_s)
# AST generation.
ast(name_without_extension, new_filename_s, new_filename_j)
# CDFG generation.
cdfg(name_without_extension, new_filename_j)
if __name__ == "__main__":
args = arguments()
generator(args.filename)
thirdparty/RTL2CDFG/v2cdfg/cdfg_generator.sh 0 → 100755
#!/usr/bin/env bash
# rm -rf ./data
# rm -rf ./ast_like_data/
# rm -rf test_ast.v
set -u
usage() {
cat <<EOF
Usage:
./cdfg_generator.sh [options] --rtl <file1.v> [file2.v ...]
./cdfg_generator.sh [options] <file1.v> [file2.v ...]
Options:
-divide Enable basic-block division in auto_run.py
-nodivide Disable division (default)
--top <module> Top module name for Yosys hierarchy
--yosys <path> Path to yosys binary (default: yosys in PATH)
-h, --help Show this help
Examples:
./cdfg_generator.sh --rtl ../verilog_data/ALU.v
./cdfg_generator.sh -divide --top top_mod --yosys /path/to/yosys \\
../verilog_data/a.v ../verilog_data/b.v
EOF
}
ifdivide=""
top_module=""
yosys_bin="yosys"
rtl_files=()
while [[ $# -gt 0 ]]; do
case "$1" in
-divide)
ifdivide="-divide"
shift
;;
-nodivide)
shift
;;
--top)
top_module="$2"
shift 2
;;
--yosys)
yosys_bin="$2"
shift 2
;;
--rtl)
shift
while [[ $# -gt 0 && "$1" != -* ]]; do
rtl_files+=("$1")
shift
done
;;
-h|--help)
usage
exit 0
;;
*)
rtl_files+=("$1")
shift
;;
esac
done
if [[ ${#rtl_files[@]} -eq 0 ]]; then
echo "[ERROR] No RTL files provided."
usage
exit 1
fi
if [[ "$yosys_bin" != "yosys" && ! -x "$yosys_bin" ]]; then
echo "[ERROR] yosys not found or not executable: $yosys_bin"
exit 1
fi
# Define log file path.
LOG_DIR=../log
LOG_FILE=$LOG_DIR/log.txt
# Ensure log directory exists.
mkdir -p $LOG_DIR
# Directories used by the pipeline.
mkdir -p ./origin_s_data ./tmp/yosys_output_data ./tmp/yosys_output_data_clean ./tmp/s_exp ./tmp/ast ./cdfg
# Use top module (if provided) as design name; otherwise derive from first RTL file.
if [[ -n "$top_module" ]]; then
design_name="$top_module"
else
base_name="$(basename "${rtl_files[0]}")"
design_name="${base_name%.*}"
fi
filename_s="${design_name}.s"
# .s file generated by parser.
new_filename_v="${design_name}_ast_clean.v"
new_filename_s="${design_name}_ast_clean.s"
new_filename_j="${design_name}_ast_clean.json"
# Generated AST files.
# # yiliu_ removable
# timeout 120s ~/py/CDFG/Stagira/stagira.exe -toegg ../yosys_data/$filename > ./origin_s_data/$filename_s
# Parse original RTL (first file) for reference.
origin_rtl="${rtl_files[0]}"
timeout 120s ../Stagira/stagira.exe -toegg "$origin_rtl" > ./origin_s_data/"$filename_s"
if [ $? -ne 0 ]; then
echo "$origin_rtl : Parser failed" >> $LOG_FILE
exit 1
fi
# python3 tree.py -i ./origin_s_data $filename_s -o ./data -r -j -e
# #yiliu
# Run Yosys with configurable RTL list and top module.
yosys_out="./tmp/yosys_output_data/${design_name}_ast.v"
yosys_script="./tmp/run_ast_${design_name}.ys"
{
echo "# Auto-generated by cdfg_generator.sh"
printf 'read_verilog -sv'
for f in "${rtl_files[@]}"; do
printf ' "%s"' "$f"
done
echo
if [[ -n "$top_module" ]]; then
echo "hierarchy -check -top $top_module"
else
echo "hierarchy -check"
fi
echo "proc"
echo "flatten"
echo "memory"
echo "write_verilog \"$yosys_out\""
} > "$yosys_script"
timeout 120s "$yosys_bin" -s "$yosys_script"
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : Yosys failed" >> $LOG_FILE
exit 1
fi
# Clean AST output.
clean_out="./tmp/yosys_output_data_clean/$new_filename_v"
timeout 120s python3 - <<PY
from src.clean_ast import vlg_clean
vlg_clean("$yosys_out", "$clean_out")
PY
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : AST clean failed" >> $LOG_FILE
exit 1
fi
# Parser generates .s file.
timeout 120s ../Stagira/stagira.exe -toegg "$clean_out" > ./tmp/s_exp/"$new_filename_s"
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : Parser failed" >> $LOG_FILE
exit 1
fi
# Convert .s to .json via tree.py.
timeout 120s python3 ./src/tree.py -i ./tmp/s_exp "$new_filename_s" -r -j -p -o ./tmp/ast
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : Ast failed" >> $LOG_FILE
exit 1
fi
if [ "$ifdivide" = "-divide" ]; then
timeout 120s python3 ./src/auto_run.py -d "$new_filename_j" > output.log 2>&1
else
timeout 120s python3 ./src/auto_run.py "$new_filename_j" > output.log 2>&1
fi
if [ $? -ne 0 ]; then
# Check for AssertionError.
if grep -q "AssertionError" output.log; then
# Write error details to fail.log.
grep "AssertionError" output.log | sed "s|^|${rtl_files[*]}: |">> $LOG_FILE
echo "AssertionError detected. See fail.log for details."
exit 1
else
echo "${rtl_files[*]} : cdfg generation failed" >> $LOG_FILE
exit 1
fi
fi
thirdparty/RTL2CDFG/v2cdfg/gencdfg-multi-thread.py 0 → 100755
import os, time, json
from multiprocessing import Pool
import concurrent.futures
#################
## global vars ##
#################
# verilog_dir = '/data/ruiyang/small_verilog_data' # dir to store the original verilog codes
verilog_dir = '../verilog_data'
success_data_dir = '../log/success' # dir to store success verilog and its generated cdfg
fail_data_dir = '../log/fail'
overtime_data_dir = '../log/overtime'
# for every verilog file in verilog_dir, process this verilog
# and generate a dir in data_dir to store the log
total_count = 0
success_count = 0
fail_count = 0
overtime_count = 0
yosys_timeout = 10
gencdfg_timeout = 10
# convert a verilog file to CDFG
# this will create a running dir to each verilog
# inorder to be applied concurrently
def process_file(filename):
global verilog_dir, data_dir, success_data_dir, fail_data_dir
global total_count, success_count, fail_count, overtime_count
global yosys_timeout, gencdfg_timeout
running_dir = ''
run_ast_verilog = ''
run_clean_ast_verilog = ''
output_data_dir = ''
yosys_success_flag = 1
cdfg_success_flag = 1
if filename.endswith(".v"):
verilog_path = os.path.join(verilog_dir, filename)
design_name = filename[:-2] # remove .v extension
# create running dir for a thread
running_dir = os.path.join("../", 'run-' + design_name)
log_dir = os.path.join(running_dir,"output.log")
os.system('cp -dr ../v2cdfg {}'.format(running_dir))
# run_verilog_path = os.path.join(running_dir,filename)
# os.system('cp {} {}'.format(verilog_path, run_verilog_path))
# yosys_success_flag = os.system('cd {} && timeout {}s yosys run_ast.ys >> yosys.log 2>&1'.format(running_dir, yosys_timeout))
# if yosys_success_flag==0:
exit_code = os.system('cd {} && ./cdfg_generator.sh -nodivide {}'.format(running_dir,filename))
# os.system('cd {} && python3 auto_yosys.py > /dev/null 2>&1'.format(running_dir))
# name = "test"
# cmd = "ast_clean"
# run_ast_verilog = os.path.join(running_dir, "test_ast.v")
# clean_ast_verilog = "../test_ast_clean.v"
# run_clean_ast_verilog = os.path.join(running_dir, "test_ast_clean.v")
# # Call the function to convert the design
# output_dir = "../example"
# # convert_one_design(clean_ast_verilog, name, cmd, output_dir)
# cdfg_success_flag = os.system(f'cd {running_dir} && cd vlg2ir && timeout {gencdfg_timeout}s python3 analyze.py {clean_ast_verilog} -N {name} -C {cmd} -O {output_dir} >> ../gencdfg.log 2>&1')
else:
return
# Generate a dir in data_dir to store the log
# if yosys_success_flag==0 and cdfg_success_flag==0:
# success_count += 1
# output_data_dir = os.path.join(success_data_dir, design_name)
# elif yosys_success_flag==31744 or cdfg_success_flag==31744:
# overtime_count += 1
# output_data_dir = os.path.join(overtime_data_dir, design_name)
# else:
# fail_count += 1
# output_data_dir = os.path.join(fail_data_dir, design_name)
if exit_code == 0:
success_count += 1
output_data_dir = os.path.join(success_data_dir, design_name)
else:
fail_count += 1
output_data_dir = os.path.join(fail_data_dir, design_name)
os.makedirs(output_data_dir, exist_ok=True)
os.system('cp {} {} > /dev/null 2>&1'.format(verilog_path, output_data_dir))
os.system('cp {} {} > /dev/null 2>&1'.format(log_dir, output_data_dir))
# os.system('cp {} {} > /dev/null 2>&1'.format(run_ast_verilog, output_data_dir))
# os.system('cp {} {} > /dev/null 2>&1'.format(run_clean_ast_verilog, output_data_dir))
os.system('cp -r {}/tmp/yosys_output_data_clean {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
os.system('cp -r {}/tmp/ast {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {}/cdfg && cp *.png {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {}/S_data && cp *.png {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {} && cp *.log {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {} && cp *.pkl {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
os.system('cp -r {}/cdfg {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
total_count += 1
print('{} finished. Process total {}, Success {}, Failed {}, Overtime {}'.format(filename, total_count, success_count, fail_count, overtime_count))
# delete the running dir
os.system('rm -rf {}'.format(running_dir))
if __name__ == '__main__':
# delete previous data
os.system('cd ../log && rm -rf *')
os.system('cd .. && rm -rf run-* && cd ./v2cdfg')
os.system('cd cdfg && rm -rf * && cd ..')
os.system('cd tmp/ast && rm -rf * && cd .. && cd ..')
os.system('cd tmp/s_exp && rm -rf * && cd .. && cd ..')
os.system('cd tmp/yosys_output_data && rm -rf * && cd .. && cd ..')
os.system('cd tmp/yosys_output_data_clean && rm -rf * && cd .. && cd ..')
if os.path.isfile("test.v"):
()# os.system('rm test.v && rm test_ast.v')
else:
print("no such file")
############
## Serial ##
############
# for filename in os.listdir(verilog_dir):
# process_file(filename)
##############
## Parallel ##
##############
thread_num = 128
read_num = 500 #4096
cnt = 0
cnt_total = 0
# setup thread pool
read_list = []
for filename in os.listdir(verilog_dir):
read_list.append(filename)
cnt += 1
cnt_total += 1
if cnt == read_num:
cnt = 0
with concurrent.futures.ThreadPoolExecutor(max_workers=thread_num) as executor:
futures = []
for f in read_list:
futures.append(executor.submit(process_file, f))
concurrent.futures.wait(futures, return_when=concurrent.futures.ALL_COMPLETED)
read_list = []
# if cnt_total==32:
# break
# Process remaining files.
if read_list:
with concurrent.futures.ThreadPoolExecutor(max_workers=thread_num) as executor:
futures = [executor.submit(process_file, f) for f in read_list]
concurrent.futures.wait(futures, return_when=concurrent.futures.ALL_COMPLETED)
thirdparty/RTL2CDFG/v2cdfg/operatorlist.txt 0 → 100755
,If,Nettype,TpVarTp,Lconc,RngC,Bin,Ufname,Casez,Dec,Sub,sharp,paras,TpEqAssigns,Svar,Funcall,Port,And,URor,Left,TpCaseLblList,TpCase,Int,localparam,Le,TpConcList,Pexp,Or,Ele,BitXor,macros,Wire,Conc,TpDim,TpFunHead,Not,body,Reg,Atom,LNot,Assign,NbkAssign,Always,Mul,BitOr,parameters,Clist,TpVarRange,TpParaList,FalseBlock,Idx,sigset,Lname,BitAnd,TpFunBody,CaseLbl,Output,Posedge,Function,TpSigDeclBody,Add,Cond,TpVarTplist,TpProg,TpAssign,TpCaseList,TpEqAssign,olists,SimpFunCall,Num,URand,TrueBlock,TpEvent,TpTask,TpModule,Hex,RtRange,Gt,Right,iolists,Ge,Input,BkAssign,TpExpList,ilists,Eq,Sym,Var,
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/origin_s_data/ALU.s 0 → 100644
出错的行号是：
6
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/origin_s_data/Led.s 0 → 100644
(TpProg (TpModule (TpTask led_chaser (sharp null) (paras (Input Nwire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Input Nwire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp)))) (Output Regtype (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists null) (iolists null) (olists null) (sigset null) (body (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (Block (body (If (Atom (Sym (Var rst))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var led)) (Atom (Num false 8 (Bin false 00000001))) NoDE)))))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var led)) (Conc (Clist (TpConcList (Ele (Atom (Sym (Idx led (TpExpList null) (RngC (Atom (Int 6)) (Atom (Int 0))))))) (Ele (Atom (Sym (Idx led (TpExpList (Atom (Int 7))) Rng0))))))) NoDE)))))))))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/origin_s_data/test.s 0 → 100644
(TpProg (TpModule (TpTask soc_design_JTAG_sim_scfifo_r (sharp null) (paras (Port (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp) (TpVarTp fifo_rd (TpDim null) NullExp) (TpVarTp rst_n (TpDim null) NullExp) (TpVarTp fifo_EF (TpDim null) NullExp) (TpVarTp fifo_rdata (TpDim null) NullExp) (TpVarTp rfifo_full (TpDim null) NullExp) (TpVarTp rfifo_used (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (iolists null) (olists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (sigset (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp bytes_left (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd_d (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp new_rom (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp num_bytes (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 6)) (Atom (Int 0))) (sharp (TpVarTp rfifo_entries (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp))))) (body (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (Block (body (If (Eq (Atom (Sym (Var rst_n))) (Atom (Int 0))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Atom (Num false 32 (Hex false 0))) NoDE)))) (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rd_d)) (Atom (Num false 1 (Bin false 0))) NoDE)))))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rd_d)) (Atom (Sym (Var fifo_rd))) NoDE)))) (If (Atom (Sym (Var fifo_rd_d))) (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Sub (Atom (Sym (Var bytes_left))) (Atom (Num false 1 (Bin false 1)))) NoDE)))) NoElse) (If (Atom (Sym (Var new_rom))) (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Atom (Sym (Var num_bytes))) NoDE)))) NoElse)))))))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_EF)) (Eq (Atom (Sym (Var bytes_left))) (Atom (Num false 32 (Bin false 0)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_full)) (Gt (Atom (Sym (Var bytes_left))) (Atom (Num false 7 (Hex false 40)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_entries)) (Cond (Atom (Sym (Var rfifo_full))) (Atom (Num false 7 (Hex false 40))) (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_used)) (Atom (Sym (Idx rfifo_entries (TpExpList null) (RngC (Atom (Int 5)) (Atom (Int 0)))))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var new_rom)) (Atom (Num false 1 (Bin false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var num_bytes)) (Atom (Num false 32 (Bin false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rdata)) (Atom (Num false 8 (Bin false 0))) NoDE))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/output.log 0 → 100644
32'D1
1'H1
1'H1
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H1
1'H1
1'H1
29'H0
32'D0
4'H1
4'H8
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
3'H0
3'H0
4'H0
32'D4294967295
32'D0
32'Hxxxxxxxx
32'Hxxxxxxxx
32'Hxxxxxxxx
3'Hx
3'Hx
32'D4294967295
32'D0
32'Hxxxxxxxx
32'D0
32'Hxxxxxxxx
3'Hx
2'H0
2'H0
3'H0
32'D1
Cond_2
Cond_3
Cond_4
Cond_5
Cond_6
Cond_7
Cond_8
Cond_9
Cond_10
Cond_11
Cond_12
Cond_13
Cond_14
Cond_15
Cond_16
Cond_17
Cond_274
Cond_276
Cond_278
Cond_280
Cond_283
Cond_284
Cond_285
Cond_286
Cond_287
Cond_288
Cond_289
Cond_291
Cond_292
----- Writting Graph Visialization File -----
Finish!
thirdparty/RTL2CDFG/v2cdfg/run_ast.ys 0 → 100755
# read -verific
read_verilog ./test.v
# elaborate design hierarchy
# hierarchy -check -top top
#big case
hierarchy -check
proc
flatten
memory
write_verilog ./test_ast.v
thirdparty/RTL2CDFG/v2cdfg/src/ast_from_json.py 0 → 100755
from anytree import NodeMixin,AnyNode,RenderTree
from anytree.importer import JsonImporter
import json
def read_json_file(file_path):
with open(file_path, 'r') as file:
data = json.load(file)
return data
def build_tree_from_json(data, level = 1, parent = None):
operator = data['name']
node = AnyNode(name = operator,level = level, parent = parent)
for child_data in data.get('children', []):
child_node = build_tree_from_json(child_data,level = level+1, parent = node)
return node
thirdparty/RTL2CDFG/v2cdfg/src/ast_pre.py 0 → 100755
from ast_from_json import *
import os
import sys
import subprocess
from anytree.exporter import JsonExporter, UniqueDotExporter
from anytree import AnyNode
# Unary operators.
operator1list = ["LNot", "Not", "URxor", "URand", "URor", "URnand", "URnor"]
# Binary operators.
operator2list = [
"Lt",
"Le",
"Gt",
"Ge",
"Add",
"Sub",
"Mul",
"Div",
"Mod",
"ShiftLeft",
"ShiftRight",
"AshiftLeft",
"AshiftRight",
"And",
"Or",
"Eq",
"Neq",
"Eeq",
"Neeq",
"BitAnd",
"BitOr",
"BitXor",
"BitNXor",
]
original_stdout = sys.stdout
operator_dict = {}
for operator in operator1list:
operator_dict[operator] = 0
for operator in operator2list:
operator_dict[operator] = 0
operator_dict["Lconc"] = 0
operator_dict["Cond"] = 0
operator_dict["Cond_If"] = 0
operator_dict["Idx"] = 0
operator_dict["Conc"] = 0
operator_dict["Casez"] = 0
operator_dict["PartAssign"] = 0
var_exp = {}
Idx_dict = {}
Idx_list = []
func_scope = False
def identical_Idx(node1, node2):
# print(node1.name + node2.name)
if node1.name.startswith("Idx") and node2.name.startswith("Idx"):
if len(node1.children) != len(node2.children):
return False
for index, subnode1 in enumerate(node1.children):
if index < len(node2.children):
# print(subnode1)
# print(node2.children[index])
if not identical_Idx(subnode1, node2.children[index]):
return False
else:
return False
else:
if node1.name != node2.name:
return False
else:
for index, subnode1 in enumerate(node1.children):
if node2.children[index]:
if not identical_Idx(subnode1, node2.children[index]):
return False
else:
return False
return True
def check_node_in_nodelist(node, node_dict):
for key, value in node_dict.items():
if identical_Idx(node, value):
return True, key
return False, None
def pre(ast):
if ast.name == "Case":
ast.name = "Casez"
# yanlw 26/8/2024
if ast.name == "TpConcList" and ast.parent.name.startswith("Lconc"):
num_ele = len(ast.children)
for tnode in ast.children:
if tnode.children[0].name == "Idx":
operator_dict["PartAssign"] += 1
tnode.children[0].name = "PartAssign_" + str(operator_dict["PartAssign"])
# print(f"partassign1: {tnode.children[0].name}{tnode.children[0]}")
num_ele -= 1
# Two cases: predecessor is Lname or predecessor is Lconc (num_partassign is non-zero).
if ast.name == "Idx" and ast.parent.name == "Lname":
operator_dict["PartAssign"] += 1
ast.name = "PartAssign_" + str(operator_dict["PartAssign"])
# print(f"partassign2: {ast.name}")
if ast.name == "If":
ast.name = "Cond_If"
if (
ast.name in operator2list
or ast.name in operator1list
or ast.name == "Cond"
or ast.name == "Idx"
or ast.name == "Conc"
or ast.name == "Casez"
or ast.name == "Lconc"
or ast.name == "Cond_If"
):
if ast.name == "Idx":
if Idx_dict and not ast.children[0].name == 'b':
result, index = check_node_in_nodelist(ast, Idx_dict)
if result:
# print("exit a identical Idx")
ast.name = Idx_dict[index].name
else:
operator_dict[ast.name] = operator_dict[ast.name] + 1
ast.name = ast.name + "_" + str(operator_dict[ast.name])
else:
operator_dict[ast.name] = operator_dict[ast.name] + 1
ast.name = ast.name + "_" + str(operator_dict[ast.name])
else:
operator_dict[ast.name] = operator_dict[ast.name] + 1
ast.name = ast.name + "_" + str(operator_dict[ast.name])
if ast.name.startswith("Idx"):
Idx_dict[ast.name] = ast
# if ast.name == "Lconc":
# ast.name = "Lname"
# tnode = AnyNode(name = "Conc", level = ast.level+1, parent = None)
# if ast.children:
# for subnode in ast.children:
# subnode.parent = tnode
# tnode.parent = ast
# extend var_exp
if ast.name == "Num":
node_name = "Constant_"
if ast.children[0]:
node_name = node_name + ast.children[0].name + "'"
if len(ast.children) > 1 and ast.children[1]:
if (
ast.children[1].name == "Hex"
or ast.children[1].name == "Bin"
or ast.children[1].name == "Dec"
or ast.children[1].name == "Oct"
):
node_name = node_name + ast.children[1].name[0]
if ast.children[1].children[0]:
node_name = node_name + ast.children[1].children[0].name
node_name = "Const," + ast.children[0].name + "," + node_name
var_exp[node_name] = node_name.split(',')[-1].replace("Constant_", "")
print(var_exp[node_name])
if ast.children:
for subnode in ast.children:
pre(subnode)
def pre_ast2json(ast, filename):
input_directory = "./data"
os.makedirs(input_directory, exist_ok=True)
input_path = os.path.join(input_directory, filename)
with open(input_path, 'w') as f:
sys.stdout = f
exporter = JsonExporter(indent=2, sort_keys=True)
print(exporter.export(ast))
sys.stdout = original_stdout
print("Preprocessed AST JSON conversion completed.")
def pre_ast2png(ast, filename):
name, ext = os.path.splitext(filename)
input_directory = "./data"
output_directory = "./ast_png"
os.makedirs(input_directory, exist_ok=True)
input_path = os.path.join(input_directory, name + ".json")
dot_output_path = os.path.join(output_directory, name + ".dot")
output_path = os.path.join(output_directory, name + ".svg")
# graphviz needs to be installed for the next line!
UniqueDotExporter(ast).to_dotfile(dot_output_path)
subprocess.check_call(['dot', dot_output_path, '-T', 'svg', '-o', output_path])
sys.stdout = original_stdout
print("Preprocessed AST PNG conversion completed.")
if __name__ == "__main__":
data = read_json_file("./data/75_ast_clean.json")
ast = build_tree_from_json(data)
pre(ast)
pre_ast2json(ast, "75_ast_clean.json")
pre_ast2png(ast, "75_ast_clean.json")
exit()
thirdparty/RTL2CDFG/v2cdfg/src/auto_run.py 0 → 100755
import argparse
import subprocess
import os
from ast2cdfg import *
def arguments():
parser = argparse.ArgumentParser(description="Example program for CLI arguments.")
parser.add_argument('filename', type=str, help="File name to process.", nargs='?')
parser.add_argument('-d', '--divide', action='store_true', help="Split basic blocks.")
return parser.parse_args()
if __name__ == "__main__":
args = arguments()
file_name = args.filename
name, ext = os.path.splitext(file_name)
# Read input file.
input_directory = "./tmp/ast"
output_directory = "./cdfg/"
# Create directory.
# output_directory = "../data/"+name
os.makedirs(output_directory, exist_ok=True)
input_path = os.path.join(input_directory, file_name)
out_path1 = os.path.join(output_directory, name + "_cdfg.dot")
out_path2 = os.path.join(output_directory, name + "_cdfg.png")
out_path3 = os.path.join(output_directory, name + "_basic_block_combined.dot")
data = read_json_file(input_path)
ast = build_tree_from_json(data)
# Preprocess: add suffix to identical keywords.
pre(ast)
# Extract CDFG; dfg is the extracted graph.
dfg_extractor = DFGExtractor()
dfg_extractor.visit(ast)
dfg_extractor.Preprocessing()
dfg_extractor.show_graph(filename=out_path1)
dfg = dfg_extractor.dfg
# print(dfg_extractor.resolve_var_exp())
# print(dfg_extractor.node_dict.keys())
# print(dfg.nodes)
# print(dfg.edges)
if args.divide:
Subgraphs = dfg_extractor.basic_block(outpath=output_directory)
dfg_extractor.show_basic_block_combine_graph(Subgraphs, out_path3)
# CDFG visualization.
# dot_path = "/mnt/c/ProgramFiles(x86)/Graphviz2.38/bin"
# os.system("dot -Tpng {} -o {}".format(out_path1,out_path2))
thirdparty/RTL2CDFG/v2cdfg/src/auto_yosys.py 0 → 100644
import argparse
import os
from clean_ast import *
def arguments():
parser = argparse.ArgumentParser(description="Example program for CLI arguments.")
parser.add_argument('filename', type=str, help="File name to process.", nargs='?')
return parser.parse_args()
if __name__ == "__main__":
args = arguments()
file_name = args.filename
print(args)
name, ext = os.path.splitext(file_name)
input_file = name + ".v"
output_file = name + "_ast.v"
ast_clean_file = name + "_ast_clean.v"
input_directory = "../verilog_data" # "./yosys_data_1000"
output_directory = "./tmp/yosys_output_data"
input_path = os.path.join(input_directory, input_file)
out_path = os.path.join(output_directory, output_file)
# Open source and target files.
with open(input_path, 'r') as source_file, open("test.v", 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
# yosys_directory = "/home/wangyipeng/oss-cad-suite/bin/"
# os.system("yosys run_ast.ys".format(yosys_directory))
os.system("yosys run_ast.ys")
# Open source and target files.
with open("test_ast.v", 'r') as source_file, open(out_path, 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
ast_clean_directory = "./tmp/yosys_output_data_clean"
ast_clean_path = os.path.join(ast_clean_directory, ast_clean_file)
vlg_clean(out_path, ast_clean_path)
# test
# vlg_clean("./test.v", ast_clean_path)
thirdparty/RTL2CDFG/v2cdfg/src/clean_ast.py 0 → 100755
import json, os, re, time
def vlg_clean(file, file_clean):
# file_tmp = file
# os.system("cp {0} ./{1}".format(file, file_tmp))
# os.remove(file)
with open(file, "r") as f:
lines = f.readlines()
with open(file_clean, "w+") as f_tmp:
for line in lines:
line = re.sub(r'\(\*(.*)\*\)', '', line)
if line.strip():
f_tmp.writelines(line)
# os.remove(file_tmp)
if __name__ == '__main__':
design_name = "test"
cmd = 'ast'
file_dir = f"./{design_name}_{cmd}.v"
file_clean_dir = f"./{design_name}_{cmd}_clean.v"
vlg_clean(file_dir, file_clean_dir)
thirdparty/RTL2CDFG/v2cdfg/src/structures.py 0 → 100644
class Subgraph:
def __init__(self, graph, name) -> None:
self.G = graph
self.name = name # Subgraph name.
self.successors = [] # Successor subgraphs.
self.predecessors = [] # Predecessor subgraphs.
def add_successor(self, successor_subgraph):
"""Add a successor subgraph."""
if successor_subgraph not in self.successors:
self.successors.append(successor_subgraph)
successor_subgraph.add_predecessor(self) # Keep predecessor list in sync.
def add_predecessor(self, predecessor_subgraph):
"""Add a predecessor subgraph."""
if predecessor_subgraph not in self.predecessors:
self.predecessors.append(predecessor_subgraph)
def __repr__(self):
return f"Subgraph(name={self.name}, successors={len(self.successors)}, predecessors={len(self.predecessors)})"
def __hash__(self):
"""Generate a unique hash from the subgraph name."""
return hash(self.name)
def __eq__(self, other):
"""Compare two subgraphs for equality."""
if isinstance(other, Subgraph):
return self.name == other.name
return False
thirdparty/RTL2CDFG/v2cdfg/test.v 0 → 100644
module soc_design_JTAG_sim_scfifo_r (
clk,
fifo_rd,
rst_n,
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
always @(posedge clk)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
endmodule
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/test_ast.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
(* src = "./test.v:1.1-49.10" *)
module soc_design_JTAG_sim_scfifo_r(clk, fifo_rd, rst_n, fifo_EF, fifo_rdata, rfifo_full, rfifo_used);
(* src = "./test.v:26.1-41.4" *)
wire [31:0] _00_;
(* src = "./test.v:26.1-41.4" *)
wire _01_;
wire [31:0] _02_;
(* src = "./test.v:37.25-37.42" *)
wire [31:0] _03_;
(* src = "./test.v:44.24-44.57" *)
(* unused_bits = "6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *)
wire [31:0] _04_;
(* src = "./test.v:17.18-17.28" *)
reg [31:0] bytes_left;
(* src = "./test.v:14.18-14.21" *)
input clk;
wire clk;
(* src = "./test.v:10.18-10.25" *)
output fifo_EF;
wire fifo_EF;
(* src = "./test.v:15.18-15.25" *)
input fifo_rd;
wire fifo_rd;
(* src = "./test.v:19.18-19.27" *)
reg fifo_rd_d;
(* src = "./test.v:11.18-11.28" *)
output [7:0] fifo_rdata;
wire [7:0] fifo_rdata;
(* src = "./test.v:21.18-21.25" *)
wire new_rom;
(* src = "./test.v:22.18-22.27" *)
wire [31:0] num_bytes;
(* src = "./test.v:23.18-23.31" *)
(* unused_bits = "6" *)
wire [6:0] rfifo_entries;
(* src = "./test.v:12.18-12.28" *)
output rfifo_full;
wire rfifo_full;
(* src = "./test.v:13.18-13.28" *)
output [5:0] rfifo_used;
wire [5:0] rfifo_used;
(* src = "./test.v:16.18-16.23" *)
input rst_n;
wire rst_n;
assign fifo_EF = ! (* src = "./test.v:42.18-42.37" *) bytes_left;
assign rfifo_full = bytes_left > (* src = "./test.v:43.21-43.39" *) 7'h40;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
bytes_left <= _00_;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
fifo_rd_d <= _01_;
assign _02_ = fifo_rd_d ? (* src = "./test.v:36.11-36.20|./test.v:36.7-37.43" *) _03_ : bytes_left;
assign _00_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) _02_ : 32'd0;
assign _01_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) fifo_rd : 1'h0;
assign _03_ = bytes_left - (* src = "./test.v:37.25-37.42" *) 1'h1;
assign { _04_[31:7], rfifo_entries[6], rfifo_used } = rfifo_full ? (* src = "./test.v:44.24-44.57" *) 32'd64 : bytes_left;
assign _04_[6:0] = { rfifo_entries[6], rfifo_used };
assign fifo_rdata = 8'h00;
assign new_rom = 1'h0;
assign num_bytes = 32'd0;
assign rfifo_entries[5:0] = rfifo_used;
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/Led_ast_clean.dot 0 → 100644
digraph tree {
"0x0" [label="TpProg"];
"0x1" [label="TpModule"];
"0x2" [label="TpTask led_chaser"];
"0x3" [label="paras"];
"0x4" [label="TpSigDeclBody"];
"0x5" [label="TpVarTplist"];
"0x6" [label="TpVarTp"];
"0x7" [label="clk"];
"0x8" [label="TpVarTp"];
"0x9" [label="rst"];
"0xa" [label="TpVarTp"];
"0xb" [label="led"];
"0xc" [label="ilists"];
"0xd" [label="TpSigDeclBody"];
"0xe" [label="TpVarTplist"];
"0xf" [label="TpVarTp"];
"0x10" [label="clk"];
"0x11" [label="TpSigDeclBody"];
"0x12" [label="TpVarTplist"];
"0x13" [label="TpVarTp"];
"0x14" [label="rst"];
"0x15" [label="olists"];
"0x16" [label="TpSigDeclBody"];
"0x17" [label="RngC"];
"0x18" [label="Int"];
"0x19" [label="7"];
"0x1a" [label="Int"];
"0x1b" [label="0"];
"0x1c" [label="TpVarTplist"];
"0x1d" [label="TpVarTp"];
"0x1e" [label="led"];
"0x1f" [label="sigset"];
"0x20" [label="Wire"];
"0x21" [label="TpSigDeclBody"];
"0x22" [label="RngC"];
"0x23" [label="Int"];
"0x24" [label="7"];
"0x25" [label="Int"];
"0x26" [label="0"];
"0x27" [label="TpVarTplist"];
"0x28" [label="TpVarTp"];
"0x29" [label="_0_"];
"0x2a" [label="Wire"];
"0x2b" [label="TpSigDeclBody"];
"0x2c" [label="TpVarTplist"];
"0x2d" [label="TpVarTp"];
"0x2e" [label="clk"];
"0x2f" [label="Reg"];
"0x30" [label="TpSigDeclBody"];
"0x31" [label="RngC"];
"0x32" [label="Int"];
"0x33" [label="7"];
"0x34" [label="Int"];
"0x35" [label="0"];
"0x36" [label="TpVarTplist"];
"0x37" [label="TpVarTp"];
"0x38" [label="led"];
"0x39" [label="Wire"];
"0x3a" [label="TpSigDeclBody"];
"0x3b" [label="TpVarTplist"];
"0x3c" [label="TpVarTp"];
"0x3d" [label="rst"];
"0x3e" [label="body"];
"0x3f" [label="Always"];
"0x40" [label="TpEvent"];
"0x41" [label="Posedge"];
"0x42" [label="TpVarRange"];
"0x43" [label="clk"];
"0x44" [label="body"];
"0x45" [label="NbkAssign"];
"0x46" [label="TpAssign"];
"0x47" [label="TpEqAssigns"];
"0x48" [label="TpEqAssign"];
"0x49" [label="Lname"];
"0x4a" [label="Var"];
"0x4b" [label="led"];
"0x4c" [label="Var"];
"0x4d" [label="_0_"];
"0x4e" [label="TpAssign"];
"0x4f" [label="TpEqAssigns"];
"0x50" [label="TpEqAssign"];
"0x51" [label="Lname"];
"0x52" [label="Var"];
"0x53" [label="_0_"];
"0x54" [label="Cond"];
"0x55" [label="Var"];
"0x56" [label="rst"];
"0x57" [label="TrueBlock"];
"0x58" [label="Num"];
"0x59" [label="8"];
"0x5a" [label="Hex"];
"0x5b" [label="1"];
"0x5c" [label="FalseBlock"];
"0x5d" [label="Conc"];
"0x5e" [label="TpConcList"];
"0x5f" [label="Ele"];
"0x60" [label="Idx"];
"0x61" [label="led"];
"0x62" [label="RngC"];
"0x63" [label="Int"];
"0x64" [label="6"];
"0x65" [label="Int"];
"0x66" [label="0"];
"0x67" [label="Ele"];
"0x68" [label="Idx"];
"0x69" [label="led"];
"0x6a" [label="TpExpList"];
"0x6b" [label="Int"];
"0x6c" [label="7"];
"0x0" -> "0x1";
"0x1" -> "0x2";
"0x2" -> "0x3";
"0x2" -> "0xc";
"0x2" -> "0x15";
"0x2" -> "0x1f";
"0x2" -> "0x3e";
"0x3" -> "0x4";
"0x4" -> "0x5";
"0x5" -> "0x6";
"0x5" -> "0x8";
"0x5" -> "0xa";
"0x6" -> "0x7";
"0x8" -> "0x9";
"0xa" -> "0xb";
"0xc" -> "0xd";
"0xc" -> "0x11";
"0xd" -> "0xe";
"0xe" -> "0xf";
"0xf" -> "0x10";
"0x11" -> "0x12";
"0x12" -> "0x13";
"0x13" -> "0x14";
"0x15" -> "0x16";
"0x16" -> "0x17";
"0x16" -> "0x1c";
"0x17" -> "0x18";
"0x17" -> "0x1a";
"0x18" -> "0x19";
"0x1a" -> "0x1b";
"0x1c" -> "0x1d";
"0x1d" -> "0x1e";
"0x1f" -> "0x20";
"0x1f" -> "0x2a";
"0x1f" -> "0x2f";
"0x1f" -> "0x39";
"0x20" -> "0x21";
"0x21" -> "0x22";
"0x21" -> "0x27";
"0x22" -> "0x23";
"0x22" -> "0x25";
"0x23" -> "0x24";
"0x25" -> "0x26";
"0x27" -> "0x28";
"0x28" -> "0x29";
"0x2a" -> "0x2b";
"0x2b" -> "0x2c";
"0x2c" -> "0x2d";
"0x2d" -> "0x2e";
"0x2f" -> "0x30";
"0x30" -> "0x31";
"0x30" -> "0x36";
"0x31" -> "0x32";
"0x31" -> "0x34";
"0x32" -> "0x33";
"0x34" -> "0x35";
"0x36" -> "0x37";
"0x37" -> "0x38";
"0x39" -> "0x3a";
"0x3a" -> "0x3b";
"0x3b" -> "0x3c";
"0x3c" -> "0x3d";
"0x3e" -> "0x3f";
"0x3e" -> "0x4e";
"0x3f" -> "0x40";
"0x3f" -> "0x44";
"0x40" -> "0x41";
"0x41" -> "0x42";
"0x42" -> "0x43";
"0x44" -> "0x45";
"0x45" -> "0x46";
"0x46" -> "0x47";
"0x47" -> "0x48";
"0x48" -> "0x49";
"0x48" -> "0x4c";
"0x49" -> "0x4a";
"0x4a" -> "0x4b";
"0x4c" -> "0x4d";
"0x4e" -> "0x4f";
"0x4f" -> "0x50";
"0x50" -> "0x51";
"0x50" -> "0x54";
"0x51" -> "0x52";
"0x52" -> "0x53";
"0x54" -> "0x55";
"0x54" -> "0x57";
"0x54" -> "0x5c";
"0x55" -> "0x56";
"0x57" -> "0x58";
"0x58" -> "0x59";
"0x58" -> "0x5a";
"0x5a" -> "0x5b";
"0x5c" -> "0x5d";
"0x5d" -> "0x5e";
"0x5e" -> "0x5f";
"0x5e" -> "0x67";
"0x5f" -> "0x60";
"0x60" -> "0x61";
"0x60" -> "0x62";
"0x62" -> "0x63";
"0x62" -> "0x65";
"0x63" -> "0x64";
"0x65" -> "0x66";
"0x67" -> "0x68";
"0x68" -> "0x69";
"0x68" -> "0x6a";
"0x6a" -> "0x6b";
"0x6b" -> "0x6c";
}
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/timescale_ast_clean.dot 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/timescale_ast_clean.json 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/tmp/run_ast_Led.ys 0 → 100644
# Auto-generated by cdfg_generator.sh
read_verilog -sv "../verilog_data/Led.v"
hierarchy -check
proc
flatten
memory
write_verilog "./tmp/yosys_output_data/Led_ast.v"
thirdparty/RTL2CDFG/v2cdfg/tmp/run_ast_timescale.ys 0 → 100644
# Auto-generated by cdfg_generator.sh
read_verilog -sv "../../../cases/eth_fifo/rtl/timescale.v" "../../../cases/eth_fifo/rtl/ethmac_defines.v" "../../../cases/eth_fifo/rtl/eth_fifo.v"
hierarchy -check
proc
flatten
memory
write_verilog "./tmp/yosys_output_data/timescale_ast.v"
thirdparty/RTL2CDFG/v2cdfg/tmp/s_exp/Led_ast_clean.s 0 → 100644
(TpProg (TpModule (TpTask led_chaser (sharp null) (paras (Port (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp) (TpVarTp rst (TpDim null) NullExp) (TpVarTp led (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp)))) (iolists null) (olists (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp)))) (sigset (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp _0_ (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp))))) (body (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var led)) (Atom (Sym (Var _0_))) NoDE)))))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _0_)) (Cond (Atom (Sym (Var rst))) (Atom (Num false 8 (Hex false 01))) (Conc (Clist (TpConcList (Ele (Atom (Sym (Idx led (TpExpList null) (RngC (Atom (Int 6)) (Atom (Int 0))))))) (Ele (Atom (Sym (Idx led (TpExpList (Atom (Int 7))) Rng0)))))))) NoDE))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/tmp/s_exp/test_ast_clean.s 0 → 100644
(TpProg (TpModule (TpTask soc_design_JTAG_sim_scfifo_r (sharp null) (paras (Port (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp) (TpVarTp fifo_rd (TpDim null) NullExp) (TpVarTp rst_n (TpDim null) NullExp) (TpVarTp fifo_EF (TpDim null) NullExp) (TpVarTp fifo_rdata (TpDim null) NullExp) (TpVarTp rfifo_full (TpDim null) NullExp) (TpVarTp rfifo_used (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (iolists null) (olists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (sigset (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _00_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp _01_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _02_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _03_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _04_ (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp bytes_left (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd_d (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp new_rom (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp num_bytes (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 6)) (Atom (Int 0))) (sharp (TpVarTp rfifo_entries (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp))))) (body (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_EF)) (LNot (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_full)) (Gt (Atom (Sym (Var bytes_left))) (Atom (Num false 7 (Hex false 40)))) NoDE)))) (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Atom (Sym (Var _00_))) NoDE)))))) (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rd_d)) (Atom (Sym (Var _01_))) NoDE)))))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _02_)) (Cond (Atom (Sym (Var fifo_rd_d))) (Atom (Sym (Var _03_))) (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _00_)) (Cond (Atom (Sym (Var rst_n))) (Atom (Sym (Var _02_))) (Atom (Num false 32 (Dec false 0)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _01_)) (Cond (Atom (Sym (Var rst_n))) (Atom (Sym (Var fifo_rd))) (Atom (Num false 1 (Hex false 0)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _03_)) (Sub (Atom (Sym (Var bytes_left))) (Atom (Num false 1 (Hex false 1)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lconc (Clist (TpConcList (Ele (Atom (Sym (Idx _04_ (TpExpList null) (RngC (Atom (Int 31)) (Atom (Int 7))))))) (Ele (Atom (Sym (Idx rfifo_entries (TpExpList (Atom (Int 6))) Rng0)))) (Ele (Atom (Sym (Var rfifo_used))))))) (Cond (Atom (Sym (Var rfifo_full))) (Atom (Num false 32 (Dec false 64))) (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Idx _04_ (TpExpList null) (RngC (Atom (Int 6)) (Atom (Int 0))))) (Conc (Clist (TpConcList (Ele (Atom (Sym (Idx rfifo_entries (TpExpList (Atom (Int 6))) Rng0)))) (Ele (Atom (Sym (Var rfifo_used))))))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rdata)) (Atom (Num false 8 (Hex false 00))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var new_rom)) (Atom (Num false 1 (Hex false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var num_bytes)) (Atom (Num false 32 (Dec false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Idx rfifo_entries (TpExpList null) (RngC (Atom (Int 5)) (Atom (Int 0))))) (Atom (Sym (Var rfifo_used))) NoDE))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/tmp/s_exp/timescale_ast_clean.s 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data/Led_ast.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
(* src = "../verilog_data/Led.v:1.1-15.10" *)
module led_chaser(clk, rst, led);
(* src = "../verilog_data/Led.v:7.1-13.4" *)
wire [7:0] _0_;
(* src = "../verilog_data/Led.v:2.16-2.19" *)
input clk;
wire clk;
(* src = "../verilog_data/Led.v:4.22-4.25" *)
output [7:0] led;
reg [7:0] led;
(* src = "../verilog_data/Led.v:3.16-3.19" *)
input rst;
wire rst;
(* src = "../verilog_data/Led.v:7.1-13.4" *)
always @(posedge clk)
led <= _0_;
assign _0_ = rst ? (* full_case = 32'd1 *) (* src = "../verilog_data/Led.v:8.9-8.12|../verilog_data/Led.v:8.5-12.8" *) 8'h01 : { led[6:0], led[7] };
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data/test_ast.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
(* src = "./test.v:1.1-49.10" *)
module soc_design_JTAG_sim_scfifo_r(clk, fifo_rd, rst_n, fifo_EF, fifo_rdata, rfifo_full, rfifo_used);
(* src = "./test.v:26.1-41.4" *)
wire [31:0] _00_;
(* src = "./test.v:26.1-41.4" *)
wire _01_;
wire [31:0] _02_;
(* src = "./test.v:37.25-37.42" *)
wire [31:0] _03_;
(* src = "./test.v:44.24-44.57" *)
(* unused_bits = "6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *)
wire [31:0] _04_;
(* src = "./test.v:17.18-17.28" *)
reg [31:0] bytes_left;
(* src = "./test.v:14.18-14.21" *)
input clk;
wire clk;
(* src = "./test.v:10.18-10.25" *)
output fifo_EF;
wire fifo_EF;
(* src = "./test.v:15.18-15.25" *)
input fifo_rd;
wire fifo_rd;
(* src = "./test.v:19.18-19.27" *)
reg fifo_rd_d;
(* src = "./test.v:11.18-11.28" *)
output [7:0] fifo_rdata;
wire [7:0] fifo_rdata;
(* src = "./test.v:21.18-21.25" *)
wire new_rom;
(* src = "./test.v:22.18-22.27" *)
wire [31:0] num_bytes;
(* src = "./test.v:23.18-23.31" *)
(* unused_bits = "6" *)
wire [6:0] rfifo_entries;
(* src = "./test.v:12.18-12.28" *)
output rfifo_full;
wire rfifo_full;
(* src = "./test.v:13.18-13.28" *)
output [5:0] rfifo_used;
wire [5:0] rfifo_used;
(* src = "./test.v:16.18-16.23" *)
input rst_n;
wire rst_n;
assign fifo_EF = ! (* src = "./test.v:42.18-42.37" *) bytes_left;
assign rfifo_full = bytes_left > (* src = "./test.v:43.21-43.39" *) 7'h40;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
bytes_left <= _00_;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
fifo_rd_d <= _01_;
assign _02_ = fifo_rd_d ? (* src = "./test.v:36.11-36.20|./test.v:36.7-37.43" *) _03_ : bytes_left;
assign _00_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) _02_ : 32'd0;
assign _01_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) fifo_rd : 1'h0;
assign _03_ = bytes_left - (* src = "./test.v:37.25-37.42" *) 1'h1;
assign { _04_[31:7], rfifo_entries[6], rfifo_used } = rfifo_full ? (* src = "./test.v:44.24-44.57" *) 32'd64 : bytes_left;
assign _04_[6:0] = { rfifo_entries[6], rfifo_used };
assign fifo_rdata = 8'h00;
assign new_rom = 1'h0;
assign num_bytes = 32'd0;
assign rfifo_entries[5:0] = rfifo_used;
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data_clean/Led_ast_clean.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
module led_chaser(clk, rst, led);
wire [7:0] _0_;
input clk;
wire clk;
output [7:0] led;
reg [7:0] led;
input rst;
wire rst;
always @(posedge clk)
led <= _0_;
assign _0_ = rst ? 8'h01 : { led[6:0], led[7] };
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data_clean/test_ast_clean.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
module soc_design_JTAG_sim_scfifo_r(clk, fifo_rd, rst_n, fifo_EF, fifo_rdata, rfifo_full, rfifo_used);
wire [31:0] _00_;
wire _01_;
wire [31:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
reg [31:0] bytes_left;
input clk;
wire clk;
output fifo_EF;
wire fifo_EF;
input fifo_rd;
wire fifo_rd;
reg fifo_rd_d;
output [7:0] fifo_rdata;
wire [7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [6:0] rfifo_entries;
output rfifo_full;
wire rfifo_full;
output [5:0] rfifo_used;
wire [5:0] rfifo_used;
input rst_n;
wire rst_n;
assign fifo_EF = ! bytes_left;
assign rfifo_full = bytes_left > 7'h40;
always @(posedge clk)
bytes_left <= _00_;
always @(posedge clk)
fifo_rd_d <= _01_;
assign _02_ = fifo_rd_d ? _03_ : bytes_left;
assign _00_ = rst_n ? _02_ : 32'd0;
assign _01_ = rst_n ? fifo_rd : 1'h0;
assign _03_ = bytes_left - 1'h1;
assign { _04_[31:7], rfifo_entries[6], rfifo_used } = rfifo_full ? 32'd64 : bytes_left;
assign _04_[6:0] = { rfifo_entries[6], rfifo_used };
assign fifo_rdata = 8'h00;
assign new_rom = 1'h0;
assign num_bytes = 32'd0;
assign rfifo_entries[5:0] = rfifo_used;
endmodule
thirdparty/RTL2CDFG/verilog_data/ALU.v 0 → 100755
module ALU (
input [31:0] A,
input [31:0] B,
input [1:0] ALUOp,
output reg [31:0] Result,
);
always @(*) begin
if (ALUOp == 2'b00)
Result <= A + B;
else if (ALUOp == 2'b01)
Result <= A - B;
else if (ALUOp == 2'b10)
Result <= A & B;
else
Result <= A % B;
end
endmodule
thirdparty/RTL2CDFG/verilog_data/Led.v 0 → 100755
module led_chaser (
input wire clk, // clock signal
input wire rst, // reset signal
output reg [7:0] led // 8-bit LED output
);
always @(posedge clk) begin
if (rst) begin
led <= 8'b00000001; // on reset, light the first LED
end else begin
led <= {led[6:0], led[7]}; // on each rising clock edge, shift LED to the right
end
end
endmodule
thirdparty/RTL2CDFG/verilog_data/comparator.v 0 → 100644
module comparator (
p,
a,
b,
clk,
);
parameter integer N = 8;
input [N-1:0] a, b;
input clk;
output p;
// assign q = (a<b)?v2cdfg/yosys_data1/comparator.v1'b0:1'b1;
always @(posedge clk) begin
if (a < b) begin
p = 1'b0;
end else begin
p = 1'b1;
end
end
endmodule
thirdparty/RTL2CDFG/verilog_data/fsm-3.v 0 → 100755
module three_state_fsm (
input wire clk, // clock signal
input wire rst, // reset signal
input wire in, // input signal
output reg [1:0] state // current state output
);
// state encoding
localparam STATE0 = 2'b00;
localparam STATE1 = 2'b01;
localparam STATE2 = 2'b10;
// state machine logic
always @(posedge clk) begin
if (rst) begin
state <= STATE0; // on reset, state machine returns to IDLE state
end else begin
// state transition logic
if (state == STATE0) begin
if (in)
state <= STATE1; // if input is high, transition from STATE0 to STATE1
end else if (state == STATE1) begin
if (in)
state <= STATE2; // if input is high, transition from STATE1 to STATE2
end else if (state == STATE2) begin
if (in)
state <= STATE0; // if input is high, transition from STATE2 to STATE0
end else begin
state <= STATE0;
end
end
end
endmodule
thirdparty/RTL2CDFG/verilog_data/full_adder_4.v 0 → 100644
// Top Level Verilog code for N-bit Ripple Carry Full Adder using Structural Modeling
module full_adder (
a,
b,
cin,
s,
cout
);
parameter integer N = 4; // N-bit adder
input [N-1:0] a, b; // N-bit inputs a and b
input cin; // input carry
output [N-1:0] s; // N-bit sum
output cout; // output final carry
wire [N:0] carry; // carry chain
genvar i; // generate variable
generate
assign carry[0] = cin; // initial carry equals cin
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
assign s[i] = (a[i] ^ b[i]) ^ carry[i]; // compute sum of each bit
assign carry[i+1] = (b[i] & carry[i]) | (a[i] & b[i]) | (a[i] & carry[i]); // compute carry
end
assign cout = carry[N]; // final carry output
endgenerate
endmodule
thirdparty/RTL2CDFG/verilog_data/test.v 0 → 100644
module soc_design_JTAG_sim_scfifo_r (
clk,
fifo_rd,
rst_n,
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
always @(posedge clk)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
endmodule
\ No newline at end of file
thirdparty/RTL2CDFG/yosys_data/test.v 0 → 100644
module soc_design_JTAG_sim_scfifo_r (
clk,
fifo_rd,
rst_n,
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
always @(posedge clk)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
endmodule
\ No newline at end of file
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