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Commit 581d8f0f by lvzhengyang
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add RTL2CDFG

parent 4119eb3d
Showing with 10430 additions and 0 deletions
README 0 → 100644
## e.g. RTL2CDFG
```
cd thirdparty/RTL2CDFG/v2cdfg
./cdfg_generator.sh --yosys /nfs_global/S/lvzhengyang/auto-assumption.misc/thirdparty/oss-cad-suite/bin/yosys ../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v
```
thirdparty/RTL2CDFG/README.md 0 → 100644
# CDFG generator
A Python program that reads Verilog code to generate a control data flow graph.
## configure
### Yosys Installation
Refer to the [yosy installation guide](https://github.com/YosysHQ/yosys?tab=readme-ov-file).
### Python Package
```
pip install -r requirements.txt
```
### Graphviz Download(Optional)
If you want to visualize the results,please download graphviz.
Refer to the [installation guide](https://www.graphviz.org/download/).
## Usage
### Single Run
#### First Way
First, please save the Verilog code in the ***./verilog_data*** directory.
This will generate CDFG for the specified files in the verilog_data directory.
```
cd ./v2cdfg && ./cdfg_generator.sh -nodivide *.v
```
The generated results are saved in ***./v2cdfg/cdfg***.
#### Second Way
This way you can generate cdfg for rtl code in any path.
```
cd ./v2cdfg && python3 cdfg_generator.py rtl_path.
```
The generated results are saved in ***./v2cdfg/cdfg***.
### Batch Run
This will generate CDFG for all Verilog files in the ***verilog_data*** directory.
```
cd ./v2cdfg && python3 gencdfg-multi-thread.py
```
The generated results are saved in ***./log***.
thirdparty/RTL2CDFG/log/log.txt 0 → 100644
test.v : Parser failed
test.v : Parser failed
test.v : Parser failed
test.v : Parser failed
test.v : Yosys failed
test.v : Yosys failed
test.v : Yosys failed
test.v : Yosys failed
test.v : Parser failed
test.v : Ast failed
../verilog_data/ALU.v : Parser failed
../../cases/eth_fifo/rtl/timescale.v : Parser failed
../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v : Ast failed
../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v: AssertionError: Exist if in design!
../../../cases/eth_fifo/rtl/timescale.v ../../../cases/eth_fifo/rtl/ethmac_defines.v ../../../cases/eth_fifo/rtl/eth_fifo.v: AssertionError: Exist if in design!
thirdparty/RTL2CDFG/requirements.txt 0 → 100644
anytree==2.12.1
matplotlib
networkx==2.8.4
thirdparty/RTL2CDFG/v2cdfg/cdfg/75_ast_clean_cdfg.dot 0 → 100644
digraph test {
"Input,1,fifo_rd" [style=filled, color=yellow];
"Input,1,rst_n" [style=filled, color=yellow];
"Output,1,fifo_EF" [style=filled, color=green];
"Output,8,fifo_rdata" [style=filled, color=green];
"Output,1,rfifo_full" [style=filled, color=green];
"Output,6,rfifo_used" [style=filled, color=green];
"Wire,32,_00_" [style=filled, color=orange];
"Wire,1,_01_" [style=filled, color=orange];
"Wire,32,_02_" [style=filled, color=orange];
"Wire,32,_03_" [style=filled, color=orange];
"Wire,32,_04_" [style=filled, color=orange];
"Reg,32,bytes_left" [style=filled, color=orange];
"Reg,1,fifo_rd_d" [style=filled, color=orange];
"Wire,1,new_rom" [style=filled, color=orange];
"Wire,32,num_bytes" [style=filled, color=orange];
"Wire,7,rfifo_entries" [style=filled, color=orange];
"LNot,Null,LNot_1" [style=filled, color=pink];
"Gt,Null,Gt_1" [style=filled, color=pink];
"Const,7,Constant_7'H40" [style=filled, color=grey];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Cond,Null,Cond_2" [style=filled, color=pink];
"Const,32,Constant_32'D0" [style=filled, color=grey];
"Cond,Null,Cond_3" [style=filled, color=pink];
"Const,1,Constant_1'H0" [style=filled, color=grey];
"Sub,Null,Sub_1" [style=filled, color=pink];
"Const,1,Constant_1'H1" [style=filled, color=grey];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_0" [style=filled, color=grey];
"Const,Null,Constant_5" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"PartSelect,Null,PartSelect_2" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Const,Null,Constant_31" [style=filled, color=grey];
"Cond,Null,Cond_4" [style=filled, color=pink];
"Const,32,Constant_32'D64" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_3" [style=filled, color=pink];
"Const,8,Constant_8'H0" [style=filled, color=grey];
"Concat,Null,Concat_3" [style=filled, color=pink];
"Concat,Null,Concat_4" [style=filled, color=pink];
"Input,1,fifo_rd" -> "Cond,Null,Cond_3" [label="2"];
"Input,1,rst_n" -> "Cond,Null,Cond_2" [label="1"];
"Input,1,rst_n" -> "Cond,Null,Cond_3" [label="1"];
"Output,1,rfifo_full" -> "Cond,Null,Cond_4" [label="1"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_1" [label="2"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_3" [label="2"];
"Wire,32,_00_" -> "Reg,32,bytes_left" [label="1"];
"Wire,1,_01_" -> "Reg,1,fifo_rd_d" [label="1"];
"Wire,32,_02_" -> "Cond,Null,Cond_2" [label="2"];
"Wire,32,_03_" -> "Cond,Null,Cond_1" [label="2"];
"Reg,32,bytes_left" -> "LNot,Null,LNot_1" [label="1"];
"Reg,32,bytes_left" -> "Gt,Null,Gt_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_1" [label="3"];
"Reg,32,bytes_left" -> "Sub,Null,Sub_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_4" [label="3"];
"Reg,1,fifo_rd_d" -> "Cond,Null,Cond_1" [label="1"];
"Wire,7,rfifo_entries" -> "PartSelect,Null,PartSelect_3" [label="1"];
"LNot,Null,LNot_1" -> "Output,1,fifo_EF" [label="1"];
"Gt,Null,Gt_1" -> "Output,1,rfifo_full" [label="1"];
"Const,7,Constant_7'H40" -> "Gt,Null,Gt_1" [label="2"];
"Cond,Null,Cond_1" -> "Wire,32,_02_" [label="1"];
"Cond,Null,Cond_2" -> "Wire,32,_00_" [label="1"];
"Const,32,Constant_32'D0" -> "Cond,Null,Cond_2" [label="3"];
"Const,32,Constant_32'D0" -> "Wire,32,num_bytes" [label="1"];
"Cond,Null,Cond_3" -> "Wire,1,_01_" [label="1"];
"Const,1,Constant_1'H0" -> "Cond,Null,Cond_3" [label="3"];
"Const,1,Constant_1'H0" -> "Wire,1,new_rom" [label="1"];
"Sub,Null,Sub_1" -> "Wire,32,_03_" [label="1"];
"Const,1,Constant_1'H1" -> "Sub,Null,Sub_1" [label="2"];
"PartSelect,Null,PartSelect_0" -> "Output,6,rfifo_used" [label="1"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"Const,Null,Constant_5" -> "PartSelect,Null,PartSelect_0" [label="2"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_3" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="3"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="3"];
"PartSelect,Null,PartSelect_2" -> "Concat,Null,Concat_4" [label="1"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_2" [label="3"];
"Const,Null,Constant_31" -> "PartSelect,Null,PartSelect_2" [label="2"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_2" [label="1"];
"Const,32,Constant_32'D64" -> "Cond,Null,Cond_4" [label="2"];
"Concat,Null,Concat_1" -> "Concat,Null,Concat_4" [label="2"];
"PartSelect,Null,PartSelect_3" -> "Concat,Null,Concat_1" [label="1"];
"Const,8,Constant_8'H0" -> "Output,8,fifo_rdata" [label="1"];
"Concat,Null,Concat_3" -> "Wire,7,rfifo_entries" [label="1"];
"Concat,Null,Concat_4" -> "Wire,32,_04_" [label="1"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/Led_ast_clean_cdfg.dot 0 → 100644
digraph test {
"Input,1,rst" [style=filled, color=yellow];
"Output,8,led" [style=filled, color=green];
"Wire,8,_0_" [style=filled, color=orange];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Const,8,Constant_8'H1" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"Const,Null,Constant_0" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Input,1,rst" -> "Cond,Null,Cond_1" [label="1"];
"Output,8,led" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Output,8,led" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Wire,8,_0_" -> "Output,8,led" [label="1"];
"Cond,Null,Cond_1" -> "Wire,8,_0_" [label="1"];
"Const,8,Constant_8'H1" -> "Cond,Null,Cond_1" [label="2"];
"Concat,Null,Concat_1" -> "Cond,Null,Cond_1" [label="3"];
"PartSelect,Null,PartSelect_0" -> "Concat,Null,Concat_1" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_0" [label="2"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_1" [label="2"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_1" [label="3"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/test_ast_clean_cdfg.dot 0 → 100644
digraph test {
"Input,1,fifo_rd" [style=filled, color=yellow];
"Input,1,rst_n" [style=filled, color=yellow];
"Output,1,fifo_EF" [style=filled, color=green];
"Output,8,fifo_rdata" [style=filled, color=green];
"Output,1,rfifo_full" [style=filled, color=green];
"Output,6,rfifo_used" [style=filled, color=green];
"Wire,32,_00_" [style=filled, color=orange];
"Wire,1,_01_" [style=filled, color=orange];
"Wire,32,_02_" [style=filled, color=orange];
"Wire,32,_03_" [style=filled, color=orange];
"Wire,32,_04_" [style=filled, color=orange];
"Reg,32,bytes_left" [style=filled, color=orange];
"Reg,1,fifo_rd_d" [style=filled, color=orange];
"Wire,1,new_rom" [style=filled, color=orange];
"Wire,32,num_bytes" [style=filled, color=orange];
"Wire,7,rfifo_entries" [style=filled, color=orange];
"LNot,Null,LNot_1" [style=filled, color=pink];
"Gt,Null,Gt_1" [style=filled, color=pink];
"Const,7,Constant_7'H40" [style=filled, color=grey];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Cond,Null,Cond_2" [style=filled, color=pink];
"Const,32,Constant_32'D0" [style=filled, color=grey];
"Cond,Null,Cond_3" [style=filled, color=pink];
"Const,1,Constant_1'H0" [style=filled, color=grey];
"Sub,Null,Sub_1" [style=filled, color=pink];
"Const,1,Constant_1'H1" [style=filled, color=grey];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_0" [style=filled, color=grey];
"Const,Null,Constant_5" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"PartSelect,Null,PartSelect_2" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Const,Null,Constant_31" [style=filled, color=grey];
"Cond,Null,Cond_4" [style=filled, color=pink];
"Const,32,Constant_32'D64" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_3" [style=filled, color=pink];
"Const,8,Constant_8'H0" [style=filled, color=grey];
"Concat,Null,Concat_3" [style=filled, color=pink];
"Concat,Null,Concat_4" [style=filled, color=pink];
"Input,1,fifo_rd" -> "Cond,Null,Cond_3" [label="2"];
"Input,1,rst_n" -> "Cond,Null,Cond_2" [label="1"];
"Input,1,rst_n" -> "Cond,Null,Cond_3" [label="1"];
"Output,1,rfifo_full" -> "Cond,Null,Cond_4" [label="1"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_1" [label="2"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_3" [label="2"];
"Wire,32,_00_" -> "Reg,32,bytes_left" [label="1"];
"Wire,1,_01_" -> "Reg,1,fifo_rd_d" [label="1"];
"Wire,32,_02_" -> "Cond,Null,Cond_2" [label="2"];
"Wire,32,_03_" -> "Cond,Null,Cond_1" [label="2"];
"Reg,32,bytes_left" -> "LNot,Null,LNot_1" [label="1"];
"Reg,32,bytes_left" -> "Gt,Null,Gt_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_1" [label="3"];
"Reg,32,bytes_left" -> "Sub,Null,Sub_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_4" [label="3"];
"Reg,1,fifo_rd_d" -> "Cond,Null,Cond_1" [label="1"];
"Wire,7,rfifo_entries" -> "PartSelect,Null,PartSelect_3" [label="1"];
"LNot,Null,LNot_1" -> "Output,1,fifo_EF" [label="1"];
"Gt,Null,Gt_1" -> "Output,1,rfifo_full" [label="1"];
"Const,7,Constant_7'H40" -> "Gt,Null,Gt_1" [label="2"];
"Cond,Null,Cond_1" -> "Wire,32,_02_" [label="1"];
"Cond,Null,Cond_2" -> "Wire,32,_00_" [label="1"];
"Const,32,Constant_32'D0" -> "Cond,Null,Cond_2" [label="3"];
"Const,32,Constant_32'D0" -> "Wire,32,num_bytes" [label="1"];
"Cond,Null,Cond_3" -> "Wire,1,_01_" [label="1"];
"Const,1,Constant_1'H0" -> "Cond,Null,Cond_3" [label="3"];
"Const,1,Constant_1'H0" -> "Wire,1,new_rom" [label="1"];
"Sub,Null,Sub_1" -> "Wire,32,_03_" [label="1"];
"Const,1,Constant_1'H1" -> "Sub,Null,Sub_1" [label="2"];
"PartSelect,Null,PartSelect_0" -> "Output,6,rfifo_used" [label="1"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"Const,Null,Constant_5" -> "PartSelect,Null,PartSelect_0" [label="2"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_3" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="3"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="3"];
"PartSelect,Null,PartSelect_2" -> "Concat,Null,Concat_4" [label="1"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_2" [label="3"];
"Const,Null,Constant_31" -> "PartSelect,Null,PartSelect_2" [label="2"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_2" [label="1"];
"Const,32,Constant_32'D64" -> "Cond,Null,Cond_4" [label="2"];
"Concat,Null,Concat_1" -> "Concat,Null,Concat_4" [label="2"];
"PartSelect,Null,PartSelect_3" -> "Concat,Null,Concat_1" [label="1"];
"Const,8,Constant_8'H0" -> "Output,8,fifo_rdata" [label="1"];
"Concat,Null,Concat_3" -> "Wire,7,rfifo_entries" [label="1"];
"Concat,Null,Concat_4" -> "Wire,32,_04_" [label="1"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/timescale_ast_clean_cdfg.dot 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/cdfg_generator.py 0 → 100644
import argparse
import os
import subprocess
import sys
from anytree.exporter import JsonExporter, UniqueDotExporter
from anytree.importer import JsonImporter
original_stdout = sys.stdout
sys.path.append(os.path.abspath('src'))
import tree
import ast2cdfg
import clean_ast
import ast_from_json
import ast_pre
LOG_FILE = "../log/log.txt"
def arguments():
parser = argparse.ArgumentParser(description="Example program for CLI arguments.")
parser.add_argument('filename', type=str, help="File name to process.", nargs='?')
return parser.parse_args()
def yosys(origin_filename):
name = os.path.splitext(os.path.basename(origin_filename))[0]
output_file = name + "_ast.v"
ast_clean_file = name + "_ast_clean.v"
output_directory = "./tmp/yosys_output_data"
out_path = os.path.join(output_directory, output_file)
# Open source and target files.
with open(origin_filename, 'r') as source_file, open("test.v", 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
# yosys_directory = "/home/wangyipeng/oss-cad-suite/bin/"
# os.system("yosys run_ast.ys".format(yosys_directory))
os.system("yosys run_ast.ys")
# Open source and target files.
with open("test_ast.v", 'r') as source_file, open(out_path, 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
ast_clean_directory = "./tmp/yosys_output_data_clean"
ast_clean_path = os.path.join(ast_clean_directory, ast_clean_file)
clean_ast.vlg_clean(out_path, ast_clean_path)
def parser(origin_filename, input_filename, output_filename):
print(input_filename)
print(output_filename)
# Use absolute paths to ensure correct file reading.
# input_file = os.path.abspath(f"./tmp/yosys_output_data_clean/{input_filename}")
# output_file = os.path.abspath(f"./tmp/s_exp/{output_filename}")
command = [
"../Stagira/stagira.exe",
"-toegg",
f"./tmp/yosys_output_data_clean/{input_filename}",
]
with open(f"./tmp/s_exp/{output_filename}", "w") as output_file:
try:
# Use subprocess.run with a 120-second timeout.
result = subprocess.run(command, timeout=120, check=True, stdout=output_file)
print("S-expression generated successfully.")
except subprocess.TimeoutExpired:
print("Command timed out: exceeded 120 seconds.")
with open(LOG_FILE, "a") as log_file:
log_file.write(f"{origin_filename} : Parser failed (timeout)\n")
except subprocess.CalledProcessError as e:
print(f"{origin_filename} : Parser failed (non-zero exit code {e.returncode})")
with open(LOG_FILE, "a") as log_file:
log_file.write(f"{origin_filename} : Parser failed\n")
def ast(origin_filename, input_filename, output_filename):
input_path = os.path.join("./tmp/s_exp", input_filename)
ast = tree.read_file(input_path, True)
with open("operatorlist.txt", "w+") as file:
operatorlist = list(set(tree.operatorlist))
for operator in operatorlist:
file.write(str(operator) + ',')
output_path = os.path.join("./tmp/ast", output_filename)
with open(output_path, 'w') as f:
sys.stdout = f
exporter = JsonExporter(indent=2, sort_keys=True)
print(exporter.export(ast))
sys.stdout = original_stdout
print("AST JSON file generated.")
dot_filename = f"{origin_filename}_ast_clean.dot"
dot_path = os.path.join("./tmp/ast", dot_filename)
importer = JsonImporter()
with open(output_path, 'r') as file:
root = importer.read(file)
# graphviz needs to be installed for the next line!
# UniqueDotExporter(root).to_picture(output_path2)
# UniqueDotExporter(root).to_dotfile(output_path4)
# subprocess.check_call(['dot', output_path4, '-T', 'png', '-o', output_path2])
UniqueDotExporter(root).to_dotfile(dot_path)
# subprocess.check_call(['dot', output_path4, '-T', 'svg', '-o', output_path2])
sys.stdout = original_stdout
print("AST dot file generated.")
def cdfg(origin_filename, input_filename):
input_path = os.path.join("./tmp/ast", input_filename)
out_path = os.path.join("./cdfg", origin_filename + "_cdfg.dot")
data = ast_from_json.read_json_file(input_path)
ast = ast_from_json.build_tree_from_json(data)
# Preprocess.
ast_pre.pre(ast)
# Extract CDFG; dfg is the extracted graph.
dfg_extractor = ast2cdfg.DFGExtractor()
dfg_extractor.visit(ast)
dfg_extractor.Preprocessing()
dfg_extractor.show_graph(filename=out_path)
def generator(filename):
# Extract file name and extension with os.path.splitext.
name_without_extension = os.path.splitext(os.path.basename(filename))[0]
# Generate new file names based on the extracted name.
filename_s = f"{name_without_extension}.s"
new_filename_v = f"{name_without_extension}_ast_clean.v"
new_filename_s = f"{name_without_extension}_ast_clean.s"
new_filename_j = f"{name_without_extension}_ast_clean.json"
# yosys
yosys(args.filename)
# Parser syntax analysis.
parser(name_without_extension, new_filename_v, new_filename_s)
# AST generation.
ast(name_without_extension, new_filename_s, new_filename_j)
# CDFG generation.
cdfg(name_without_extension, new_filename_j)
if __name__ == "__main__":
args = arguments()
generator(args.filename)
thirdparty/RTL2CDFG/v2cdfg/cdfg_generator.sh 0 → 100755
#!/usr/bin/env bash
# rm -rf ./data
# rm -rf ./ast_like_data/
# rm -rf test_ast.v
set -u
usage() {
cat <<EOF
Usage:
./cdfg_generator.sh [options] --rtl <file1.v> [file2.v ...]
./cdfg_generator.sh [options] <file1.v> [file2.v ...]
Options:
-divide Enable basic-block division in auto_run.py
-nodivide Disable division (default)
--top <module> Top module name for Yosys hierarchy
--yosys <path> Path to yosys binary (default: yosys in PATH)
-h, --help Show this help
Examples:
./cdfg_generator.sh --rtl ../verilog_data/ALU.v
./cdfg_generator.sh -divide --top top_mod --yosys /path/to/yosys \\
../verilog_data/a.v ../verilog_data/b.v
EOF
}
ifdivide=""
top_module=""
yosys_bin="yosys"
rtl_files=()
while [[ $# -gt 0 ]]; do
case "$1" in
-divide)
ifdivide="-divide"
shift
;;
-nodivide)
shift
;;
--top)
top_module="$2"
shift 2
;;
--yosys)
yosys_bin="$2"
shift 2
;;
--rtl)
shift
while [[ $# -gt 0 && "$1" != -* ]]; do
rtl_files+=("$1")
shift
done
;;
-h|--help)
usage
exit 0
;;
*)
rtl_files+=("$1")
shift
;;
esac
done
if [[ ${#rtl_files[@]} -eq 0 ]]; then
echo "[ERROR] No RTL files provided."
usage
exit 1
fi
if [[ "$yosys_bin" != "yosys" && ! -x "$yosys_bin" ]]; then
echo "[ERROR] yosys not found or not executable: $yosys_bin"
exit 1
fi
# Define log file path.
LOG_DIR=../log
LOG_FILE=$LOG_DIR/log.txt
# Ensure log directory exists.
mkdir -p $LOG_DIR
# Directories used by the pipeline.
mkdir -p ./origin_s_data ./tmp/yosys_output_data ./tmp/yosys_output_data_clean ./tmp/s_exp ./tmp/ast ./cdfg
# Use top module (if provided) as design name; otherwise derive from first RTL file.
if [[ -n "$top_module" ]]; then
design_name="$top_module"
else
base_name="$(basename "${rtl_files[0]}")"
design_name="${base_name%.*}"
fi
filename_s="${design_name}.s"
# .s file generated by parser.
new_filename_v="${design_name}_ast_clean.v"
new_filename_s="${design_name}_ast_clean.s"
new_filename_j="${design_name}_ast_clean.json"
# Generated AST files.
# # yiliu_ removable
# timeout 120s ~/py/CDFG/Stagira/stagira.exe -toegg ../yosys_data/$filename > ./origin_s_data/$filename_s
# Parse original RTL (first file) for reference.
origin_rtl="${rtl_files[0]}"
timeout 120s ../Stagira/stagira.exe -toegg "$origin_rtl" > ./origin_s_data/"$filename_s"
if [ $? -ne 0 ]; then
echo "$origin_rtl : Parser failed" >> $LOG_FILE
exit 1
fi
# python3 tree.py -i ./origin_s_data $filename_s -o ./data -r -j -e
# #yiliu
# Run Yosys with configurable RTL list and top module.
yosys_out="./tmp/yosys_output_data/${design_name}_ast.v"
yosys_script="./tmp/run_ast_${design_name}.ys"
{
echo "# Auto-generated by cdfg_generator.sh"
printf 'read_verilog -sv'
for f in "${rtl_files[@]}"; do
printf ' "%s"' "$f"
done
echo
if [[ -n "$top_module" ]]; then
echo "hierarchy -check -top $top_module"
else
echo "hierarchy -check"
fi
echo "proc"
echo "flatten"
echo "memory"
echo "write_verilog \"$yosys_out\""
} > "$yosys_script"
timeout 120s "$yosys_bin" -s "$yosys_script"
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : Yosys failed" >> $LOG_FILE
exit 1
fi
# Clean AST output.
clean_out="./tmp/yosys_output_data_clean/$new_filename_v"
timeout 120s python3 - <<PY
from src.clean_ast import vlg_clean
vlg_clean("$yosys_out", "$clean_out")
PY
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : AST clean failed" >> $LOG_FILE
exit 1
fi
# Parser generates .s file.
timeout 120s ../Stagira/stagira.exe -toegg "$clean_out" > ./tmp/s_exp/"$new_filename_s"
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : Parser failed" >> $LOG_FILE
exit 1
fi
# Convert .s to .json via tree.py.
timeout 120s python3 ./src/tree.py -i ./tmp/s_exp "$new_filename_s" -r -j -p -o ./tmp/ast
if [ $? -ne 0 ]; then
echo "${rtl_files[*]} : Ast failed" >> $LOG_FILE
exit 1
fi
if [ "$ifdivide" = "-divide" ]; then
timeout 120s python3 ./src/auto_run.py -d "$new_filename_j" > output.log 2>&1
else
timeout 120s python3 ./src/auto_run.py "$new_filename_j" > output.log 2>&1
fi
if [ $? -ne 0 ]; then
# Check for AssertionError.
if grep -q "AssertionError" output.log; then
# Write error details to fail.log.
grep "AssertionError" output.log | sed "s|^|${rtl_files[*]}: |">> $LOG_FILE
echo "AssertionError detected. See fail.log for details."
exit 1
else
echo "${rtl_files[*]} : cdfg generation failed" >> $LOG_FILE
exit 1
fi
fi
thirdparty/RTL2CDFG/v2cdfg/gencdfg-multi-thread.py 0 → 100755
import os, time, json
from multiprocessing import Pool
import concurrent.futures
#################
## global vars ##
#################
# verilog_dir = '/data/ruiyang/small_verilog_data' # dir to store the original verilog codes
verilog_dir = '../verilog_data'
success_data_dir = '../log/success' # dir to store success verilog and its generated cdfg
fail_data_dir = '../log/fail'
overtime_data_dir = '../log/overtime'
# for every verilog file in verilog_dir, process this verilog
# and generate a dir in data_dir to store the log
total_count = 0
success_count = 0
fail_count = 0
overtime_count = 0
yosys_timeout = 10
gencdfg_timeout = 10
# convert a verilog file to CDFG
# this will create a running dir to each verilog
# inorder to be applied concurrently
def process_file(filename):
global verilog_dir, data_dir, success_data_dir, fail_data_dir
global total_count, success_count, fail_count, overtime_count
global yosys_timeout, gencdfg_timeout
running_dir = ''
run_ast_verilog = ''
run_clean_ast_verilog = ''
output_data_dir = ''
yosys_success_flag = 1
cdfg_success_flag = 1
if filename.endswith(".v"):
verilog_path = os.path.join(verilog_dir, filename)
design_name = filename[:-2] # remove .v extension
# create running dir for a thread
running_dir = os.path.join("../", 'run-' + design_name)
log_dir = os.path.join(running_dir,"output.log")
os.system('cp -dr ../v2cdfg {}'.format(running_dir))
# run_verilog_path = os.path.join(running_dir,filename)
# os.system('cp {} {}'.format(verilog_path, run_verilog_path))
# yosys_success_flag = os.system('cd {} && timeout {}s yosys run_ast.ys >> yosys.log 2>&1'.format(running_dir, yosys_timeout))
# if yosys_success_flag==0:
exit_code = os.system('cd {} && ./cdfg_generator.sh -nodivide {}'.format(running_dir,filename))
# os.system('cd {} && python3 auto_yosys.py > /dev/null 2>&1'.format(running_dir))
# name = "test"
# cmd = "ast_clean"
# run_ast_verilog = os.path.join(running_dir, "test_ast.v")
# clean_ast_verilog = "../test_ast_clean.v"
# run_clean_ast_verilog = os.path.join(running_dir, "test_ast_clean.v")
# # Call the function to convert the design
# output_dir = "../example"
# # convert_one_design(clean_ast_verilog, name, cmd, output_dir)
# cdfg_success_flag = os.system(f'cd {running_dir} && cd vlg2ir && timeout {gencdfg_timeout}s python3 analyze.py {clean_ast_verilog} -N {name} -C {cmd} -O {output_dir} >> ../gencdfg.log 2>&1')
else:
return
# Generate a dir in data_dir to store the log
# if yosys_success_flag==0 and cdfg_success_flag==0:
# success_count += 1
# output_data_dir = os.path.join(success_data_dir, design_name)
# elif yosys_success_flag==31744 or cdfg_success_flag==31744:
# overtime_count += 1
# output_data_dir = os.path.join(overtime_data_dir, design_name)
# else:
# fail_count += 1
# output_data_dir = os.path.join(fail_data_dir, design_name)
if exit_code == 0:
success_count += 1
output_data_dir = os.path.join(success_data_dir, design_name)
else:
fail_count += 1
output_data_dir = os.path.join(fail_data_dir, design_name)
os.makedirs(output_data_dir, exist_ok=True)
os.system('cp {} {} > /dev/null 2>&1'.format(verilog_path, output_data_dir))
os.system('cp {} {} > /dev/null 2>&1'.format(log_dir, output_data_dir))
# os.system('cp {} {} > /dev/null 2>&1'.format(run_ast_verilog, output_data_dir))
# os.system('cp {} {} > /dev/null 2>&1'.format(run_clean_ast_verilog, output_data_dir))
os.system('cp -r {}/tmp/yosys_output_data_clean {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
os.system('cp -r {}/tmp/ast {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {}/cdfg && cp *.png {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {}/S_data && cp *.png {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {} && cp *.log {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
# os.system('cd {} && cp *.pkl {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
os.system('cp -r {}/cdfg {} > /dev/null 2>&1'.format(running_dir, output_data_dir))
total_count += 1
print('{} finished. Process total {}, Success {}, Failed {}, Overtime {}'.format(filename, total_count, success_count, fail_count, overtime_count))
# delete the running dir
os.system('rm -rf {}'.format(running_dir))
if __name__ == '__main__':
# delete previous data
os.system('cd ../log && rm -rf *')
os.system('cd .. && rm -rf run-* && cd ./v2cdfg')
os.system('cd cdfg && rm -rf * && cd ..')
os.system('cd tmp/ast && rm -rf * && cd .. && cd ..')
os.system('cd tmp/s_exp && rm -rf * && cd .. && cd ..')
os.system('cd tmp/yosys_output_data && rm -rf * && cd .. && cd ..')
os.system('cd tmp/yosys_output_data_clean && rm -rf * && cd .. && cd ..')
if os.path.isfile("test.v"):
()# os.system('rm test.v && rm test_ast.v')
else:
print("no such file")
############
## Serial ##
############
# for filename in os.listdir(verilog_dir):
# process_file(filename)
##############
## Parallel ##
##############
thread_num = 128
read_num = 500 #4096
cnt = 0
cnt_total = 0
# setup thread pool
read_list = []
for filename in os.listdir(verilog_dir):
read_list.append(filename)
cnt += 1
cnt_total += 1
if cnt == read_num:
cnt = 0
with concurrent.futures.ThreadPoolExecutor(max_workers=thread_num) as executor:
futures = []
for f in read_list:
futures.append(executor.submit(process_file, f))
concurrent.futures.wait(futures, return_when=concurrent.futures.ALL_COMPLETED)
read_list = []
# if cnt_total==32:
# break
# Process remaining files.
if read_list:
with concurrent.futures.ThreadPoolExecutor(max_workers=thread_num) as executor:
futures = [executor.submit(process_file, f) for f in read_list]
concurrent.futures.wait(futures, return_when=concurrent.futures.ALL_COMPLETED)
thirdparty/RTL2CDFG/v2cdfg/operatorlist.txt 0 → 100755
,If,Nettype,TpVarTp,Lconc,RngC,Bin,Ufname,Casez,Dec,Sub,sharp,paras,TpEqAssigns,Svar,Funcall,Port,And,URor,Left,TpCaseLblList,TpCase,Int,localparam,Le,TpConcList,Pexp,Or,Ele,BitXor,macros,Wire,Conc,TpDim,TpFunHead,Not,body,Reg,Atom,LNot,Assign,NbkAssign,Always,Mul,BitOr,parameters,Clist,TpVarRange,TpParaList,FalseBlock,Idx,sigset,Lname,BitAnd,TpFunBody,CaseLbl,Output,Posedge,Function,TpSigDeclBody,Add,Cond,TpVarTplist,TpProg,TpAssign,TpCaseList,TpEqAssign,olists,SimpFunCall,Num,URand,TrueBlock,TpEvent,TpTask,TpModule,Hex,RtRange,Gt,Right,iolists,Ge,Input,BkAssign,TpExpList,ilists,Eq,Sym,Var,
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/origin_s_data/ALU.s 0 → 100644
出错的行号是：
6
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/origin_s_data/Led.s 0 → 100644
(TpProg (TpModule (TpTask led_chaser (sharp null) (paras (Input Nwire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Input Nwire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp)))) (Output Regtype (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists null) (iolists null) (olists null) (sigset null) (body (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (Block (body (If (Atom (Sym (Var rst))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var led)) (Atom (Num false 8 (Bin false 00000001))) NoDE)))))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var led)) (Conc (Clist (TpConcList (Ele (Atom (Sym (Idx led (TpExpList null) (RngC (Atom (Int 6)) (Atom (Int 0))))))) (Ele (Atom (Sym (Idx led (TpExpList (Atom (Int 7))) Rng0))))))) NoDE)))))))))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/origin_s_data/test.s 0 → 100644
(TpProg (TpModule (TpTask soc_design_JTAG_sim_scfifo_r (sharp null) (paras (Port (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp) (TpVarTp fifo_rd (TpDim null) NullExp) (TpVarTp rst_n (TpDim null) NullExp) (TpVarTp fifo_EF (TpDim null) NullExp) (TpVarTp fifo_rdata (TpDim null) NullExp) (TpVarTp rfifo_full (TpDim null) NullExp) (TpVarTp rfifo_used (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (iolists null) (olists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (sigset (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp bytes_left (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd_d (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp new_rom (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp num_bytes (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 6)) (Atom (Int 0))) (sharp (TpVarTp rfifo_entries (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp))))) (body (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (Block (body (If (Eq (Atom (Sym (Var rst_n))) (Atom (Int 0))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Atom (Num false 32 (Hex false 0))) NoDE)))) (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rd_d)) (Atom (Num false 1 (Bin false 0))) NoDE)))))) (Block (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rd_d)) (Atom (Sym (Var fifo_rd))) NoDE)))) (If (Atom (Sym (Var fifo_rd_d))) (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Sub (Atom (Sym (Var bytes_left))) (Atom (Num false 1 (Bin false 1)))) NoDE)))) NoElse) (If (Atom (Sym (Var new_rom))) (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Atom (Sym (Var num_bytes))) NoDE)))) NoElse)))))))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_EF)) (Eq (Atom (Sym (Var bytes_left))) (Atom (Num false 32 (Bin false 0)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_full)) (Gt (Atom (Sym (Var bytes_left))) (Atom (Num false 7 (Hex false 40)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_entries)) (Cond (Atom (Sym (Var rfifo_full))) (Atom (Num false 7 (Hex false 40))) (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_used)) (Atom (Sym (Idx rfifo_entries (TpExpList null) (RngC (Atom (Int 5)) (Atom (Int 0)))))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var new_rom)) (Atom (Num false 1 (Bin false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var num_bytes)) (Atom (Num false 32 (Bin false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rdata)) (Atom (Num false 8 (Bin false 0))) NoDE))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/output.log 0 → 100644
32'D1
1'H1
1'H1
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H1
1'H1
1'H1
29'H0
32'D0
4'H1
4'H8
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
1'H0
3'H0
3'H0
4'H0
32'D4294967295
32'D0
32'Hxxxxxxxx
32'Hxxxxxxxx
32'Hxxxxxxxx
3'Hx
3'Hx
32'D4294967295
32'D0
32'Hxxxxxxxx
32'D0
32'Hxxxxxxxx
3'Hx
2'H0
2'H0
3'H0
32'D1
Cond_2
Cond_3
Cond_4
Cond_5
Cond_6
Cond_7
Cond_8
Cond_9
Cond_10
Cond_11
Cond_12
Cond_13
Cond_14
Cond_15
Cond_16
Cond_17
Cond_274
Cond_276
Cond_278
Cond_280
Cond_283
Cond_284
Cond_285
Cond_286
Cond_287
Cond_288
Cond_289
Cond_291
Cond_292
----- Writting Graph Visialization File -----
Finish!
thirdparty/RTL2CDFG/v2cdfg/run_ast.ys 0 → 100755
# read -verific
read_verilog ./test.v
# elaborate design hierarchy
# hierarchy -check -top top
#big case
hierarchy -check
proc
flatten
memory
write_verilog ./test_ast.v
thirdparty/RTL2CDFG/v2cdfg/src/ast2cdfg.py 0 → 100755
import networkx as nx
from anytree import NodeMixin, AnyNode, RenderTree
# import matplotlib.pyplot as plt
import sys
import re
import os
from ast_from_json import *
from ast_pre import *
from collections import defaultdict
# import pygraphviz as pgv
import matplotlib.pyplot as plt
from structures import *
import math
import copy
original_init = AnyNode.__init__
# AnyNode.__init__ = new_init
def has_suffix(s):
# Suffix matching: eg case_2
return bool(re.search(r"_\d+$", s))
# Delete the level attribute in the AnyNode node, because the node in the AST has a level attribute
def copy_without_level(node):
attributes = node.__dict__.copy()
# delete level
attributes.pop('level', None)
if '_NodeMixin__children' in attributes:
attributes['children'] = attributes.pop('_NodeMixin__children')
else:
attributes['children'] = []
if '_NodeMixin__parent' in attributes:
attributes['parent'] = attributes.pop('_NodeMixin__parent')
else:
attributes['parent'] = []
# Use the remaining attribute
new_node = AnyNode(**attributes)
return new_node
class variable:
def __init__(self,range,type=None) :
self.Range = range
self.type = type
class AnynodeVisitor(object):
def visit(self, node):
"""Visit a node."""
method_name = node.name
if any(node.name.startswith(operator) for operator in operator2list) and not node.name == "Left" and not node.name == "Right" and has_suffix(node.name):
method_name = "Operator2"
if node.name.startswith("Cond") and has_suffix(node.name):
method_name = "Cond"
if node.name.startswith("Idx") and has_suffix(node.name):
method_name = "Idx"
if node.name.startswith("Conc") and has_suffix(node.name):
method_name = "Conc"
if node.name.startswith("Lconc") and has_suffix(node.name):
method_name = "Lconc"
if node.name.startswith("Casez") and has_suffix(node.name):
method_name = "Casez"
if node.name.startswith("TpSigDeclBody") and has_suffix(node.name):
method_name = "TpSigDeclBody"
if node.name.startswith("PartAssign") and has_suffix(node.name):
method_name = "PartAssign"
if any(node.name.startswith(operator) for operator in operator1list) and has_suffix(node.name):
method_name = "Operator1"
method = 'visit_' + method_name
visitor = getattr(self, method, self.generic_visit)
return visitor(node)
def generic_visit(self, node):
"""Called if no explicit visitor function exists for a node."""
if node.children:
for child in node.children:
self.visit(child)
else:
()
def generic_rev_visit(self, node):
if node.children:
for child in reversed(node.children):
self.visit(child)
else:
()
class DFGExtractor(AnynodeVisitor):
def __init__(self, graph=None):
# Dictionary definitions.
self.defs = {} # Variable definition locations.
self.uses = {} # Variable use locations.
self.dfg = graph if graph is not None else nx.MultiDiGraph() # Initialize a directed graph to represent CDFG
# Operand and target stacks for arithmetic operator matching.
self.target = []
self.Source1 = []
self.Source2 = []
# Store ternary cond operands and targets.
self.cond_source1 = []
self.cond_source2 = []
self.cond_source3 = []
self.cond_target = []
# Operator stack for matching.
self.operators = []
# Condition stack.
self.conditions = []
# Concat stack for matching concat content.
self.conc = []
# Case stack.
self.casez = []
# Branch indicator; used to detect current branch during traversal.
self.ast_branch = "init"
self.con_label = 0 # Label for concat edges.
self.oper_label = 0
self.const_label = 0
self.case_num = 0 #
self.parameter = 0 # Index of function parameter during calls.
self.conc_num = 0 # Count of conc instances.
self.wire_set = set()
self.var_set = set()
self.in_set = set() # Inputs for graph rendering.
self.out_set = set() # Outputs for graph rendering.
self.sigset_set = set() # Internal signal set (function locals, etc.).
self.seq_set = set()
self.comb_set = set() # Connector set: operators and condition symbols.
self.label_set = set() # Case label set.
self.edge_set = set()
self.node_dict = {} # Node lookup for edge wiring.
self.edge_dict = {} # Edge lookup by id.
self.wire_dict = {} #
self.temp_dict = {} #
self.fundec = 0 # Inside function definition; avoid name collisions.
self.func_input_num = 0 # Function parameter count.
self.func_input_list = [] # Function parameter list.
self.func_list = [] # Track function definitions.
self.func_dict = {} # Function node lookup.
self.func_call = "" # Current function name during calls.
self.func_left = None # Record function assignment target.
self.current_scope = {} # Current scope for nested functions/control structures.
self.if_scope = None # Track if-scope status.
# hzq
self.left = 0
self.part = 0
#hzq
self.tpRange = [0, 0] # Store variable range; [0,0] means length 1.
self.type = None
self.vars = {} # Variable definitions and metadata.
self.partselects = [] # Partselects in lconc.
#block
self.block_num = 0
#expression
self.var_exp = var_exp
self.Idx_operator2_left = None
self.Idx_operator2_right = None
self.Idx_exp = None
def var_exp_directory(self,key):
if key in self.var_exp:
return self.var_exp[key]
else:
return key
def in_nodes(self, node):
for node_id in self.dfg.nodes:
# print(f"nodename : {node.name}")
attributes = node.__dict__.copy()
if node.name == node_id.name:
# print(f"repeat : {node.name}")
return True
self.node_dict[node.name] = node
return False
def visit_Function(self, node):
self.func_input_num = 0
self.func_input_list = []
self.fundec = 1
if node.children[0].name == "TpFunHead":
tnode = node.children[0]
if len(tnode.children) > 1:
function_name = tnode.children[1].name
self.current_scope["Function" + function_name] = [self.func_input_num,self.func_input_list]
self.func_list.insert(0, "Function" + function_name)
self.generic_visit(node)
if self.func_dict["Function" + function_name].startswith("Casez"):
print(f"remove {self.func_list[0] + function_name}")
self.dfg.remove_node(self.node_dict[self.func_list[0] + function_name])
self.fundec = 0
# self.current_scope.pop("Function" + function_name)
# hzq
def visit_TpSigDeclBody(self,node):
if node.parent.name == "Wire" or node.parent.name == "Reg":
self.type = node.parent.name
else:
self.type = None
if node.children[0].name == "TpVarTplist" :
self.tpRange[0] = 0
self.tpRange[1] = 0
elif node.children[0].name == "RngC" :
self.tpRange[0] = int(node.children[0].children[0].children[0].name)
self.tpRange[1] = int(node.children[0].children[1].children[0].name)
self.generic_visit(node)
# yanlw 26/8/2024
def visit_PartAssign(self, node):
node = copy_without_level(node)
self.add_node(node)
self.comb_set.add(node.name)
isLname = 1 # 1 = name, 0 = conc
# print(f"partassign: {node.name}; ast_branch：{self.ast_branch}, {node.children} ")
if node.children:
if node.children[0].name in self.node_dict.keys():
self.add_edge(self.node_dict[node.name],self.node_dict[node.children[0].name], label = 1)
i = 1
while len(node.children) > i and node.children[i].name == "TpExpList":
tnode = node.children[i]
# hzq
if self.ast_branch.startswith("Lconc") :
if tnode.children[0]:
#yanlw 8/15
isLname = 0
tnode1 = AnyNode(name = "PartSelect_" + str(self.part))
#yanlw 8/15
self.partselects.append("PartSelect_" + str(self.part))
self.add_node(tnode1)
self.comb_set.add(tnode1.name)
self.add_edge(self.node_dict[tnode1.name],self.node_dict[node.name], label = 1)
tnode2 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[tnode1.name], label = 3)
# print (self.left + int(tnode.children[0].children[0].name))
tnode3 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode3)
self.add_edge(self.node_dict[tnode3.name],self.node_dict[tnode1.name], label = 2)
# self.add_edge(self.node_dict[self.conc[0]],self.node_dict[tnode1.name], label = self.part + 1)
self.left = self.left + 1
self.part = self.part + 1
# print(f"self.left: {self.left}")
if tnode.children[0]:
tnode2 = AnyNode(name = "Constant_" + tnode.children[0].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = i+1)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = i+2)
i = i + 1
if len(node.children) > i and node.children[i].name == "RngC":
tnode = node.children[i]
tnode = copy_without_level(tnode)
# print(f"partassign: {node.name}; ast_branch：{self.ast_branch} ")
if self.ast_branch.startswith("Lconc") :
if tnode.children[0]:
#yanlw 8/15
isLname = 0
# partselect -> partassign
tnode1 = AnyNode(name = "PartSelect_" + str(self.part))
#yanlw 8/15
self.partselects.append("PartSelect_" + str(self.part))
self.add_node(tnode1)
self.comb_set.add(tnode1.name)
self.add_edge(self.node_dict[tnode1.name],self.node_dict[node.name], label = 1)
tnode2 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[tnode1.name], label = 3)
self.left = self.left + int(tnode.children[0].children[0].name) - int(tnode.children[1].children[0].name)
# print (self.left + int(tnode.children[0].children[0].name))
tnode3 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode3)
self.add_edge(self.node_dict[tnode3.name],self.node_dict[tnode1.name], label = 2)
# self.add_edge(self.node_dict[self.conc[0]],self.node_dict[tnode1.name], label = self.part + 1)
self.left = self.left + 1
self.part = self.part + 1
if tnode.children[0]:
tnode2 = AnyNode(name = "Constant_" + tnode.children[0].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 2)
if tnode.children[1]:
tnode2 = AnyNode(name = "Constant_" + tnode.children[1].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 3)
if len(node.children) > i and node.children[i].name == "RngP":
tnode = node.children[i]
tnode = copy_without_level(tnode)
if self.ast_branch.startswith("Lconc") :
if tnode.children[0]:
#yanlw 8/15
isLname = 0
# partselect -> partassign
tnode1 = AnyNode(name = "PartSelect_" + str(self.part))
#yanlw 8/15
self.partselects.append("PartSelect_" + str(self.part))
self.add_node(tnode1)
self.comb_set.add(tnode1.name)
self.add_edge(self.node_dict[tnode1.name],self.node_dict[node.name], label = 1)
tnode2 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[tnode1.name], label = 2)
self.left = self.left + int(tnode.children[0].children[0].name) - int(tnode.children[1].children[0].name)
# print (self.left + int(tnode.children[0].children[0].name))
tnode3 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode3)
self.add_edge(self.node_dict[tnode3.name],self.node_dict[tnode1.name], label = 3)
# self.add_edge(self.node_dict[self.conc[0]],self.node_dict[tnode1.name], label = self.part + 1)
self.left = self.left + 1
self.part = self.part + 1
if tnode.children[0]:
# Assume nodes already created.
if tnode.children[0].name == "Var":
# print(f"node: {tnode.children[0].children[0]}")
self.add_edge(self.node_dict[tnode.children[0].children[0].name],self.node_dict[node.name], label = 2)
if tnode.children[1]:
tnode2 = AnyNode(name = "Constant_plus" + tnode.children[1].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 3)
if len(node.children) > i and node.children[i].name == "RngN":
if tnode.children[0]:
# Assume nodes already created.
if tnode.children[0].name == "Var":
# print(f"node: {tnode.children[0].children[0]}")
self.add_edge(self.node_dict[tnode.children[0].children[0].name],self.node_dict[node.name], label = 2)
if tnode.children[1]:
tnode2 = AnyNode(name = "Constant_neg" + tnode.children[1].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 3)
# flag is target
if isLname :
self.target.insert(0, node.name)
def visit_ilists(self,node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_olists(self,node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_sigset(self,node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_body(self,node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_TpVarTp(self,node):
temp_ast_branch = self.ast_branch
if self.ast_branch == "init":
()
elif self.ast_branch.startswith("ilists"):
if node.children[0] and not self.in_nodes(node.children[0]):
# hzq
# print(f"{node.children[0].name} : {self.tpRange}")
self.vars[node.children[0].name] = variable(self.tpRange.copy(),self.type)
self.in_set.add(node.children[0].name)
self.var_set.add(node.children[0].name)
tnode = copy_without_level(node.children[0])
self.add_node(tnode)
if len(node.children) > 1:
self.target.insert(0,node.children[0].name)
elif self.ast_branch.startswith("olists"):
if node.children[0] and not self.in_nodes(node.children[0]):
self.vars[node.children[0].name] = variable(self.tpRange.copy(),self.type)
self.out_set.add(node.children[0].name)
self.var_set.add(node.children[0].name)
tnode = copy_without_level(node.children[0])
self.add_node(tnode)
if len(node.children) > 1:
self.target.insert(0,node.children[0].name)
elif self.ast_branch.startswith("sigset"):
if node.children[0] and not self.in_nodes(node.children[0]):
# print(f"sigset:{node.children[0]}")
self.vars[node.children[0].name] = variable(self.tpRange.copy(),self.type)
self.sigset_set.add(node.children[0].name)
self.var_set.add(node.children[0].name)
tnode = copy_without_level(node.children[0])
self.add_node(tnode)
if len(node.children) > 1:
self.target.insert(0,node.children[0].name)
if node.children[0] and self.fundec == 1 and self.current_scope:
# hzq
node.children[0].name = self.func_list[0] + node.children[0].name
self.vars[node.children[0].name] = variable(self.tpRange.copy(),self.type)
self.sigset_set.add(node.children[0].name)
self.var_set.add(node.children[0].name)
tnode = copy_without_level(node.children[0])
self.add_node(tnode)
# print(node.children[0].name)
self.current_scope[self.func_list[0]][0] += 1
self.current_scope[self.func_list[0]][1].append(node.children[0].name)
else:
if node.children[0] and not self.in_nodes(node.children[0]):
self.vars[node.children[0].name] = variable(self.tpRange.copy(),self.type)
self.sigset_set.add(node.children[0].name)
self.var_set.add(node.children[0].name)
tnode = copy_without_level(node.children[0])
self.add_node(tnode)
if len(node.children) > 1:
self.target.insert(0,node.children[0].name)
self.ast_branch = node.name
self.generic_visit(node)
self.ast_branch = temp_ast_branch
def visit_TpEqAssign(self, node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_Cond(self, node):
node = copy_without_level(node)
self.add_node(node)
self.comb_set.add(node.name)
# print(self.ast_branch)
# print(self.ast_branch)
# hzq
if self.ast_branch.startswith("Lconc"):
# if self.target:
target_name = self.target[0]
# print("target:" + target_name)
if target_name.startswith("Lconc"):
# print(self.partselects)
# print(self.partselects)
for partsel in self.partselects :
# print(node.name + " " + partsel + "\n")
self.add_edge(self.node_dict[node.name], self.node_dict[partsel], label = 1)
if self.ast_branch.startswith("Lname"):
# if self.target:
target_name = self.target[0]
self.cond_target.insert(0,node.name)
self.add_edge(self.node_dict[node.name], self.node_dict[target_name], label = 1)
if self.if_scope == "TrueBlock" :
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 2)
if self.if_scope == "FalseBlock":
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 3)
# if self.if_scope == "TrueBlock" :
# self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 2)
if self.if_scope:
if node.parent.name == "TrueBlock":
tlabel = 2
if node.parent.name == "FalseBlock":
tlabel = 3
self.add_edge(self.node_dict[node.name],self.node_dict[self.conditions[0]], label = tlabel)
if node.name.startswith("Cond_If"):
assert False,"Exist if in design!"
self.if_scope = "If"
self.conditions.insert(0,node.name)
self.ast_branch = node.name
self.generic_visit(node)
if node.name.startswith("Cond_If"):
self.if_scope = None
def visit_TrueBlock(self, node):
# if self.ast_branch.startswith("Cond"):
self.ast_branch = "TrueBlock"
# else:
# ()
if self.if_scope == "If":
self.if_scope = "TrueBlock"
self.generic_visit(node)
def visit_FalseBlock(self, node):
# if self.ast_branch.startswith("Cond") or self.ast_branch.startswith("TrueBlock"):
self.ast_branch = "FalseBlock"
# else:
# ()
if self.if_scope == "TrueBlock":
self.if_scope = "FalseBlock"
self.generic_visit(node)
def visit_Lname(self, node):
self.ast_branch = node.name
self.generic_visit(node)
# def visit_Lconc(self, node):
# # hzq
# self.left = 0
# self.add_node(node)
# self.node_dict[node.name] = copy_without_level(node)
# self.comb_set.add(node.name)
# node.is_target = True
# # if node.children:
# # if node.children[0].name == "TpConcList":
# # tnode = node.children[0]
# # for element in tnode.children:
# # if element.name == "Ele":
# self.conc.insert(0, node.name)
# self.target.insert(0, node.name)
# self.ast_branch = node.name
# self.generic_visit(node)
# self.con_label = 0
# hzq
def visit_Lconc(self, node):
# hzq
self.left = 0
self.partselects = []
self.target.insert(0, node.name)
self.ast_branch = node.name
self.conc_num += 1
if node.children:
if node.children[0].name == "TpConcList":
self.generic_rev_visit(node.children[0])
else : self.generic_visit(node)
def visit_Left(self, node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_Right(self, node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_Conc(self,node):
node = copy_without_level(node)
self.add_node(node)
self.comb_set.add(node.name)
# if node.children:
# if node.children[0].name == "TpConcList":
# tnode = node.children[0]
# for element in tnode.children:
# if element.name == "Ele":
self.conc.insert(0, node.name)
# print(self.ast_branch)
self.conc_num += 1
if self.ast_branch.startswith("Lname") or self.ast_branch.startswith("Lconc"):
if not node.parent.name == "Lname" and not node.parent.name == "Lconc":
# if self.target:
if self.ast_branch.startswith("Lconc"):
for partsel in self.partselects :
# print(node.name + " " + partsel + "\n")
self.add_edge(self.node_dict[node.name], self.node_dict[partsel], label = 1)
else:
target_name = self.target[0]
self.add_edge(self.node_dict[node.name], self.node_dict[target_name], label = 1)
else:
self.target.insert(0,node.name)
if self.if_scope == "TrueBlock" :
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 2)
if self.if_scope == "FalseBlock" :
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 3)
if self.ast_branch.startswith("TpParaList") or (node.parent and node.parent.name == "Pexp"):
function_name = self.func_call
inputnumber = self.current_scope[function_name][0]
inputlist = self.current_scope[function_name][1]
# print(self.parameter)
# print(inputlist)
self.add_edge(self.node_dict[node.name], self.node_dict[inputlist[self.parameter]], label = 1)
self.parameter += 1
if self.ast_branch.startswith("Cond"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.name], self.node_dict[node_name], label =1)
if self.ast_branch.startswith("TrueBlock"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.name], self.node_dict[node_name], label =2)
if self.ast_branch.startswith("FalseBlock"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.name], self.node_dict[node_name], label =3)
if self.ast_branch == 'Left':
self.Source1.insert(0, node.name)
if self.ast_branch == 'Right':
self.Source2.insert(0, node.name)
target_name = self.target[0]
operator_name = self.operators[0]
# print(self.Source1[0])
# print(self.Source2[0])
self.add_edge(self.node_dict[self.Source1[0]], self.node_dict[operator_name], label =1)
self.add_edge(self.node_dict[self.Source2[0]], self.node_dict[operator_name], label =2)
if self.if_scope == "If":
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.conditions[0]], label = 1)
else:
self.add_edge(self.node_dict[operator_name], self.node_dict[target_name], label =1)
if self.ast_branch.startswith("Operator1"):
self.add_edge(self.node_dict[node.name], self.node_dict[self.operators[0]], label = 1)
if self.if_scope == "If":
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.conditions[0]], label = 1)
else:
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.target[0]], label = 1)
# yanlw
if self.ast_branch.startswith("PartAssign"):
target_name = self.target[0]
if target_name.startswith("Lconc"):
for partsel in self.partselects :
# print(node.name + " " + partsel + "\n")
self.add_edge(self.node_dict[node.name], self.node_dict[partsel], label = 1)
if target_name.startswith("PartAssign"):
self.add_edge(self.node_dict[node.name], self.node_dict[target_name], label = 1)
self.ast_branch = node.name
self.generic_visit(node)
self.con_label = 0
def visit_Idx(self,node):
node = copy_without_level(node)
self.add_node(node)
self.Idx_exp = str(node.children[0].name)
self.comb_set.add(node.name)
if node.children:
if self.fundec == 1:
node.children[0].name = self.func_list[0] + node.children[0].name
if node.children[0].name in self.node_dict.keys():
self.add_edge(self.node_dict[node.children[0].name],self.node_dict[node.name], label = 1)
i = 1
while len(node.children) > i and node.children[i].name == "TpExpList":
tnode = node.children[i]
# hzq
if self.ast_branch.startswith("Lconc"):
if tnode.children[0]:
tnode1 = AnyNode(name = "PartSelect_" + str(self.part))
self.partselects.append("PartSelect_" + str(self.part))
self.add_node(tnode1)
self.comb_set.add(tnode1.name)
self.add_edge(self.node_dict[tnode1.name],self.node_dict[node.name], label = 1)
tnode2 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[tnode1.name], label = 3)
# print (self.left + int(tnode.children[0].children[0].name))
tnode3 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode3)
self.add_edge(self.node_dict[tnode3.name],self.node_dict[tnode1.name], label = 2)
# self.add_edge(self.node_dict[self.conc[0]],self.node_dict[tnode1.name], label = self.part + 1)
self.left = self.left + 1
self.part = self.part + 1
if tnode.children[0]:
tnode2 = AnyNode(name = "Constant_" + tnode.children[0].children[0].name)
self.add_node(tnode2)
self.Idx_exp = self.Idx_exp + f"[{str(tnode.children[0].children[0].name)}]"
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = i+1)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = i+2)
i = i + 1
if len(node.children) > i and node.children[i].name == "RngC":
tnode = node.children[i]
# hzq
if self.ast_branch.startswith("Lconc"):
if tnode.children[0]:
tnode1 = AnyNode(name = "PartSelect_" + str(self.part))
self.partselects.append("PartSelect_" + str(self.part))
self.add_node(tnode1)
self.comb_set.add(tnode1.name)
self.add_edge(self.node_dict[tnode1.name],self.node_dict[node.name], label = 1)
tnode2 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[tnode1.name], label = 3)
self.left = self.left + int(tnode.children[0].children[0].name) - int(tnode.children[1].children[0].name)
# print (self.left + int(tnode.children[0].children[0].name))
tnode3 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode3)
self.add_edge(self.node_dict[tnode3.name],self.node_dict[tnode1.name], label = 2)
# self.add_edge(self.node_dict[self.conc[0]],self.node_dict[tnode1.name], label = self.part + 1)
self.left = self.left + 1
self.part = self.part + 1
if tnode.children[0]:
tnode2 = AnyNode(name = "Constant_" + tnode.children[0].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 2)
if tnode.children[1]:
tnode2 = AnyNode(name = "Constant_" + tnode.children[1].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 3)
# yanlw
if len(node.children) > i and node.children[i].name == "RngP":
tnode = node.children[i]
# print(f"node: {tnode}")
# print(f"node: {tnode.children[0]}")
# print(f"node: {tnode.children[1]}")
if tnode.children[0]:
# Assume nodes already created.
if tnode.children[0].name == "Var":
# print(f"node: {tnode.children[0].children[0]}")
self.add_edge(self.node_dict[tnode.children[0].children[0].name],self.node_dict[node.name], label = 2)
if tnode.children[1]:
tnode2 = AnyNode(name = "Constant_plus" + tnode.children[1].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 3)
if len(node.children) > i and node.children[i].name == "RngN":
tnode = node.children[i]
if tnode.children[0]:
# Assume nodes already created.
if tnode.children[0].name == "Var":
# print(f"node: {tnode.children[0].children[0]}")
self.add_edge(self.node_dict[tnode.children[0].children[0].name],self.node_dict[node.name], label = 2)
if tnode.children[1]:
tnode2 = AnyNode(name = "Constant_neg" + tnode.children[1].children[0].name)
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[node.name], label = 3)
if self.ast_branch.startswith("Lname"):
# if self.target:
if self.target:
target_name = self.target[0]
if self.func_list and target_name.startswith(self.func_list[0]):
self.add_edge(self.node_dict[node.name], self.node_dict[self.casez[0]], label = self.case_num)
elif node.parent.name == "Lname":
self.target.insert(0, node.name)
if self.if_scope == "TrueBlock" :
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 2)
if self.if_scope == "FalseBlock" :
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 3)
elif node.parent.name == "TpEqAssign":
self.add_edge(self.node_dict[node.name], self.node_dict[target_name], label = 1)
if self.ast_branch.startswith("TpVarTp"):
if self.target:
target_name = self.target[0]
self.add_edge(self.node_dict[node.name], self.node_dict[target_name], label = 1)
if self.ast_branch.startswith("TpParaList") or (node.parent and node.parent.name == "Pexp"):
function_name = self.func_call
inputnumber = self.current_scope[function_name][0]
inputlist = self.current_scope[function_name][1]
# print(self.parameter)
# print(inputlist)
self.add_edge(self.node_dict[node.name], self.node_dict[inputlist[self.parameter]], label = 1)
self.parameter += 1
if self.ast_branch.startswith("Cond"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.name], self.node_dict[node_name], label =1)
if self.ast_branch.startswith("TrueBlock"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.name], self.node_dict[node_name], label =2)
if self.ast_branch.startswith("FalseBlock"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.name], self.node_dict[node_name], label =3)
if self.ast_branch.startswith("Conc"):
self.con_label += 1
# print(node.name)
# print(self.con_label)
self.add_edge(self.node_dict[node.name],self.node_dict[self.conc[0]], label = self.con_label)
if self.ast_branch.startswith("Left"):
self.Source1.insert(0,node.name)
if self.ast_branch.startswith("Right"):
self.Source2.insert(0,node.name)
if self.target and self.Source1 and self.Source2 and self.operators:
# Pop stack.
target_name = self.target[0]
operator_name = self.operators[0]
self.add_edge(self.node_dict[self.Source1[0]], self.node_dict[operator_name], label =1)
self.add_edge(self.node_dict[self.Source2[0]], self.node_dict[operator_name], label =2)
if self.if_scope == "If":
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.conditions[0]], label = 1)
else:
self.add_edge(self.node_dict[operator_name], self.node_dict[target_name], label = 1)
if self.ast_branch.startswith("Operator1"):
self.add_edge(self.node_dict[node.name], self.node_dict[self.operators[0]], label = 1)
if self.if_scope == "If":
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.conditions[0]], label = 1)
else:
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.target[0]], label = 1)
# self.ast_branch = node.name
return
self.generic_visit(node)
def visit_Operator1(self, node):
node = copy_without_level(node)
self.add_node(node)
self.comb_set.add(node.name)
self.operators.insert(0,node.name)
self.ast_branch = "Operator1"
self.generic_visit(node)
def visit_Operator2(self, node):
# print(node.name)
node = copy_without_level(node)
self.add_node(node)
self.comb_set.add(node.name)
self.operators.insert(0,node.name)
# yanlw 23/8/2024
if self.ast_branch.startswith("Lconc"):
# print(f"operator2:{node.name}, operate_target: {self.target[0]}, {self.ast_branch}")
# if self.target:
target_name = self.target[0]
# print("target:" + target_name)
if target_name.startswith("Lconc"):
for partsel in self.partselects :
self.add_edge(self.node_dict[node.name], self.node_dict[partsel], label = 1)
if self.ast_branch.startswith("Lname"):
# if self.target:
target_name = self.target[0]
self.add_edge(self.node_dict[node.name], self.node_dict[target_name], label = 1)
self.ast_branch = "Operator2"
self.generic_visit(node)
def visit_Num(self, node):
str = "Constant_"
if node.children[0]:
str = str + node.children[0].name + "'"
if len(node.children) > 1 and node.children[1]:
if node.children[1].name == "Hex" or node.children[1].name == "Bin" or node.children[1].name == "Dec" or node.children[1].name == "Oct":
str = str + node.children[1].name[0]
if node.children[1].children[0]:
str = str + node.children[1].children[0].name
str = "Const,"+ node.children[0].name + "," + str
tnode = AnyNode(name = str)
# print(tnode.name)
self.add_node(tnode)
# print(self.ast_branch)
if self.ast_branch.startswith("Lname") or self.ast_branch.startswith("Lconc"):
target_name = self.target[0]
if "Function" + target_name in self.func_list:
self.add_edge(self.node_dict[tnode.name], self.node_dict[self.casez[0]], label = self.case_num)
elif node.parent.name == "TpEqAssign":
self.add_edge(self.node_dict[tnode.name], self.node_dict[target_name], label = 1)
if self.ast_branch.startswith("TpVarTp"):
if self.target:
target_name = self.target[0]
self.add_edge(self.node_dict[tnode.name], self.node_dict[target_name], label = 1)
if self.ast_branch.startswith("TpParaList"):
function_name = self.func_call
inputnumber = self.current_scope[function_name][0]
inputlist = self.current_scope[function_name][1]
self.add_edge(self.node_dict[tnode.name], self.node_dict[inputlist[self.parameter]], label = 1)
# print(self.node_dict[inputlist[self.parameter]])
self.parameter += 1
if self.ast_branch.startswith("Cond"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[tnode.name], self.node_dict[node_name], label =1)
if self.ast_branch.startswith("TrueBlock"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[tnode.name], self.node_dict[node_name], label =2)
if self.ast_branch.startswith("FalseBlock"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[tnode.name], self.node_dict[node_name], label =3)
if self.ast_branch.startswith("TpCase"):
node_name = self.casez[0]
self.label_set.add(tnode.name)
self.add_edge(self.node_dict[tnode.name], self.node_dict[node_name], label = self.case_num)
if self.ast_branch.startswith("Left"):
self.Source1.insert(0, tnode.name)
if self.ast_branch.startswith("Right"):
self.Source2.insert(0, tnode.name)
if self.target and self.Source1 and self.Source2 and self.operators:
# Pop stack.
target_name = self.target[0]
operator_name = self.operators[0]
# print(self.Source1[0])
# print(self.Source2[0])
self.add_edge(self.node_dict[self.Source1[0]], self.node_dict[operator_name], label =1)
self.add_edge(self.node_dict[self.Source2[0]], self.node_dict[operator_name], label =2)
# print(f"{target_name}+ {operator_name}")
# print(f"{ self.node_dict[target_name]} ")
# yanlw 26/8/2024
if self.node_dict.get(target_name):
self.add_edge(self.node_dict[operator_name], self.node_dict[target_name], label =1)
if self.ast_branch.startswith("Conc") or self.ast_branch.startswith("Lconc"):
self.con_label += 1
self.add_edge(self.node_dict[tnode.name],self.node_dict[self.conc[0]], label = self.con_label)
if self.ast_branch.startswith("Operator1"):
self.add_edge(self.node_dict[tnode.name], self.node_dict[self.operators[0]], label = 1)
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.target[0]], label = 1)
return
self.generic_visit(node)
def visit_Default(self,node):
node = copy_without_level(node)
self.add_node(node)
self.label_set.add(node.name)
self.add_edge(self.node_dict[node.name], self.node_dict[self.casez[0]], label = self.case_num)
self.ast_branch = node.name
self.generic_visit(node)
def visit_Var(self, node):
if self.fundec == 1:
node.children[0].name = self.func_list[0] + node.children[0].name
if not self.in_nodes(node.children[0]):
# print(f"node : {node.children[0].name}")
tnode = copy_without_level(node.children[0])
self.add_node(tnode)
# self.wire_set.add(node.children[0].name)
self.sigset_set.add(node.children[0].name) # Intermediate variable.
# hzq
if self.ast_branch.startswith("Lconc") or (self.ast_branch.startswith("PartAssign") and node.parent.name == "Ele"):
if node.children[0]:
rang = self.vars[node.children[0].name].Range
tnode1 = AnyNode( name = "PartSelect_" + str(self.part))
self.partselects.append("PartSelect_" + str(self.part))
self.add_node(tnode1)
self.comb_set.add(tnode1.name)
self.add_edge(self.node_dict[tnode1.name],self.node_dict[node.children[0].name], label = 1)
tnode2 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode2)
self.add_edge(self.node_dict[tnode2.name],self.node_dict[tnode1.name], label = 3)
self.left = self.left + rang[0] - rang[1]
# print (self.left + int(tnode.children[0].children[0].name))
tnode3 = AnyNode(name = "Constant_" + str(self.left))
self.add_node(tnode3)
self.add_edge(self.node_dict[tnode3.name],self.node_dict[tnode1.name], label = 2)
# self.add_edge(self.node_dict[self.conc[0]], self.node_dict[tnode1.name], label = self.part + 1)
self.left = self.left + 1
self.part = self.part + 1
# yanlw
if node.parent.name == "TpEqAssign" and self.target:
target_name = self.target[0]
if self.func_list and target_name.startswith(self.func_list[0]):
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[self.casez[0]], label = self.case_num)
elif self.ast_branch.startswith("PartAssign"):
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[target_name], label =1)
else:
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[target_name], label =1)
if self.ast_branch.startswith("TpVarTp"):
if self.target:
target_name = self.target[0]
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[target_name], label = 1)
if self.ast_branch.startswith("Lname"):
# if node.parent.parent.children[1] and node.parent.parent.children[1].name == "Cond":
# self.add_edge(self.node_dict["Cond"], self.node_dict[node.children[0].name], label = 1)
# else:
# print(node.children[0].name)
if node.parent.name == "Lname" or node.parent.name == "Lconc":
# if self.target:
self.target.insert(0,node.children[0].name)
target_name = node.children[0].name
if self.if_scope == "TrueBlock" :
# print("TrueBlock")
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 2)
if self.if_scope == "FalseBlock" :
# print("FalseBlock")
self.add_edge(self.node_dict[target_name],self.node_dict[self.conditions[0]], label = 3)
if self.ast_branch.startswith("TpParaList") or node.parent.name == "Pexp":
function_name = self.func_call
inputnumber = self.current_scope[function_name][0]
inputlist = self.current_scope[function_name][1]
# print(self.parameter)
# print(inputlist)
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[inputlist[self.parameter]], label = 1)
self.parameter += 1
if self.ast_branch.startswith("Cond"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[node_name], label =1)
if self.ast_branch.startswith("TrueBlock"):
node_name = self.conditions[0]
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[node_name], label =2)
if self.ast_branch.startswith("FalseBlock"):
node_name = self.conditions[0]
# print(f"node_name:{node_name}")
# print(node.children[0].name)
print(self.conditions[0])
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[node_name], label =3)
if self.ast_branch.startswith("Left"):
self.Source1.insert(0, node.children[0].name)
if self.ast_branch.startswith("Right"):
# print(self.Source1[0])
self.Source2.insert(0, node.children[0].name)
if self.target and self.Source1 and self.Source2 and self.operators:
# Pop stack.
target_name = self.target[0]
operator_name = self.operators[0]
self.add_edge(self.node_dict[self.Source1[0]], self.node_dict[operator_name], label =1)
self.add_edge(self.node_dict[self.Source2[0]], self.node_dict[operator_name], label =2)
if self.if_scope == "If":
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.conditions[0]], label = 1)
else:
self.add_edge(self.node_dict[operator_name], self.node_dict[target_name], label = 1)
if self.ast_branch.startswith("Conc"):
self.con_label += 1
self.add_edge(self.node_dict[node.children[0].name],self.node_dict[self.conc[0]], label = self.con_label)
if self.ast_branch.startswith("Operator1"):
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[self.operators[0]], label = 1)
if self.if_scope == "If":
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.conditions[0]], label = 1)
else:
self.add_edge(self.node_dict[self.operators[0]], self.node_dict[self.target[0]], label = 1)
if self.ast_branch.startswith("Casez"):
self.case_num += 1
tnode = copy_without_level(node.children[0])
self.add_edge(self.node_dict[node.children[0].name], self.node_dict[self.casez[0]], label = self.case_num)
if self.ast_branch == "Ufname":
self.func_call = "Function" + node.children[0].name
self.dfg.remove_node(self.node_dict[node.children[0].name])
# print("call:" + self.func_call)
self.generic_visit(node)
def visit_Sfname(self,node):
self.func_call = "Function" + node.children[0].name
assert False,"Exist SysFunName!"
def visit_Casez(self,node):
node = copy_without_level(node)
self.add_node(node)
self.comb_set.add(node.name)
self.casez.insert(0, node.name)
self.case_num = 0
if self.func_list:
function_name = self.func_list[0]
self.func_dict[function_name] = node.name
# inum = self.current_scope[function_name][0]
# self.case_num += inum
# for i in range(inum):
# node_name = self.current_scope[function_name][1][i]
# self.add_edge(self.node_dict[node_name], node, label = i+1)
if self.if_scope:
if node.parent.name == "TrueBlock":
tlabel = 2
if node.parent.name == "FalseBlock":
tlabel = 3
self.add_edge(self.node_dict[node.name],self.node_dict[self.conditions[0]], label = tlabel)
self.ast_branch = node.name
self.generic_visit(node)
def visit_TpCase(self,node):
self.ast_branch = node.name
self.case_num += 1
self.generic_visit(node)
def visit_Funcall(self,node):
self.func_left = self.ast_branch
self.ast_branch = node.name
self.generic_visit(node)
self.parameter = 0
def visit_TpParaList(self,node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_Ufname(self,node):
self.ast_branch = node.name
self.generic_visit(node)
def visit_TpParaList(self,node):
self.ast_branch = node.name
self.generic_visit(node)
# print(self.func_left)
if self.ast_branch.startswith("Lconc") or self.func_left.startswith("Lconc"):
# if self.target:
target_name = self.target[0]
# print("target:" + target_name)
if target_name.startswith("Lconc"):
# print(self.partselects)
# print(self.partselects)
for partsel in self.partselects :
# print(node.name + " " + partsel + "\n")
self.add_edge(self.node_dict[self.func_dict[self.func_call]], self.node_dict[partsel], label = 1)
else:
self.add_edge(self.node_dict[self.func_dict[self.func_call]], self.node_dict[self.target[0]], label = 1)
self.parameter = 0
def find_node(self, node):
if self.dfg.has_node(node):
return self.dfg.nodes[node]
else:
return None
# Find the specified edge.
def find_edge(self, u, v):
if self.dfg.has_edge(u, v):
return self.dfg[u][v]
else:
return None
def predecessor(self,node):
predecessors = list(self.dfg.predecessors(node))
# print(f"All nodes pointing to {node}: {predecessors}")
return predecessors
def successor(self,node):
successors = list(self.dfg.successors(node))
# print(f"All nodes reachable from {node}: {successors}")
return successors
def is_function_var(self,node):
if node.name.startswith("Function"):
return True
else:
return False
# Extra handling for functions generated from case.
def case_function(self):
for node_name in self.comb_set:
if node_name.startswith("Casez"):
# Find all nodes pointing to this node.
predecessors = self.predecessor(self.node_dict[node_name])
for node in predecessors:
# print(predecessors)
if node.name.startswith("Const") or node.name.startswith("Idx"):
self.delete_node(node)
tpredecessors = self.predecessor(self.node_dict[node_name])
for node in tpredecessors:
if node.name.startswith("Const"):
self.dfg.remove_edge(node,self.node_dict[node_name])
predecessors = self.predecessor(self.node_dict[node_name])
for node in predecessors:
if node.name == "Default":
self.delete_node(node,False)
filter_predecessors = list(filter(self.is_function_var,predecessors))
# print(filter_predecessors)
s_num = 0
b_num = 0
for node in filter_predecessors:
if node.name[-1] == 'a':
# print("a")
a_predecessors = self.predecessor(node)
self.delete_node(node,False,"a")
if node.name[-1] == 's':
# print("s")
s_predecessors = self.predecessor(node)
if len(s_predecessors) == 1 and s_predecessors[0].name.startswith("Conc"):
Conc_node = s_predecessors[0]
Conc_predecessors = self.predecessor(Conc_node)
for predecessor in Conc_predecessors:
# print(predecessor)
s_num = s_num + self.number_of_edges(predecessor,Conc_node)
self.delete_node(node,False,"s")
self.delete_node(Conc_node,True,"s")
if node.name[-1] == 'b':
# print("b")
b_predecessors = self.predecessor(node)
if len(b_predecessors) == 1 and b_predecessors[0].name.startswith("Conc"):
Conc_node = b_predecessors[0]
Conc_predecessors = self.predecessor(Conc_node)
for predecessor in Conc_predecessors:
b_num = b_num + self.number_of_edges(predecessor,Conc_node)
# print(s_num)
# print(b_num)
# assert b_num == s_num,"Case Error!"
self.delete_node(node,False,"b")
self.delete_node(Conc_node,True,"b")
else:
assert False,"Error, Case_b unable to process"
predecessors = self.predecessor(self.node_dict[node_name])
def number_of_edges(self,node1,node2):
return self.dfg.number_of_edges(node1,node2)
# Return the edge label.
def edge_label(self, node1, node2):
# Iterate over the set and check for a matching edge.
for edge in self.edge_set:
if edge[0] == node1.name and edge[1].startswith(node2.name):
return edge[2]
return None
# Delete a node and reconnect a single edge.
def delete_node(self,node,tag = True,parameter = None):
if node:
predecessors = self.predecessor(node)
if len(self.successor(node)) == 1:
target_node = self.successor(node)[0]
for subnode in predecessors:
if parameter == "s":
if tag == True:
edges_number_list = self.edge_dict[(subnode.name.split(',')[-1], node.name.split(',')[-1])]
for edges_number in edges_number_list:
# print(f"edge:{edges_number}")
label = edges_number * 2 - 1
self.add_edge(subnode,target_node,label)
else:
label = self.edge_label(node,target_node) * 2 - 1
self.add_edge(subnode,target_node,label)
elif parameter == "b":
if tag == True:
# edges_ab = list(self.dfg.edges(subnode, node, keys=True))
# edges_ab = [ edge for edge in edges_ab if edge[0] == subnode and edge[1] == node ]
# print(self.edge_dict[(subnode.name, node.name)])
edges_number_list = self.edge_dict[(subnode.name.split(',')[-1], node.name.split(',')[-1])]
for edges_number in edges_number_list:
# print(f"edge:{edges_number}")
label = edges_number * 2
self.add_edge(subnode,target_node,label)
else:
label = self.edge_label(node,target_node) * 2
self.add_edge(subnode,target_node,label)
elif parameter == "a":
if tag == True:
label = self.edge_label(subnode,node) * 2
self.add_edge(subnode,target_node,label)
else:
label = self.edge_label(node,target_node) * 2
self.add_edge(subnode,target_node,label)
else:
if tag == True:
label = self.edge_label(subnode,node)
self.add_edge(subnode,target_node,label)
else:
label = self.edge_label(node,target_node)
self.add_edge(subnode,target_node,label)
# print(f"delete node : {node.name}")
self.dfg.remove_node(node)
# print(f"Node {node} has been removed")
def remove_isolated_nodes(self):
isolated_nodes = [node for node in self.dfg.nodes if self.dfg.degree(node) == 0]
for node in isolated_nodes:
self.dfg.remove_node(node)
# print(f"Isolated node {node} has been removed")
# Add simplification strategy.
def simplify_Idx(self):
u = self.node_dict["Add_1"]
v = self.node_dict["_00_"]
if self.find_edge(u,v):
print("find edge!")
def add_node(self,node):
if not self.in_nodes(node):
self.dfg.add_node(self.node_dict[node.name])
def add_edge(self,node1,node2,label):
if not (node1.name,node2.name,label) in self.edge_set:
self.dfg.add_edge(node1,node2,label = label)
# Use setdefault to simplify dict initialization.
self.edge_dict.setdefault((node1.name.split(',')[-1], node2.name.split(',')[-1]), []).append(label)
# print(f"{(node1.name,node2.name)} : {label}")
self.edge_set.add((node1.name,node2.name,label))
def remove_same_node(self):
nodelist = []
removelist = []
for node in self.dfg.nodes:
if self.in_nodes:
removelist.append(node)
else:
nodelist.append(node)
def remain_Idx(self):
if self.partselects:
exist_partselect = self.partselects[-1]
index = int(exist_partselect[-1]) + 1
else:
index = 0
for node in self.dfg.nodes:
if node.name.startswith("Idx"):
node.name = "PartSelect_" + str(index)
self.node_dict[node.name] = node
self.comb_set.add(node.name)
index += 1
# self.edge_dict[(node.name,)]
# for node_name in removelist:
# print(self.dfg.nodes)
# self.dfg.remove_node(node)
def node_name(self):
inset= set()
outset = set()
sigset = set()
combset = set()
self.remove_same_node()
for node in self.dfg.nodes:
node_name = node.name
if node_name.startswith("Conc"):
self.node_dict[node_name].name = node_name.replace('Conc_', 'Concat_')
if node_name.startswith("Casez"):
self.node_dict[node_name].name = node_name.replace('Casez_', 'Case_')
if node_name in self.in_set:
left = self.vars[node_name].Range[0]
right = self.vars[node_name].Range[1]
Range = left - right + 1
newname = "Input," + str(Range) + "," + self.node_dict[node_name].name
self.node_dict[node_name].name = newname
inset.add(self.node_dict[node_name].name)
if node_name in self.out_set:
left = self.vars[node_name].Range[0]
right = self.vars[node_name].Range[1]
Range = left - right + 1
if self.vars[node_name].type:
newname = "Output" + "_" + self.vars[node_name].type + "," + str(Range) + "," + self.node_dict[node_name].name
else:
newname = "Output," + str(Range) + "," + self.node_dict[node_name].name
self.node_dict[node_name].name = newname
outset.add(self.node_dict[node_name].name)
if node_name in self.sigset_set and not node_name.startswith("Function_"):
left = self.vars[node_name].Range[0]
right = self.vars[node_name].Range[1]
Range = left - right + 1
newname = self.vars[node_name].type + "," + str(Range) + "," + self.node_dict[node_name].name
self.node_dict[node_name].name = newname
sigset.add(self.node_dict[node_name].name)
if node_name in self.comb_set:
operator_type = re.sub(r'_\d+$', '', self.node_dict[node_name].name)
newname = operator_type + ",Null," + self.node_dict[node_name].name
self.node_dict[node_name].name = newname
combset.add(self.node_dict[node_name].name)
if node_name.startswith("Constant_"):
newname = "Const,Null," + node.name
node.name = newname
self.in_set = inset
self.out_set = outset
self.sigset_set = sigset
self.comb_set = combset
# Merge multiple nodes with the same name; keep the first node name.
def node_merge(self,node_name_list,type):
if type == "PartAssign":
merge_node_name = node_name_list[0]
exist_edge_num = 3
# print(node_name_list)
for node_name in node_name_list[1:]:
predecessors = self.predecessor(self.node_dict[node_name])
predecessors_len = len(predecessors)
# print(predecessors_len)
for node in predecessors:
# print("--------------------------------")
# print((node.name,node_name))
# print(self.edge_dict[(node.name.split(',')[-1],node_name.split(',')[-1])])
for edge_num in self.edge_dict[(node.name.split(',')[-1],node_name.split(',')[-1])]:
edge_label = edge_num
self.add_edge(node, self.node_dict[merge_node_name], label = exist_edge_num + edge_label)
# a[0] = b
exist_edge_num += 3
def partassign_merge(self):
remove_list = []
for node in self.dfg.nodes:
predecessors = self.predecessor(node)
names = [node.name for node in predecessors]
partassign_names = [name for name in names if name.startswith('PartAssign')]
remove_list = remove_list + partassign_names[1:]
# Check if there are multiple.
if len(partassign_names) > 1:
# print(f"{node.name} has multiple strings with 'partassign' prefix")
self.node_merge(partassign_names,"PartAssign")
else:
()
remove_node_list = [self.node_dict[node_name] for node_name in remove_list]
self.dfg.remove_nodes_from(remove_node_list)
def partassign_function(self):
remove_list = []
add_list = []
for node in self.dfg.nodes:
if node.name.startswith("PartAssign"):
predecessors = self.predecessor(node)
names = [node.name for node in predecessors]
tnode = AnyNode(name = "Conc_" + str(self.conc_num + 1))
self.conc_num += 1
self.comb_set.add(tnode.name)
self.node_dict[tnode.name] = tnode
partassign_class = [[] for _ in range(math.ceil(len(names) / 3))]
for name in names:
# print("--------------------------------")
# print(self.edge_dict[(name,node.name)])
for edge_label in self.edge_dict[(name.split(',')[-1],node.name.split(',')[-1])]:
# print(f"{(name,node.name)}:{edge_label}")
class_num = int((edge_label+2) / 3)
# Ensure the sublist for class_num exists.
if class_num >= len(partassign_class):
partassign_class.extend([[] for _ in range(class_num - len(partassign_class) + 1)])
# Ensure sublist length allows insertion at index 1 or 2.
while len(partassign_class[class_num]) < 3:
partassign_class[class_num].append(None) # Pad with None.
if (edge_label+2) % 3 == 0:
partassign_class[class_num][0] = name
if (edge_label+2) % 3 == 1:
partassign_class[class_num][1] = name
if (edge_label+2) % 3 == 2:
partassign_class[class_num][1] = name
sorted_partassign_class = sorted(partassign_class, key=lambda x: x[1] if len(x) > 1 else '')
# print(sorted_partassign_class)
new_edge_label = (len(sorted_partassign_class) - 1)
# print(new_edge_label)
for part_assign in sorted_partassign_class:
if part_assign:
# print((self.node_dict[part_assign[0]],tnode,new_edge_label))
add_list.append((self.node_dict[part_assign[0]],tnode,new_edge_label))
new_edge_label -= 1
successors = self.successor(node)
for suc_node in successors:
add_list.append((tnode,suc_node,1))
remove_list.append(node.name)
for add_edge in add_list:
self.add_edge(add_edge[0],add_edge[1],int(add_edge[2]))
remove_node_list = [self.node_dict[node_name] for node_name in remove_list]
self.dfg.remove_nodes_from(remove_node_list)
# Remove wire nodes.
def remove_wires(self):
# Find all wire variables to delete.
wires_to_remove = [node for node in self.dfg.nodes if isinstance(node.name, str) and node.name.startswith("_") and node.name.endswith("_")]
print(wires_to_remove)
print(self.edge_dict)
for wire in wires_to_remove:
predecessors = list(self.dfg.predecessors(wire))
successors = list(self.dfg.successors(wire))
# Check wire predecessors and successors first.
if predecessors and successors:
# If wire has both predecessors and successors, connect them.
for pred in predecessors:
for succ in successors:
label = self.edge_dict[(wire.name.split(',')[-1],succ.name.split(',')[-1])]
print(f"({wire.name},{succ.name}):{label[0]}")
self.add_edge(pred, succ, label[0]) # Connect predecessor and successor.
# Delete the wire last.
self.dfg.remove_node(wire)
def extract_name(self, text):
match = re.match(r"([^,]+),([^,]+),([^,]+)", text)
if match:
part1 = match.group(1) # Extract part 1.
part2 = match.group(2) # Extract part 2.
part3 = match.group(3) # Extract part 3.
if part1 == "Const" and part2 != "Null":
return text
return part3
else:
raise ValueError("Input format mismatch; cannot extract parts.")
def print_graph(self, G):
# Print each edge and its attributes, including label.
for edge in G.edges(data=True):
print(edge)
for node in G.nodes(data=True):
print(node)
# def load_dot_file(self, dot_file_path):
# Read dot file and convert to a networkx graph.
# A = pgv.AGraph(dot_file_path)
# G = nx.nx_agraph.from_agraph(A)
# return G
# def find_boundary_nodes(self, G, link_node, subgraph_nodes):
# # Find boundary nodes that connect to external nodes in the current subgraph.
# boundary_nodes = set()
# for sub_node in subgraph_nodes :
# if sub_node != link_node:
# for neighbor in G.neighbors(sub_node):
# if neighbor not in subgraph_nodes:
# boundary_nodes.add(sub_node)
# # break # Exit loop after finding boundary node.
# return boundary_nodes
def find_boundary_nodes(self, G, node, subgraph_nodes):
# Find subgraph input/output boundary nodes.
boundary_nodes = set()
for n in subgraph_nodes:
# If a node predecessor or successor is in the full graph but not in the subgraph, it is a boundary node.
for pred in G.predecessors(n):
if pred not in subgraph_nodes:
boundary_nodes.add(pred)
for succ in G.successors(n):
if succ not in subgraph_nodes:
boundary_nodes.add(succ)
return boundary_nodes
def add_predecessors(self, graph, subgraph, node):
# Skip nodes already in the subgraph.
if node in subgraph.G.nodes :
return
# Add current node.
# print(node)
subgraph.G.add_node(node)
# Collect and traverse all predecessors.
predecessors = list(graph.predecessors(node))
for predecessor in predecessors:
# Recursively traverse each predecessor's predecessors.
self.add_predecessors(graph, subgraph, predecessor)
pre_name = self.extract_name(predecessor.name)
node_name = self.extract_name(node.name)
subgraph.G.add_edge(predecessor, node, label = self.edge_dict[(pre_name.split(',')[-1],node_name.split(',')[-1])][0]) # Add edge.
# def split_graph(self, G, rule_function):
# # Split graph into subgraphs by the given rule.
# subgraphs = {}
# for node in list(G.nodes):
# tag = rule_function(node)
# if tag is not None:
# node_list = self.predecessor(node)
# print(node_list)
# for node in node_list:
# self.block_num = self.block_num + 1
# key = tag + "_" + str(self.block_num)
# subgraphs[key] = Subgraph(Graph = nx.DiGraph(),name = key)
# # print(list(G.predecessors(node)))
# self.add_predecessors(G, subgraphs[key], node)
# boundary_nodes = self.find_boundary_nodes(G, node, subgraphs[key].G.nodes)
# print(boundary_nodes)
# # Remove non-shared nodes from the original graph.
# for node in subgraphs[key].G.nodes:
# if not node in boundary_nodes: # Delete nodes referenced by only one subgraph.
# G.remove_node(node)
# print()
# subgraphs["BasicBlock_Remain"] = Subgraph(Graph = G,name = "BasicBlock_Remain")
# return subgraphs
# Updated splitting algorithm.
def split_graph(self, G, rule_function):
# Split graph into subgraphs by the given rule.
subgraphs = {}
visited_nodes = set() # Track processed nodes to avoid duplicates.
for node in list(G.nodes):
if node in visited_nodes:
continue # Skip processed nodes.
tag = rule_function(node) # Determine which subgraph the node belongs to.
if tag is not None:
self.block_num += 1
block_name = f"{tag}_{self.block_num}"
# Create a new subgraph.
subgraphs[block_name] = Subgraph(Graph=nx.DiGraph(), name=block_name)
# Add current node and its predecessors/successors.
self.add_predecessors_and_successors(
G, subgraphs[block_name], node, visited_nodes
)
# Find subgraph boundary nodes (inputs/outputs).
boundary_nodes = self.find_boundary_nodes(
G, node, subgraphs[block_name].G.nodes
)
print(f"Boundary nodes for {block_name}: {boundary_nodes}")
# Put remaining nodes into a separate subgraph.
subgraphs["BasicBlock_Remain"] = Subgraph(Graph=G, name="BasicBlock_Remain")
return subgraphs
def add_predecessors_and_successors(self, G, subgraph, node, visited_nodes):
# Traverse node and its predecessors/successors and add them to subgraph.
stack = [node]
while stack:
current = stack.pop()
if current not in visited_nodes:
subgraph.G.add_node(current, **G.nodes[current]) # Add to subgraph.
visited_nodes.add(current)
# Traverse predecessors.
for pred in G.predecessors(current):
label = self.edge_dict[(pred.name.split(',')[-1],current.name.split(',')[-1])]
subgraph.G.add_edge(pred, current,label=label)
# stack.append(pred)
# Traverse successors.
for succ in G.successors(current):
label = self.edge_dict[(current.name.split(',')[-1],succ.name.split(',')[-1])]
subgraph.G.add_edge(current, succ,label=label)
# stack.append(succ)
def visualize_subgraphs(self, subgraphs, outpath):
# Visualize each subgraph.
for key, subgraph in subgraphs.items(): # Use items() iteration.
os.makedirs(outpath+"/basicblock",exist_ok=True)
out_path = os.path.join(outpath+"/basicblock", key + ".dot")
self.show_graph(subgraph.G,out_path)
# def basic_block(self,outpath):
# G = self.dfg.copy()
# # remove_wires(G)
# # Define a rule function, e.g., group by the first letter of the node name.
# def rule_function(node):
# if node is None or str(node.name).strip() == "":
# return None # Or return a specific default name.
# if str(node.name).startswith("Cond"):
# return "BasicBlock" # Use Cond nodes as grouping criteria.
# # successors = self.successor(node)
# # if len(successors) == 1 and successors[0].name.startswith("Cond"):
# # self.block_num = self.block_num + 1
# # block_name = "BasicBlock" + str(self.block_num)
# # return block_name # Use Cond nodes as grouping criteria.
# return None
# subgraphs = self.split_graph(G, rule_function)
# self.visualize_subgraphs(subgraphs,outpath)
# return subgraphs
def basic_block(self,outpath):
G = self.dfg.copy()
# remove_wires(G)
# Define a rule function, e.g., group by the first letter of the node name.
def rule_function(node):
if node is None or str(node.name).strip() == "":
return None # Or return a specific default name.
# Part 2: operator-node grouping rule.
# Check if the node is an operator (e.g., Add, Mul).
divide_operators = ["ShiftLeft",
"ShiftRight",
"AshiftLeft",
"AshiftRight",
"LNot",
"And",
"Or",
"Not",
"BitAnd",
"BitOr",
"BitXor",
"BitNXor",
"URxor",
"URand",
"URor",
"URnand",
"URnor",
"URnxor",
"Cond", # cond is an operator too and can be included.
"Eq",
"Neq",
"Eeq",
"Neeq",
"Le",
"Ge",
"Lt",
"Gt",
"Add",
"Sub",
"Mul",
"Div",
"Mod",
"Power",
"Funcall" ] # Extend the operator list as needed.
for op in divide_operators:
if str(node.name).startswith(op):
#if str(node.name).startswith("Add"):
return "BasicBlock" # Use Cond nodes as grouping criteria.
# successors = self.successor(node)
# if len(successors) == 1 and successors[0].name.startswith("Cond"):
# self.block_num = self.block_num + 1
# block_name = "BasicBlock" + str(self.block_num)
# return block_name # Use Cond nodes as grouping criteria.
return None
subgraphs = self.split_graph(G, rule_function)
self.visualize_subgraphs(subgraphs,outpath)
return subgraphs
def Preprocessing(self):
self.case_function()
self.remove_isolated_nodes()
self.partassign_merge()
self.partassign_function()
self.remain_Idx()
# self.remove_wires()
self.node_name()
def show_basic_block_combine_graph(self, subgraphs = None, filename = None):
top_name = 'Combined'
with open (filename, 'w') as f:
line = "digraph {0} ".format(top_name)
line = line + "{\n"
f.write(line)
if subgraphs != None:
for key,subgraph in subgraphs.items():
line = " subgraph cluster_{0} ".format(subgraph.name)
line = line + "{\n"
f.write(line)
line = " label=\"{0}\";\n".format(subgraph.name)
f.write(line)
# Write node to graph file
for node in subgraph.G.nodes:
if not node:
break
node_name = re.sub(r'\.|\[|\]|\\', r'_', node.name)
if node.name in self.in_set:
line = " \"{0}\" [style=filled, color=yellow];\n".format(node_name)
elif node.name in self.out_set:
line = " \"{0}\" [style=filled, color=green];\n".format(node_name)
elif node.name in self.sigset_set:
line = " \"{0}\" [style=filled, color=orange];\n".format(node_name)
# elif node.name in self.seq_set:
# line = " {0} [style=filled, color=lightblue];\n".format(node_name)
elif node.name in self.wire_set:
line = " \"{0}\" [style=filled, color=black, fillcolor=white];\n".format(node_name)
elif node.name.startswith("Const"):
if node.name in self.label_set:
line = " \"{0}\" [style=filled, color=red];\n".format(node_name)
else:
line = " \"{0}\" [style=filled, color=grey];\n".format(node_name)
elif node.name in self.label_set:
line = " \"{0}\" [style=filled, color=red];\n".format(node_name)
elif node.name in self.comb_set:
line = " \"{0}\" [style=filled, color=pink];\n".format(node_name)
else:
line = " {0};\n".format(node_name)
f.write(line)
# # Write edge to graph file
# for vertice in subgraph.G.edges(data = True):
# if vertice:
# u = vertice[0]
# v = vertice[1]
# label = vertice[2]["label"]
# node1_name = re.sub(r'\.|\[|\]|\\', r'_', u.name)
# node2_name = re.sub(r'\.|\[|\]|\\', r'_', v.name)
# # if node1_name.startswith("Const"):
# # node1_name = "\"" + node1_name + "\""
# # if node2_name.startswith("Const"):
# # node2_name = "\"" + node2_name + "\""
# # pair = '{0} -> {1} [label=\"{2}\"]'.format(vertice, val, edge_id)
# # reverse the ast to CDFG
# pair = '\"{0}\" -> \"{1}\" [label=\"{2}\"]'.format(node1_name, node2_name, label)
# line = " {0};\n".format(pair)
# f.write(line)
f.write(" }\n")
# Write edge to graph file
for vertice in self.dfg.edges(data = True):
if vertice:
u = vertice[0]
v = vertice[1]
label = vertice[2]["label"]
node1_name = re.sub(r'\.|\[|\]|\\', r'_', u.name)
node2_name = re.sub(r'\.|\[|\]|\\', r'_', v.name)
# if node1_name.startswith("Const"):
# node1_name = "\"" + node1_name + "\""
# if node2_name.startswith("Const"):
# node2_name = "\"" + node2_name + "\""
# pair = '{0} -> {1} [label=\"{2}\"]'.format(vertice, val, edge_id)
# reverse the ast to CDFG
pair = '\"{0}\" -> \"{1}\" [label=\"{2}\"]'.format(node1_name, node2_name, label)
line = " {0};\n".format(pair)
f.write(line)
f.write("}\n")
def resolve_var_exp(self):
resolved = self.var_exp.copy()
def replace_in_value(value, resolved_dict):
# Traverse resolved_dict to perform replacements.
for key, replacement in resolved_dict.items():
if key in value:
# Wrap in parentheses to preserve precedence.
value = value.replace(key, f"{replacement}")
return value
while True:
progress = False
for key in list(resolved.keys()):
original_value = resolved[key]
resolved[key] = replace_in_value(original_value, resolved)
if resolved[key] != original_value:
progress = True
# No more progress means the maximal resolution is done.
if not progress:
break
return resolved
# def write_node_edge_to_dot(self,G):
def show_graph(self, G = None, filename = None):
# self.get_stat()
print('----- Writting Graph Visialization File -----')
# outfile_path = "./png/"
# outfile = outfile_path+"AST_graph.dot"
top_name = 'test'
# print(self.dfg.nodes)
if G == None:
G = self.dfg
with open (filename, 'w') as f:
line = "digraph {0} ".format(top_name)
line = line + "{\n"
f.write(line)
reg_set = set()
# Write node to graph file
for node in G.nodes:
if not node:
break
node_name = re.sub(r'\.|\[|\]|\\', r'_', node.name)
if node.name in self.in_set:
line = " \"{0}\" [style=filled, color=yellow];\n".format(node_name)
elif node.name in self.out_set:
line = " \"{0}\" [style=filled, color=green];\n".format(node_name)
elif node.name in self.sigset_set:
line = " \"{0}\" [style=filled, color=orange];\n".format(node_name)
# elif node.name in self.seq_set:
# line = " {0} [style=filled, color=lightblue];\n".format(node_name)
elif node.name in self.wire_set:
line = " \"{0}\" [style=filled, color=black, fillcolor=white];\n".format(node_name)
elif node.name.startswith("Const"):
if node.name in self.label_set:
line = " \"{0}\" [style=filled, color=red];\n".format(node_name)
else:
line = " \"{0}\" [style=filled, color=grey];\n".format(node_name)
elif node.name in self.label_set:
line = " \"{0}\" [style=filled, color=red];\n".format(node_name)
elif node.name in self.comb_set:
line = " \"{0}\" [style=filled, color=pink];\n".format(node_name)
else:
line = " {0};\n".format(node_name)
f.write(line)
# Write edge to graph file
for vertice in G.edges(data = True):
if vertice:
u = vertice[0]
v = vertice[1]
label = vertice[2]["label"]
node1_name = re.sub(r'\.|\[|\]|\\', r'_', u.name)
node2_name = re.sub(r'\.|\[|\]|\\', r'_', v.name)
# if node1_name.startswith("Const"):
# node1_name = "\"" + node1_name + "\""
# if node2_name.startswith("Const"):
# node2_name = "\"" + node2_name + "\""
# pair = '{0} -> {1} [label=\"{2}\"]'.format(vertice, val, edge_id)
# reverse the ast to CDFG
pair = '\"{0}\" -> \"{1}\" [label=\"{2}\"]'.format(node1_name, node2_name, label)
line = " {0};\n".format(pair)
f.write(line)
f.write("}\n")
print('Finish!\n')
def Operator_simple(self, operator_name):
if operator_name.startswith("Add"):
return "+"
elif operator_name.startswith("Sub"):
return "-"
elif operator_name.startswith("Mul"):
return "*"
elif operator_name.startswith("Div"):
return "/"
elif operator_name.startswith("Mod"):
return "%"
elif operator_name.startswith("Eq"):
return "=="
elif operator_name.startswith("Neq"):
return "!="
elif operator_name.startswith("Gt"):
return ">"
elif operator_name.startswith("Lt"):
return "<"
elif operator_name.startswith("Ge"):
return ">="
elif operator_name.startswith("Le"):
return "<="
elif operator_name.startswith("Eeq"):
return "==="
elif operator_name.startswith("Neeq"):
return "!=="
elif operator_name.startswith("And"):
return "&&"
elif operator_name.startswith("BitAnd"):
return "&"
elif operator_name.startswith("Or"):
return "||"
elif operator_name.startswith("BitOr"):
return "|"
elif operator_name.startswith("BitXor"):
return "^"
elif operator_name.startswith("BitNXor"):
return "~^"
elif operator_name.startswith("Not"):
return "~"
elif operator_name.startswith("ShiftLeft"):
return "<<"
elif operator_name.startswith("ShiftRight"):
return ">>"
elif operator_name.startswith("AshiftLeft"):
return "<<<"
elif operator_name.startswith("AshiftRight"):
return ">>>"
elif operator_name.startswith("LogicAnd"):
return "&&"
elif operator_name.startswith("LogicOr"):
return "||"
elif operator_name.startswith("LNot"):
return "!"
elif operator_name.startswith("URxor"):
return "^"
elif operator_name.startswith("URand"):
return "&"
elif operator_name.startswith("URor"):
return "|"
elif operator_name.startswith("URnand"):
return "~&"
elif operator_name.startswith("URnor"):
return "~|"
# If no match found, return None or raise an exception as appropriate
return None
def variable_exp(self,node_name):
print(self.node_dict[node_name])
pre_list = self.predecessor(self.node_dict[node_name])
if __name__ == "__main__":
# node1 = AnyNode(name = "parent", parent = None, level = 6)
# tnode1 = AnyNode(name = "sss",parent = node1, level = 7)
# tnode1 = copy_without_level(tnode1)
# print(tnode1.parent)
# exit()
data = read_json_file("./data/75_ast_clean.json")
ast = build_tree_from_json(data)
# Preprocess: add suffix to identical keywords.
pre(ast)
# Extract CDFG; dfg is the extracted graph.
dfg_extractor = DFGExtractor()
dfg_extractor.visit(ast)
dfg_extractor.Preprocessing()
dfg_extractor.show_graph(filename = "rrrrr.dot")
exit()
Subgraphs = dfg_extractor.basic_block(".")
print((Subgraphs))
dfg_extractor.show_basic_block_combine_graph(Subgraphs,"control_example_combined")
# output_directory = "."
# for key, subgraph in subgraphs.items():
# out_path = os.path.join(output_directory, key+"_cdfg.dot")
# sub_dfg_extractor = DFGExtractor(subgraph.G)
# sub_dfg_extractor.show_graph(out_path)
dfg = dfg_extractor.dfg
# print(RenderTree(ast))
# Extract DFG.
# dfg = extract_dfg_from_ast(ast)
input_directory = "./data"
output_directory = "./png"
# input_path = os.path.join(input_directory, file_name)
out_path1 = os.path.join(output_directory, "comparator_ast_clean_cdfg.dot")
out_path2 = os.path.join(output_directory, "comparator_ast_clean_cdfg.png")
# print(dfg.nodes)
# print(dfg.edges(data=True))
dfg_extractor.show_graph(out_path1)
# for edg in dfg.edges :
# print(edg[0])
out_path = "./png"
# print(dfg_extractor.out_set)
# print(dfg_extractor.node_dict)
os.system("dot.exe -Tpng {} -o {}".format(out_path1,out_path2))
thirdparty/RTL2CDFG/v2cdfg/src/ast_from_json.py 0 → 100755
from anytree import NodeMixin,AnyNode,RenderTree
from anytree.importer import JsonImporter
import json
def read_json_file(file_path):
with open(file_path, 'r') as file:
data = json.load(file)
return data
def build_tree_from_json(data, level = 1, parent = None):
operator = data['name']
node = AnyNode(name = operator,level = level, parent = parent)
for child_data in data.get('children', []):
child_node = build_tree_from_json(child_data,level = level+1, parent = node)
return node
thirdparty/RTL2CDFG/v2cdfg/src/ast_pre.py 0 → 100755
from ast_from_json import *
import os
import sys
import subprocess
from anytree.exporter import JsonExporter, UniqueDotExporter
from anytree import AnyNode
# Unary operators.
operator1list = ["LNot", "Not", "URxor", "URand", "URor", "URnand", "URnor"]
# Binary operators.
operator2list = [
"Lt",
"Le",
"Gt",
"Ge",
"Add",
"Sub",
"Mul",
"Div",
"Mod",
"ShiftLeft",
"ShiftRight",
"AshiftLeft",
"AshiftRight",
"And",
"Or",
"Eq",
"Neq",
"Eeq",
"Neeq",
"BitAnd",
"BitOr",
"BitXor",
"BitNXor",
]
original_stdout = sys.stdout
operator_dict = {}
for operator in operator1list:
operator_dict[operator] = 0
for operator in operator2list:
operator_dict[operator] = 0
operator_dict["Lconc"] = 0
operator_dict["Cond"] = 0
operator_dict["Cond_If"] = 0
operator_dict["Idx"] = 0
operator_dict["Conc"] = 0
operator_dict["Casez"] = 0
operator_dict["PartAssign"] = 0
var_exp = {}
Idx_dict = {}
Idx_list = []
func_scope = False
def identical_Idx(node1, node2):
# print(node1.name + node2.name)
if node1.name.startswith("Idx") and node2.name.startswith("Idx"):
if len(node1.children) != len(node2.children):
return False
for index, subnode1 in enumerate(node1.children):
if index < len(node2.children):
# print(subnode1)
# print(node2.children[index])
if not identical_Idx(subnode1, node2.children[index]):
return False
else:
return False
else:
if node1.name != node2.name:
return False
else:
for index, subnode1 in enumerate(node1.children):
if node2.children[index]:
if not identical_Idx(subnode1, node2.children[index]):
return False
else:
return False
return True
def check_node_in_nodelist(node, node_dict):
for key, value in node_dict.items():
if identical_Idx(node, value):
return True, key
return False, None
def pre(ast):
if ast.name == "Case":
ast.name = "Casez"
# yanlw 26/8/2024
if ast.name == "TpConcList" and ast.parent.name.startswith("Lconc"):
num_ele = len(ast.children)
for tnode in ast.children:
if tnode.children[0].name == "Idx":
operator_dict["PartAssign"] += 1
tnode.children[0].name = "PartAssign_" + str(operator_dict["PartAssign"])
# print(f"partassign1: {tnode.children[0].name}{tnode.children[0]}")
num_ele -= 1
# Two cases: predecessor is Lname or predecessor is Lconc (num_partassign is non-zero).
if ast.name == "Idx" and ast.parent.name == "Lname":
operator_dict["PartAssign"] += 1
ast.name = "PartAssign_" + str(operator_dict["PartAssign"])
# print(f"partassign2: {ast.name}")
if ast.name == "If":
ast.name = "Cond_If"
if (
ast.name in operator2list
or ast.name in operator1list
or ast.name == "Cond"
or ast.name == "Idx"
or ast.name == "Conc"
or ast.name == "Casez"
or ast.name == "Lconc"
or ast.name == "Cond_If"
):
if ast.name == "Idx":
if Idx_dict and not ast.children[0].name == 'b':
result, index = check_node_in_nodelist(ast, Idx_dict)
if result:
# print("exit a identical Idx")
ast.name = Idx_dict[index].name
else:
operator_dict[ast.name] = operator_dict[ast.name] + 1
ast.name = ast.name + "_" + str(operator_dict[ast.name])
else:
operator_dict[ast.name] = operator_dict[ast.name] + 1
ast.name = ast.name + "_" + str(operator_dict[ast.name])
else:
operator_dict[ast.name] = operator_dict[ast.name] + 1
ast.name = ast.name + "_" + str(operator_dict[ast.name])
if ast.name.startswith("Idx"):
Idx_dict[ast.name] = ast
# if ast.name == "Lconc":
# ast.name = "Lname"
# tnode = AnyNode(name = "Conc", level = ast.level+1, parent = None)
# if ast.children:
# for subnode in ast.children:
# subnode.parent = tnode
# tnode.parent = ast
# extend var_exp
if ast.name == "Num":
node_name = "Constant_"
if ast.children[0]:
node_name = node_name + ast.children[0].name + "'"
if len(ast.children) > 1 and ast.children[1]:
if (
ast.children[1].name == "Hex"
or ast.children[1].name == "Bin"
or ast.children[1].name == "Dec"
or ast.children[1].name == "Oct"
):
node_name = node_name + ast.children[1].name[0]
if ast.children[1].children[0]:
node_name = node_name + ast.children[1].children[0].name
node_name = "Const," + ast.children[0].name + "," + node_name
var_exp[node_name] = node_name.split(',')[-1].replace("Constant_", "")
print(var_exp[node_name])
if ast.children:
for subnode in ast.children:
pre(subnode)
def pre_ast2json(ast, filename):
input_directory = "./data"
os.makedirs(input_directory, exist_ok=True)
input_path = os.path.join(input_directory, filename)
with open(input_path, 'w') as f:
sys.stdout = f
exporter = JsonExporter(indent=2, sort_keys=True)
print(exporter.export(ast))
sys.stdout = original_stdout
print("Preprocessed AST JSON conversion completed.")
def pre_ast2png(ast, filename):
name, ext = os.path.splitext(filename)
input_directory = "./data"
output_directory = "./ast_png"
os.makedirs(input_directory, exist_ok=True)
input_path = os.path.join(input_directory, name + ".json")
dot_output_path = os.path.join(output_directory, name + ".dot")
output_path = os.path.join(output_directory, name + ".svg")
# graphviz needs to be installed for the next line!
UniqueDotExporter(ast).to_dotfile(dot_output_path)
subprocess.check_call(['dot', dot_output_path, '-T', 'svg', '-o', output_path])
sys.stdout = original_stdout
print("Preprocessed AST PNG conversion completed.")
if __name__ == "__main__":
data = read_json_file("./data/75_ast_clean.json")
ast = build_tree_from_json(data)
pre(ast)
pre_ast2json(ast, "75_ast_clean.json")
pre_ast2png(ast, "75_ast_clean.json")
exit()
thirdparty/RTL2CDFG/v2cdfg/src/auto_run.py 0 → 100755
import argparse
import subprocess
import os
from ast2cdfg import *
def arguments():
parser = argparse.ArgumentParser(description="Example program for CLI arguments.")
parser.add_argument('filename', type=str, help="File name to process.", nargs='?')
parser.add_argument('-d', '--divide', action='store_true', help="Split basic blocks.")
return parser.parse_args()
if __name__ == "__main__":
args = arguments()
file_name = args.filename
name, ext = os.path.splitext(file_name)
# Read input file.
input_directory = "./tmp/ast"
output_directory = "./cdfg/"
# Create directory.
# output_directory = "../data/"+name
os.makedirs(output_directory, exist_ok=True)
input_path = os.path.join(input_directory, file_name)
out_path1 = os.path.join(output_directory, name + "_cdfg.dot")
out_path2 = os.path.join(output_directory, name + "_cdfg.png")
out_path3 = os.path.join(output_directory, name + "_basic_block_combined.dot")
data = read_json_file(input_path)
ast = build_tree_from_json(data)
# Preprocess: add suffix to identical keywords.
pre(ast)
# Extract CDFG; dfg is the extracted graph.
dfg_extractor = DFGExtractor()
dfg_extractor.visit(ast)
dfg_extractor.Preprocessing()
dfg_extractor.show_graph(filename=out_path1)
dfg = dfg_extractor.dfg
# print(dfg_extractor.resolve_var_exp())
# print(dfg_extractor.node_dict.keys())
# print(dfg.nodes)
# print(dfg.edges)
if args.divide:
Subgraphs = dfg_extractor.basic_block(outpath=output_directory)
dfg_extractor.show_basic_block_combine_graph(Subgraphs, out_path3)
# CDFG visualization.
# dot_path = "/mnt/c/ProgramFiles(x86)/Graphviz2.38/bin"
# os.system("dot -Tpng {} -o {}".format(out_path1,out_path2))
thirdparty/RTL2CDFG/v2cdfg/src/auto_yosys.py 0 → 100644
import argparse
import os
from clean_ast import *
def arguments():
parser = argparse.ArgumentParser(description="Example program for CLI arguments.")
parser.add_argument('filename', type=str, help="File name to process.", nargs='?')
return parser.parse_args()
if __name__ == "__main__":
args = arguments()
file_name = args.filename
print(args)
name, ext = os.path.splitext(file_name)
input_file = name + ".v"
output_file = name + "_ast.v"
ast_clean_file = name + "_ast_clean.v"
input_directory = "../verilog_data" # "./yosys_data_1000"
output_directory = "./tmp/yosys_output_data"
input_path = os.path.join(input_directory, input_file)
out_path = os.path.join(output_directory, output_file)
# Open source and target files.
with open(input_path, 'r') as source_file, open("test.v", 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
# yosys_directory = "/home/wangyipeng/oss-cad-suite/bin/"
# os.system("yosys run_ast.ys".format(yosys_directory))
os.system("yosys run_ast.ys")
# Open source and target files.
with open("test_ast.v", 'r') as source_file, open(out_path, 'w') as target_file:
# Read source file content.
content = source_file.read()
# Write content to target file.
target_file.write(content)
print("Content written to target file successfully.")
ast_clean_directory = "./tmp/yosys_output_data_clean"
ast_clean_path = os.path.join(ast_clean_directory, ast_clean_file)
vlg_clean(out_path, ast_clean_path)
# test
# vlg_clean("./test.v", ast_clean_path)
thirdparty/RTL2CDFG/v2cdfg/src/clean_ast.py 0 → 100755
import json, os, re, time
def vlg_clean(file, file_clean):
# file_tmp = file
# os.system("cp {0} ./{1}".format(file, file_tmp))
# os.remove(file)
with open(file, "r") as f:
lines = f.readlines()
with open(file_clean, "w+") as f_tmp:
for line in lines:
line = re.sub(r'\(\*(.*)\*\)', '', line)
if line.strip():
f_tmp.writelines(line)
# os.remove(file_tmp)
if __name__ == '__main__':
design_name = "test"
cmd = 'ast'
file_dir = f"./{design_name}_{cmd}.v"
file_clean_dir = f"./{design_name}_{cmd}_clean.v"
vlg_clean(file_dir, file_clean_dir)
thirdparty/RTL2CDFG/v2cdfg/src/structures.py 0 → 100644
class Subgraph:
def __init__(self, graph, name) -> None:
self.G = graph
self.name = name # Subgraph name.
self.successors = [] # Successor subgraphs.
self.predecessors = [] # Predecessor subgraphs.
def add_successor(self, successor_subgraph):
"""Add a successor subgraph."""
if successor_subgraph not in self.successors:
self.successors.append(successor_subgraph)
successor_subgraph.add_predecessor(self) # Keep predecessor list in sync.
def add_predecessor(self, predecessor_subgraph):
"""Add a predecessor subgraph."""
if predecessor_subgraph not in self.predecessors:
self.predecessors.append(predecessor_subgraph)
def __repr__(self):
return f"Subgraph(name={self.name}, successors={len(self.successors)}, predecessors={len(self.predecessors)})"
def __hash__(self):
"""Generate a unique hash from the subgraph name."""
return hash(self.name)
def __eq__(self, other):
"""Compare two subgraphs for equality."""
if isinstance(other, Subgraph):
return self.name == other.name
return False
thirdparty/RTL2CDFG/v2cdfg/src/tree.py 0 → 100755
# -*- coding: utf-8 -*-
# Build a tree from S-expression files and output AST as JSON.
from anytree import NodeMixin, AnyNode, RenderTree
from anytree.exporter import JsonExporter, UniqueDotExporter
from anytree.importer import JsonImporter
import sys
import os
import argparse
import json
from io import StringIO
from anytree.exporter import DotExporter
import subprocess
original_stdout = sys.stdout
def arguments():
parser = argparse.ArgumentParser(description="Example program for CLI arguments.")
parser.add_argument('-r', '--reduced', action='store_true', help="Use reduced syntax tree.")
parser.add_argument('-j', '--json', action='store_true', help="Generate JSON file.")
parser.add_argument('-p', '--png', action='store_true', help="Generate PNG file (JSON required).")
parser.add_argument('filename', type=str, help="File name to process.", nargs='?')
parser.add_argument('-i', '--input_directory', type=str, default='.', help="Input directory.")
parser.add_argument('-o', '--output_directory', type=str, default='.', help="Output directory.")
parser.add_argument('-v', '--verify', action='store_true', help="Read JSON file and verify no loss.")
parser.add_argument('-e', '--exist', action='store_true', help="Check if *.json already exists in output.")
return parser.parse_args()
# Read an S-expression file (e.g., comparator.txt) and build the AST.
# If reduced is true, build a reduced tree; otherwise build the full tree.
def read_file(file_name, red):
with open(file_name, 'r') as file:
content = file.read()
#print(content)
tag = -1
while content[tag] != ')':
tag = tag - 1
# Slice from index 1 to the second-to-last character (strip outer parentheses).
sexpr = content[1:tag]
#print(sexpr)
# Tokenize (strip inner parentheses of the S-expression).
#tokens = tokenize(sexpr)
#print(tokens)
# Parse S-expression.
parsed_expr = parse_sexpr(sexpr)
#print("Parsed S-Expression:", parsed_expr)
# Build AST.
if red:
ast = build_reduced_ast(parsed_expr)
ast_walker_reduce(ast)
else:
ast = build_complete_ast(parsed_expr)
return ast
# Process tokenized S-expression into a nested list.
def parse_sexpr(expr):
tokens = tokenize(expr)
LL =[]
while tokens:
LL.append(read_from_tokens(tokens))
return LL
# Tokenize (strip inner parentheses of the S-expression).
def tokenize(expr):
# Add spaces to ensure parentheses are separated correctly.
expr = expr.replace('(', ' ( ').replace(')', ' ) ')
return expr.split()
# Token processing algorithm: append contents inside parentheses to L.
def read_from_tokens(tokens):
if not tokens:
raise SyntaxError('Unexpected EOF while reading')
token = tokens.pop(0)
if token == '(':
L = []
while tokens and tokens[0] != ')':
L.append(read_from_tokens(tokens))
if tokens:
tokens.pop(0) # pop off ')'
return L
elif token == ')':
raise SyntaxError('Unexpected )')
else:
return atom(token)
# Parse as numeric or symbol.
def atom(token):
try:
return int(token)
except ValueError:
try:
return float(token)
except ValueError:
return str(token)
# Read operator list to help validate JSON.
operatorlist = []
with open("operatorlist.txt", "r+") as file:
content = file.read()
operatorlist = content.split(",")
operatorlist = list(set(operatorlist))
tpvartplist = []
# Syntax tree construction algorithm.
def build_complete_ast(parsed_expr,parent = None):
if isinstance(parsed_expr, list):
#print(parsed_expr)
operator = str(parsed_expr.pop(0))
# Maintain operator list.
if not operator in operatorlist and not operator.isdigit() and not len(operator) == 1:
operatorlist.append(operator)
# Combine module/task name into one node, e.g., "TpTask fullAdder".
if operator == "TpTask":
taskname = parsed_expr.pop(0)
operator = operator + " " + taskname
node = AnyNode(name = str(operator),parent = parent)
for sub_expr in parsed_expr:
child_node = build_complete_ast(sub_expr,parent = node)
return node
else:
nodename = str(parsed_expr)
nodename = nodename.replace("\n","").replace('"', '')
nodename = nodename.replace("\\","")#.replace("\\", "")
return AnyNode(name = nodename,parent = parent)
def build_reduced_ast(parsed_expr,parent = None):
if isinstance(parsed_expr, list):
# print(parsed_expr)
operator = str(parsed_expr.pop(0))
# Maintain operator list.
if not operator in operatorlist and not operator.isdigit() and not len(operator) == 1:
operatorlist.append(operator)
# Combine module/task name into one node, e.g., "TpTask fullAdder".
if operator == "TpTask":
taskname = parsed_expr.pop(0)
operator = operator + " " + taskname
# Drop Atom nodes.
if operator == "Atom" or operator == "Sym" or operator == "Parameter" or operator == "Assign" or operator == "Port" or operator == "Clist":
build_reduced_ast(parsed_expr[0], parent=parent)
else:
if parsed_expr:
if operator == "sharp":
operator = "TpVarTplist"
operatorlist.append("TpVarTplist")
if operator == "Svar":
operator = "Var"
operatorlist.append("Var")
node = AnyNode(name=str(operator), parent=parent)
# Add condition to if.
if operator == "If":
lst = ['TrueBlock']
lst.append(parsed_expr[1])
parsed_expr[1] = lst
lst = ['FalseBlock']
lst.append(parsed_expr[2])
parsed_expr[2] = lst
if operator == "Ge" or operator == "Le" or operator == "Lt" or operator == "Gt" or operator == "Sub" or operator == "Mod" or operator == "Div" or operator == "Add" or operator == "Mul" or operator == "And" or operator == "Or" or operator == "BitAnd" or operator == "BitOr" or operator == "BitXor" or operator == "Eq" or operator == "Neq" or operator == "Eeq" or operator == "Neeq" or operator == "ShiftRight" or operator == "ShiftLeft" or operator == "AshiftLeft" or operator == "AshiftRight" or operator == "Power" or operator == "BitNXor":
lst = ['Left']
lst.append(parsed_expr[0])
parsed_expr[0] = lst
lst = ['Right']
lst.append(parsed_expr[1])
parsed_expr[1] = lst
# Add condition to '?' operator.
if operator == "Cond":
lst = ['TrueBlock']
lst.append(parsed_expr[1])
parsed_expr[1] = lst
lst = ['FalseBlock']
lst.append(parsed_expr[2])
parsed_expr[2] = lst
if operator == "TpVarTp":
tpvartplist.append(parsed_expr[0])
for sub_expr in parsed_expr:
child_node = build_reduced_ast(sub_expr, parent=node)
return node
else:
()
else:
nodename = str(parsed_expr)
nodename = nodename.replace("\n","").replace('"', '')
nodename = nodename.replace("\\","")#.replace("\\", "")
#print(nodename)
# Drop symbols and delays.
if nodename == "NoDelay" or nodename == "false" or nodename == "NoDE" or nodename == "NullExp" or nodename == "Rng0" or nodename == "NullPara" or nodename == "NoPathDelay" or nodename == "NoCond" or nodename == "Nullnet" or nodename == "NoElse" or nodename == "EmptyStmt" or nodename == "null":
()
else:
return AnyNode(name=nodename, parent=parent)
def read_json_file(file_path):
with open(file_path, 'r') as file:
data = json.load(file)
return data
def tree_to_list(node):
if not node.children:
for operator in operatorlist:
if node.name == operator:
return [node.name]
return node.name
else:
result = [node.name]
for child in node.children:
result.append(tree_to_list(child))
return result
def list_to_s_expression(lst):
if isinstance(lst, list):
return '(' + ' '.join(list_to_s_expression(el) for el in lst) + ')'
else:
return str(lst)
def build_tree_from_json(data, level=1, parent=None):
operator = data['name']
node = AnyNode(name=operator, level=level, parent=parent)
for child_data in data.get('children', []):
child_node = build_tree_from_json(child_data, level=level + 1, parent=node)
return node
# Insert a node, e.g., a-children[ b,c ] -> insert_node(a,'d') -> a-children[ d-children[ b,c ] ]
def insert_node(node, name):
i_node = AnyNode(name=name, parent=None)
if node.children:
for subnode in node.children:
subnode.parent = i_node
i_node.parent = node
def delete_subtree(node, index):
lst = list(node.parent.children)
del lst[index]
tple = tuple(lst)
node.parent.children = tple
def delete_node(node, index):
if node.children:
lst = list(node.parent.children)
index1 = 0
for subnode in node.children:
subnode.parent = node.parent
lst.insert(index + index1, subnode)
index1 = index1 + 1
tple = tuple(lst)
node.parent.children = tple
else:
delete_subtree(node, index)
# Prune tpvar nodes.
def reduce_strategy_tpvar(node):
index = 0
if node.parent is not None and node.parent.children:
for subnode in node.parent.children:
if subnode.name == node.name:
delete_node(subnode, index)
break
else:
index = index + 1
# Prune duplicate input/output in sigset.
def reduce_strategy_sigset(node):
index = 0
if node.parent.name == "TpFunBody":
return
if node.children:
for subnode in node.children:
if subnode.name == "Input" or subnode.name == "Output":
delete_subtree(subnode, index)
else:
index = index + 1
# Drop leaf operator nodes with no parameters.
def reduce_strategy_leaf(node):
index = 0
if node.parent is not None and node.parent.children:
for subnode in node.parent.children:
if subnode.name == node.name:
delete_subtree(subnode, index)
else:
index = index + 1
def reduce_strategy_NullExp(node):
if node.name == "NullExp":
()
def reduce_strategy_RngC(node):
if node.parent.name == "Idx":
return
if node.children[0].children[0].name == '0' and node.children[1].children[0].name == '0':
index = 0
for subnode in node.parent.children:
if subnode == node:
break
else:
index = index + 1
delete_subtree(node, index)
def ast_walker_reduce(node):
# Traverse and simplify nodes; add more rules here as needed.
if node.name == "Genvar":
node.children = node.children[0].children
if node.name == "TpVar":
reduce_strategy_tpvar(node)
if node.name == "RngC":
reduce_strategy_RngC(node)
if node.name == "sigset":
reduce_strategy_sigset(node)
if not node.children and node.name in operatorlist and not node.name in tpvartplist and not node.name.isdigit() and not len(node.name) == 1:
if node.parent and not node.parent.name == "Strg" and not node.parent.name == "Pstr" and not node.parent.name == "PathVar" and not node.parent.name == "Define" and not node.parent.name == "tpBlkLbl" and not node.parent.name == "Var":
reduce_strategy_leaf(node)
if node.children:
for child in node.children:
ast_walker_reduce(child)
# Main: read the S-expression file (e.g., comparator.txt) and output JSON/PNG.
# comparator.json: intermediate AST form.
# comparator.png: visualized AST structure.
if __name__ == "__main__":
if len(sys.argv) < 2:
print("Usage: python readfile.py <filename>")
else:
args = arguments()
file_name = args.filename
name, ext = os.path.splitext(file_name)
input_path = os.path.join(args.input_directory, file_name)
# Ensure directory exists.
os.makedirs(args.input_directory, exist_ok=True)
if args.verify:
data = read_json_file(input_path)
ast = build_tree_from_json(data)
#print(operatorlist)
# exporter = JsonExporter(indent=2, sort_keys=True)
# data = exporter.export(ast)
# importer = JsonImporter()
# root = importer.import_(data)
# UniqueDotExporter(root).to_picture("test.png")
# exit()
list1 = tree_to_list(ast)
str1 = list_to_s_expression(list1).replace(" ", "").replace("\n", "")
# Only the parts that do not affect the tree still lack parentheses.
with open(name + ".s", 'r') as file:
str2 = file.read().replace(" ", "").replace("\n", "")
print("S-expression reconstructed from JSON:\n" + repr(str1))
print("Original S-expression:\n" + repr(str2))
if str1 == str2:
print("Verification passed")
else:
print("Verification failed")
else:
output_file_1 = name + ".json"
dot_file = name + ".dot"
output_file_2 = name + ".svg"
output_file_3 = name + ".txt"
# Build full file paths.
output_path1 = os.path.join(args.output_directory , output_file_1)
output_path2 = os.path.join(args.output_directory , output_file_2)
output_path3 = os.path.join(args.output_directory , output_file_3)
output_path4 = os.path.join(args.output_directory , dot_file)
# Ensure directory exists.
if args.exist:
if os.path.exists(output_path1):
print(f"File '{output_path1}' exists in directory '{args.output_directory}'.")
exit()
else:
()
os.makedirs(args.output_directory, exist_ok=True)
ast = read_file(input_path,args.reduced)
with open("operatorlist.txt", "w+") as file:
operatorlist = list(set(operatorlist))
for operator in operatorlist:
file.write(str(operator) + ',')
# print("Filename without extension: " + name)
# with open(output_path3,'w') as txtfile:
# sys.stdout = txtfile
# print(RenderTree(ast))
if args.json:
with open(output_path1, 'w') as f:
sys.stdout = f
exporter = JsonExporter(indent=2, sort_keys=True)
print(exporter.export(ast))
sys.stdout = original_stdout
print("JSON file generated.")
if args.png:
importer = JsonImporter()
with open(output_path1, 'r') as file:
root = importer.read(file)
# graphviz needs to be installed for the next line!
# UniqueDotExporter(root).to_picture(output_path2)
# UniqueDotExporter(root).to_dotfile(output_path4)
# subprocess.check_call(['dot', output_path4, '-T', 'png', '-o', output_path2])
UniqueDotExporter(root).to_dotfile(output_path4)
# subprocess.check_call(['dot', output_path4, '-T', 'svg', '-o', output_path2])
sys.stdout = original_stdout
print("PNG file generated.")
thirdparty/RTL2CDFG/v2cdfg/test.v 0 → 100644
module soc_design_JTAG_sim_scfifo_r (
clk,
fifo_rd,
rst_n,
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
always @(posedge clk)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
endmodule
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/test_ast.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
(* src = "./test.v:1.1-49.10" *)
module soc_design_JTAG_sim_scfifo_r(clk, fifo_rd, rst_n, fifo_EF, fifo_rdata, rfifo_full, rfifo_used);
(* src = "./test.v:26.1-41.4" *)
wire [31:0] _00_;
(* src = "./test.v:26.1-41.4" *)
wire _01_;
wire [31:0] _02_;
(* src = "./test.v:37.25-37.42" *)
wire [31:0] _03_;
(* src = "./test.v:44.24-44.57" *)
(* unused_bits = "6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *)
wire [31:0] _04_;
(* src = "./test.v:17.18-17.28" *)
reg [31:0] bytes_left;
(* src = "./test.v:14.18-14.21" *)
input clk;
wire clk;
(* src = "./test.v:10.18-10.25" *)
output fifo_EF;
wire fifo_EF;
(* src = "./test.v:15.18-15.25" *)
input fifo_rd;
wire fifo_rd;
(* src = "./test.v:19.18-19.27" *)
reg fifo_rd_d;
(* src = "./test.v:11.18-11.28" *)
output [7:0] fifo_rdata;
wire [7:0] fifo_rdata;
(* src = "./test.v:21.18-21.25" *)
wire new_rom;
(* src = "./test.v:22.18-22.27" *)
wire [31:0] num_bytes;
(* src = "./test.v:23.18-23.31" *)
(* unused_bits = "6" *)
wire [6:0] rfifo_entries;
(* src = "./test.v:12.18-12.28" *)
output rfifo_full;
wire rfifo_full;
(* src = "./test.v:13.18-13.28" *)
output [5:0] rfifo_used;
wire [5:0] rfifo_used;
(* src = "./test.v:16.18-16.23" *)
input rst_n;
wire rst_n;
assign fifo_EF = ! (* src = "./test.v:42.18-42.37" *) bytes_left;
assign rfifo_full = bytes_left > (* src = "./test.v:43.21-43.39" *) 7'h40;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
bytes_left <= _00_;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
fifo_rd_d <= _01_;
assign _02_ = fifo_rd_d ? (* src = "./test.v:36.11-36.20|./test.v:36.7-37.43" *) _03_ : bytes_left;
assign _00_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) _02_ : 32'd0;
assign _01_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) fifo_rd : 1'h0;
assign _03_ = bytes_left - (* src = "./test.v:37.25-37.42" *) 1'h1;
assign { _04_[31:7], rfifo_entries[6], rfifo_used } = rfifo_full ? (* src = "./test.v:44.24-44.57" *) 32'd64 : bytes_left;
assign _04_[6:0] = { rfifo_entries[6], rfifo_used };
assign fifo_rdata = 8'h00;
assign new_rom = 1'h0;
assign num_bytes = 32'd0;
assign rfifo_entries[5:0] = rfifo_used;
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/Led_ast_clean.dot 0 → 100644
digraph tree {
"0x0" [label="TpProg"];
"0x1" [label="TpModule"];
"0x2" [label="TpTask led_chaser"];
"0x3" [label="paras"];
"0x4" [label="TpSigDeclBody"];
"0x5" [label="TpVarTplist"];
"0x6" [label="TpVarTp"];
"0x7" [label="clk"];
"0x8" [label="TpVarTp"];
"0x9" [label="rst"];
"0xa" [label="TpVarTp"];
"0xb" [label="led"];
"0xc" [label="ilists"];
"0xd" [label="TpSigDeclBody"];
"0xe" [label="TpVarTplist"];
"0xf" [label="TpVarTp"];
"0x10" [label="clk"];
"0x11" [label="TpSigDeclBody"];
"0x12" [label="TpVarTplist"];
"0x13" [label="TpVarTp"];
"0x14" [label="rst"];
"0x15" [label="olists"];
"0x16" [label="TpSigDeclBody"];
"0x17" [label="RngC"];
"0x18" [label="Int"];
"0x19" [label="7"];
"0x1a" [label="Int"];
"0x1b" [label="0"];
"0x1c" [label="TpVarTplist"];
"0x1d" [label="TpVarTp"];
"0x1e" [label="led"];
"0x1f" [label="sigset"];
"0x20" [label="Wire"];
"0x21" [label="TpSigDeclBody"];
"0x22" [label="RngC"];
"0x23" [label="Int"];
"0x24" [label="7"];
"0x25" [label="Int"];
"0x26" [label="0"];
"0x27" [label="TpVarTplist"];
"0x28" [label="TpVarTp"];
"0x29" [label="_0_"];
"0x2a" [label="Wire"];
"0x2b" [label="TpSigDeclBody"];
"0x2c" [label="TpVarTplist"];
"0x2d" [label="TpVarTp"];
"0x2e" [label="clk"];
"0x2f" [label="Reg"];
"0x30" [label="TpSigDeclBody"];
"0x31" [label="RngC"];
"0x32" [label="Int"];
"0x33" [label="7"];
"0x34" [label="Int"];
"0x35" [label="0"];
"0x36" [label="TpVarTplist"];
"0x37" [label="TpVarTp"];
"0x38" [label="led"];
"0x39" [label="Wire"];
"0x3a" [label="TpSigDeclBody"];
"0x3b" [label="TpVarTplist"];
"0x3c" [label="TpVarTp"];
"0x3d" [label="rst"];
"0x3e" [label="body"];
"0x3f" [label="Always"];
"0x40" [label="TpEvent"];
"0x41" [label="Posedge"];
"0x42" [label="TpVarRange"];
"0x43" [label="clk"];
"0x44" [label="body"];
"0x45" [label="NbkAssign"];
"0x46" [label="TpAssign"];
"0x47" [label="TpEqAssigns"];
"0x48" [label="TpEqAssign"];
"0x49" [label="Lname"];
"0x4a" [label="Var"];
"0x4b" [label="led"];
"0x4c" [label="Var"];
"0x4d" [label="_0_"];
"0x4e" [label="TpAssign"];
"0x4f" [label="TpEqAssigns"];
"0x50" [label="TpEqAssign"];
"0x51" [label="Lname"];
"0x52" [label="Var"];
"0x53" [label="_0_"];
"0x54" [label="Cond"];
"0x55" [label="Var"];
"0x56" [label="rst"];
"0x57" [label="TrueBlock"];
"0x58" [label="Num"];
"0x59" [label="8"];
"0x5a" [label="Hex"];
"0x5b" [label="1"];
"0x5c" [label="FalseBlock"];
"0x5d" [label="Conc"];
"0x5e" [label="TpConcList"];
"0x5f" [label="Ele"];
"0x60" [label="Idx"];
"0x61" [label="led"];
"0x62" [label="RngC"];
"0x63" [label="Int"];
"0x64" [label="6"];
"0x65" [label="Int"];
"0x66" [label="0"];
"0x67" [label="Ele"];
"0x68" [label="Idx"];
"0x69" [label="led"];
"0x6a" [label="TpExpList"];
"0x6b" [label="Int"];
"0x6c" [label="7"];
"0x0" -> "0x1";
"0x1" -> "0x2";
"0x2" -> "0x3";
"0x2" -> "0xc";
"0x2" -> "0x15";
"0x2" -> "0x1f";
"0x2" -> "0x3e";
"0x3" -> "0x4";
"0x4" -> "0x5";
"0x5" -> "0x6";
"0x5" -> "0x8";
"0x5" -> "0xa";
"0x6" -> "0x7";
"0x8" -> "0x9";
"0xa" -> "0xb";
"0xc" -> "0xd";
"0xc" -> "0x11";
"0xd" -> "0xe";
"0xe" -> "0xf";
"0xf" -> "0x10";
"0x11" -> "0x12";
"0x12" -> "0x13";
"0x13" -> "0x14";
"0x15" -> "0x16";
"0x16" -> "0x17";
"0x16" -> "0x1c";
"0x17" -> "0x18";
"0x17" -> "0x1a";
"0x18" -> "0x19";
"0x1a" -> "0x1b";
"0x1c" -> "0x1d";
"0x1d" -> "0x1e";
"0x1f" -> "0x20";
"0x1f" -> "0x2a";
"0x1f" -> "0x2f";
"0x1f" -> "0x39";
"0x20" -> "0x21";
"0x21" -> "0x22";
"0x21" -> "0x27";
"0x22" -> "0x23";
"0x22" -> "0x25";
"0x23" -> "0x24";
"0x25" -> "0x26";
"0x27" -> "0x28";
"0x28" -> "0x29";
"0x2a" -> "0x2b";
"0x2b" -> "0x2c";
"0x2c" -> "0x2d";
"0x2d" -> "0x2e";
"0x2f" -> "0x30";
"0x30" -> "0x31";
"0x30" -> "0x36";
"0x31" -> "0x32";
"0x31" -> "0x34";
"0x32" -> "0x33";
"0x34" -> "0x35";
"0x36" -> "0x37";
"0x37" -> "0x38";
"0x39" -> "0x3a";
"0x3a" -> "0x3b";
"0x3b" -> "0x3c";
"0x3c" -> "0x3d";
"0x3e" -> "0x3f";
"0x3e" -> "0x4e";
"0x3f" -> "0x40";
"0x3f" -> "0x44";
"0x40" -> "0x41";
"0x41" -> "0x42";
"0x42" -> "0x43";
"0x44" -> "0x45";
"0x45" -> "0x46";
"0x46" -> "0x47";
"0x47" -> "0x48";
"0x48" -> "0x49";
"0x48" -> "0x4c";
"0x49" -> "0x4a";
"0x4a" -> "0x4b";
"0x4c" -> "0x4d";
"0x4e" -> "0x4f";
"0x4f" -> "0x50";
"0x50" -> "0x51";
"0x50" -> "0x54";
"0x51" -> "0x52";
"0x52" -> "0x53";
"0x54" -> "0x55";
"0x54" -> "0x57";
"0x54" -> "0x5c";
"0x55" -> "0x56";
"0x57" -> "0x58";
"0x58" -> "0x59";
"0x58" -> "0x5a";
"0x5a" -> "0x5b";
"0x5c" -> "0x5d";
"0x5d" -> "0x5e";
"0x5e" -> "0x5f";
"0x5e" -> "0x67";
"0x5f" -> "0x60";
"0x60" -> "0x61";
"0x60" -> "0x62";
"0x62" -> "0x63";
"0x62" -> "0x65";
"0x63" -> "0x64";
"0x65" -> "0x66";
"0x67" -> "0x68";
"0x68" -> "0x69";
"0x68" -> "0x6a";
"0x6a" -> "0x6b";
"0x6b" -> "0x6c";
}
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/Led_ast_clean.json 0 → 100644
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "clk"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "rst"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "led"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "paras"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "clk"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
},
{
"children": [
{
"children": [
{
"children": [
{
"name": "rst"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "ilists"
},
{
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"0x2a" -> "0x2b";
"0x2c" -> "0x2d";
"0x2d" -> "0x2e";
"0x2f" -> "0x30";
"0x30" -> "0x31";
"0x31" -> "0x32";
"0x33" -> "0x34";
"0x33" -> "0x39";
"0x34" -> "0x35";
"0x34" -> "0x37";
"0x35" -> "0x36";
"0x37" -> "0x38";
"0x39" -> "0x3a";
"0x3a" -> "0x3b";
"0x3c" -> "0x3d";
"0x3c" -> "0x47";
"0x3c" -> "0x4c";
"0x3c" -> "0x56";
"0x3c" -> "0x60";
"0x3c" -> "0x6a";
"0x3c" -> "0x74";
"0x3c" -> "0x79";
"0x3c" -> "0x7e";
"0x3c" -> "0x83";
"0x3c" -> "0x88";
"0x3c" -> "0x92";
"0x3c" -> "0x97";
"0x3c" -> "0xa1";
"0x3c" -> "0xab";
"0x3c" -> "0xb0";
"0x3c" -> "0xba";
"0x3d" -> "0x3e";
"0x3e" -> "0x3f";
"0x3e" -> "0x44";
"0x3f" -> "0x40";
"0x3f" -> "0x42";
"0x40" -> "0x41";
"0x42" -> "0x43";
"0x44" -> "0x45";
"0x45" -> "0x46";
"0x47" -> "0x48";
"0x48" -> "0x49";
"0x49" -> "0x4a";
"0x4a" -> "0x4b";
"0x4c" -> "0x4d";
"0x4d" -> "0x4e";
"0x4d" -> "0x53";
"0x4e" -> "0x4f";
"0x4e" -> "0x51";
"0x4f" -> "0x50";
"0x51" -> "0x52";
"0x53" -> "0x54";
"0x54" -> "0x55";
"0x56" -> "0x57";
"0x57" -> "0x58";
"0x57" -> "0x5d";
"0x58" -> "0x59";
"0x58" -> "0x5b";
"0x59" -> "0x5a";
"0x5b" -> "0x5c";
"0x5d" -> "0x5e";
"0x5e" -> "0x5f";
"0x60" -> "0x61";
"0x61" -> "0x62";
"0x61" -> "0x67";
"0x62" -> "0x63";
"0x62" -> "0x65";
"0x63" -> "0x64";
"0x65" -> "0x66";
"0x67" -> "0x68";
"0x68" -> "0x69";
"0x6a" -> "0x6b";
"0x6b" -> "0x6c";
"0x6b" -> "0x71";
"0x6c" -> "0x6d";
"0x6c" -> "0x6f";
"0x6d" -> "0x6e";
"0x6f" -> "0x70";
"0x71" -> "0x72";
"0x72" -> "0x73";
"0x74" -> "0x75";
"0x75" -> "0x76";
"0x76" -> "0x77";
"0x77" -> "0x78";
"0x79" -> "0x7a";
"0x7a" -> "0x7b";
"0x7b" -> "0x7c";
"0x7c" -> "0x7d";
"0x7e" -> "0x7f";
"0x7f" -> "0x80";
"0x80" -> "0x81";
"0x81" -> "0x82";
"0x83" -> "0x84";
"0x84" -> "0x85";
"0x85" -> "0x86";
"0x86" -> "0x87";
"0x88" -> "0x89";
"0x89" -> "0x8a";
"0x89" -> "0x8f";
"0x8a" -> "0x8b";
"0x8a" -> "0x8d";
"0x8b" -> "0x8c";
"0x8d" -> "0x8e";
"0x8f" -> "0x90";
"0x90" -> "0x91";
"0x92" -> "0x93";
"0x93" -> "0x94";
"0x94" -> "0x95";
"0x95" -> "0x96";
"0x97" -> "0x98";
"0x98" -> "0x99";
"0x98" -> "0x9e";
"0x99" -> "0x9a";
"0x99" -> "0x9c";
"0x9a" -> "0x9b";
"0x9c" -> "0x9d";
"0x9e" -> "0x9f";
"0x9f" -> "0xa0";
"0xa1" -> "0xa2";
"0xa2" -> "0xa3";
"0xa2" -> "0xa8";
"0xa3" -> "0xa4";
"0xa3" -> "0xa6";
"0xa4" -> "0xa5";
"0xa6" -> "0xa7";
"0xa8" -> "0xa9";
"0xa9" -> "0xaa";
"0xab" -> "0xac";
"0xac" -> "0xad";
"0xad" -> "0xae";
"0xae" -> "0xaf";
"0xb0" -> "0xb1";
"0xb1" -> "0xb2";
"0xb1" -> "0xb7";
"0xb2" -> "0xb3";
"0xb2" -> "0xb5";
"0xb3" -> "0xb4";
"0xb5" -> "0xb6";
"0xb7" -> "0xb8";
"0xb8" -> "0xb9";
"0xba" -> "0xbb";
"0xbb" -> "0xbc";
"0xbc" -> "0xbd";
"0xbd" -> "0xbe";
"0xbf" -> "0xc0";
"0xbf" -> "0xc9";
"0xbf" -> "0xd8";
"0xbf" -> "0xe7";
"0xbf" -> "0xf6";
"0xbf" -> "0x105";
"0xbf" -> "0x116";
"0xbf" -> "0x127";
"0xbf" -> "0x136";
"0xbf" -> "0x157";
"0xbf" -> "0x16d";
"0xbf" -> "0x177";
"0xbf" -> "0x181";
"0xbf" -> "0x18b";
"0xc0" -> "0xc1";
"0xc1" -> "0xc2";
"0xc2" -> "0xc3";
"0xc2" -> "0xc6";
"0xc3" -> "0xc4";
"0xc4" -> "0xc5";
"0xc6" -> "0xc7";
"0xc7" -> "0xc8";
"0xc9" -> "0xca";
"0xca" -> "0xcb";
"0xcb" -> "0xcc";
"0xcb" -> "0xcf";
"0xcc" -> "0xcd";
"0xcd" -> "0xce";
"0xcf" -> "0xd0";
"0xcf" -> "0xd3";
"0xd0" -> "0xd1";
"0xd1" -> "0xd2";
"0xd3" -> "0xd4";
"0xd4" -> "0xd5";
"0xd4" -> "0xd6";
"0xd6" -> "0xd7";
"0xd8" -> "0xd9";
"0xd8" -> "0xdd";
"0xd9" -> "0xda";
"0xda" -> "0xdb";
"0xdb" -> "0xdc";
"0xdd" -> "0xde";
"0xde" -> "0xdf";
"0xdf" -> "0xe0";
"0xe0" -> "0xe1";
"0xe1" -> "0xe2";
"0xe1" -> "0xe5";
"0xe2" -> "0xe3";
"0xe3" -> "0xe4";
"0xe5" -> "0xe6";
"0xe7" -> "0xe8";
"0xe7" -> "0xec";
"0xe8" -> "0xe9";
"0xe9" -> "0xea";
"0xea" -> "0xeb";
"0xec" -> "0xed";
"0xed" -> "0xee";
"0xee" -> "0xef";
"0xef" -> "0xf0";
"0xf0" -> "0xf1";
"0xf0" -> "0xf4";
"0xf1" -> "0xf2";
"0xf2" -> "0xf3";
"0xf4" -> "0xf5";
"0xf6" -> "0xf7";
"0xf7" -> "0xf8";
"0xf8" -> "0xf9";
"0xf8" -> "0xfc";
"0xf9" -> "0xfa";
"0xfa" -> "0xfb";
"0xfc" -> "0xfd";
"0xfc" -> "0xff";
"0xfc" -> "0x102";
"0xfd" -> "0xfe";
"0xff" -> "0x100";
"0x100" -> "0x101";
"0x102" -> "0x103";
"0x103" -> "0x104";
"0x105" -> "0x106";
"0x106" -> "0x107";
"0x107" -> "0x108";
"0x107" -> "0x10b";
"0x108" -> "0x109";
"0x109" -> "0x10a";
"0x10b" -> "0x10c";
"0x10b" -> "0x10e";
"0x10b" -> "0x111";
"0x10c" -> "0x10d";
"0x10e" -> "0x10f";
"0x10f" -> "0x110";
"0x111" -> "0x112";
"0x112" -> "0x113";
"0x112" -> "0x114";
"0x114" -> "0x115";
"0x116" -> "0x117";
"0x117" -> "0x118";
"0x118" -> "0x119";
"0x118" -> "0x11c";
"0x119" -> "0x11a";
"0x11a" -> "0x11b";
"0x11c" -> "0x11d";
"0x11c" -> "0x11f";
"0x11c" -> "0x122";
"0x11d" -> "0x11e";
"0x11f" -> "0x120";
"0x120" -> "0x121";
"0x122" -> "0x123";
"0x123" -> "0x124";
"0x123" -> "0x125";
"0x125" -> "0x126";
"0x127" -> "0x128";
"0x128" -> "0x129";
"0x129" -> "0x12a";
"0x129" -> "0x12d";
"0x12a" -> "0x12b";
"0x12b" -> "0x12c";
"0x12d" -> "0x12e";
"0x12d" -> "0x131";
"0x12e" -> "0x12f";
"0x12f" -> "0x130";
"0x131" -> "0x132";
"0x132" -> "0x133";
"0x132" -> "0x134";
"0x134" -> "0x135";
"0x136" -> "0x137";
"0x137" -> "0x138";
"0x138" -> "0x139";
"0x138" -> "0x14c";
"0x139" -> "0x13a";
"0x13a" -> "0x13b";
"0x13a" -> "0x143";
"0x13a" -> "0x149";
"0x13b" -> "0x13c";
"0x13c" -> "0x13d";
"0x13c" -> "0x13e";
"0x13e" -> "0x13f";
"0x13e" -> "0x141";
"0x13f" -> "0x140";
"0x141" -> "0x142";
"0x143" -> "0x144";
"0x144" -> "0x145";
"0x144" -> "0x146";
"0x146" -> "0x147";
"0x147" -> "0x148";
"0x149" -> "0x14a";
"0x14a" -> "0x14b";
"0x14c" -> "0x14d";
"0x14c" -> "0x14f";
"0x14c" -> "0x154";
"0x14d" -> "0x14e";
"0x14f" -> "0x150";
"0x150" -> "0x151";
"0x150" -> "0x152";
"0x152" -> "0x153";
"0x154" -> "0x155";
"0x155" -> "0x156";
"0x157" -> "0x158";
"0x158" -> "0x159";
"0x159" -> "0x15a";
"0x159" -> "0x162";
"0x15a" -> "0x15b";
"0x15b" -> "0x15c";
"0x15b" -> "0x15d";
"0x15d" -> "0x15e";
"0x15d" -> "0x160";
"0x15e" -> "0x15f";
"0x160" -> "0x161";
"0x162" -> "0x163";
"0x163" -> "0x164";
"0x163" -> "0x16a";
"0x164" -> "0x165";
"0x165" -> "0x166";
"0x165" -> "0x167";
"0x167" -> "0x168";
"0x168" -> "0x169";
"0x16a" -> "0x16b";
"0x16b" -> "0x16c";
"0x16d" -> "0x16e";
"0x16e" -> "0x16f";
"0x16f" -> "0x170";
"0x16f" -> "0x173";
"0x170" -> "0x171";
"0x171" -> "0x172";
"0x173" -> "0x174";
"0x173" -> "0x175";
"0x175" -> "0x176";
"0x177" -> "0x178";
"0x178" -> "0x179";
"0x179" -> "0x17a";
"0x179" -> "0x17d";
"0x17a" -> "0x17b";
"0x17b" -> "0x17c";
"0x17d" -> "0x17e";
"0x17d" -> "0x17f";
"0x17f" -> "0x180";
"0x181" -> "0x182";
"0x182" -> "0x183";
"0x183" -> "0x184";
"0x183" -> "0x187";
"0x184" -> "0x185";
"0x185" -> "0x186";
"0x187" -> "0x188";
"0x187" -> "0x189";
"0x189" -> "0x18a";
"0x18b" -> "0x18c";
"0x18c" -> "0x18d";
"0x18d" -> "0x18e";
"0x18d" -> "0x196";
"0x18e" -> "0x18f";
"0x18f" -> "0x190";
"0x18f" -> "0x191";
"0x191" -> "0x192";
"0x191" -> "0x194";
"0x192" -> "0x193";
"0x194" -> "0x195";
"0x196" -> "0x197";
}
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/test_ast_clean.json 0 → 100644
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "clk"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "fifo_rd"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "rst_n"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "fifo_EF"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "fifo_rdata"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "rfifo_full"
}
],
"name": "TpVarTp"
},
{
"children": [
{
"name": "rfifo_used"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "paras"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "clk"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
},
{
"children": [
{
"children": [
{
"children": [
{
"name": "fifo_rd"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
},
{
"children": [
{
"children": [
{
"children": [
{
"name": "rst_n"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "ilists"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "fifo_EF"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
},
{
"children": [
{
"children": [
{
"children": [
{
"name": "7"
}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "fifo_rdata"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
},
{
"children": [
{
"children": [
{
"children": [
{
"name": "rfifo_full"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
},
{
"children": [
{
"children": [
{
"children": [
{
"name": "5"
}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "rfifo_used"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "olists"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "31"
}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "_00_"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "_01_"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
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}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "_02_"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "31"
}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "_03_"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "31"
}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "_04_"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "31"
}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "bytes_left"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Reg"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "clk"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "fifo_EF"
}
],
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}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "fifo_rd"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "fifo_rd_d"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Reg"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "7"
}
],
"name": "Int"
},
{
"children": [
{
"name": "0"
}
],
"name": "Int"
}
],
"name": "RngC"
},
{
"children": [
{
"children": [
{
"name": "fifo_rdata"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
}
],
"name": "TpSigDeclBody"
}
],
"name": "Wire"
},
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "new_rom"
}
],
"name": "TpVarTp"
}
],
"name": "TpVarTplist"
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],
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{
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"children": [
{
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"name": "TpEvent"
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{
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{
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{
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{
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}
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"name": "Ele"
},
{
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{
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{
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{
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}
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}
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{
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{
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{
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{
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{
"children": [
{
"children": [
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{
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{
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{
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{
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{
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{
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{
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],
"name": "TpAssign"
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{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"children": [
{
"name": "rfifo_entries"
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{
"children": [
{
"children": [
{
"name": "5"
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],
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{
"children": [
{
"name": "0"
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"name": "Lname"
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{
"children": [
{
"name": "rfifo_used"
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],
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],
"name": "body"
}
],
"name": "TpTask soc_design_JTAG_sim_scfifo_r"
}
],
"name": "TpModule"
}
],
"name": "TpProg"
}
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/timescale_ast_clean.dot 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/tmp/ast/timescale_ast_clean.json 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/tmp/run_ast_Led.ys 0 → 100644
# Auto-generated by cdfg_generator.sh
read_verilog -sv "../verilog_data/Led.v"
hierarchy -check
proc
flatten
memory
write_verilog "./tmp/yosys_output_data/Led_ast.v"
thirdparty/RTL2CDFG/v2cdfg/tmp/run_ast_timescale.ys 0 → 100644
# Auto-generated by cdfg_generator.sh
read_verilog -sv "../../../cases/eth_fifo/rtl/timescale.v" "../../../cases/eth_fifo/rtl/ethmac_defines.v" "../../../cases/eth_fifo/rtl/eth_fifo.v"
hierarchy -check
proc
flatten
memory
write_verilog "./tmp/yosys_output_data/timescale_ast.v"
thirdparty/RTL2CDFG/v2cdfg/tmp/s_exp/Led_ast_clean.s 0 → 100644
(TpProg (TpModule (TpTask led_chaser (sharp null) (paras (Port (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp) (TpVarTp rst (TpDim null) NullExp) (TpVarTp led (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp)))) (iolists null) (olists (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp)))) (sigset (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp _0_ (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp led (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst (TpDim null) NullExp))))) (body (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var led)) (Atom (Sym (Var _0_))) NoDE)))))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _0_)) (Cond (Atom (Sym (Var rst))) (Atom (Num false 8 (Hex false 01))) (Conc (Clist (TpConcList (Ele (Atom (Sym (Idx led (TpExpList null) (RngC (Atom (Int 6)) (Atom (Int 0))))))) (Ele (Atom (Sym (Idx led (TpExpList (Atom (Int 7))) Rng0)))))))) NoDE))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/tmp/s_exp/test_ast_clean.s 0 → 100644
(TpProg (TpModule (TpTask soc_design_JTAG_sim_scfifo_r (sharp null) (paras (Port (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp) (TpVarTp fifo_rd (TpDim null) NullExp) (TpVarTp rst_n (TpDim null) NullExp) (TpVarTp fifo_EF (TpDim null) NullExp) (TpVarTp fifo_rdata (TpDim null) NullExp) (TpVarTp rfifo_full (TpDim null) NullExp) (TpVarTp rfifo_used (TpDim null) NullExp))))) (parameters null) (localparam null) (ilists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (iolists null) (olists (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp))) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (sigset (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _00_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp _01_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _02_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _03_ (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp _04_ (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp bytes_left (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp clk (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_EF (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd (TpDim null) NullExp)))) (Reg (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp fifo_rd_d (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 7)) (Atom (Int 0))) (sharp (TpVarTp fifo_rdata (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp new_rom (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 31)) (Atom (Int 0))) (sharp (TpVarTp num_bytes (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 6)) (Atom (Int 0))) (sharp (TpVarTp rfifo_entries (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rfifo_full (TpDim null) NullExp)))) (Output (Nettype Nullnet) (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 5)) (Atom (Int 0))) (sharp (TpVarTp rfifo_used (TpDim null) NullExp)))) (Input Nullnet (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp)))) (Wire (TpSigDeclBody false NoDelay (RngC (Atom (Int 0)) (Atom (Int 0))) (sharp (TpVarTp rst_n (TpDim null) NullExp))))) (body (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_EF)) (LNot (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var rfifo_full)) (Gt (Atom (Sym (Var bytes_left))) (Atom (Num false 7 (Hex false 40)))) NoDE)))) (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var bytes_left)) (Atom (Sym (Var _00_))) NoDE)))))) (Always (TpEvent (Posedge (TpVarRange clk Rng0))) (body (NbkAssign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rd_d)) (Atom (Sym (Var _01_))) NoDE)))))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _02_)) (Cond (Atom (Sym (Var fifo_rd_d))) (Atom (Sym (Var _03_))) (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _00_)) (Cond (Atom (Sym (Var rst_n))) (Atom (Sym (Var _02_))) (Atom (Num false 32 (Dec false 0)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _01_)) (Cond (Atom (Sym (Var rst_n))) (Atom (Sym (Var fifo_rd))) (Atom (Num false 1 (Hex false 0)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var _03_)) (Sub (Atom (Sym (Var bytes_left))) (Atom (Num false 1 (Hex false 1)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lconc (Clist (TpConcList (Ele (Atom (Sym (Idx _04_ (TpExpList null) (RngC (Atom (Int 31)) (Atom (Int 7))))))) (Ele (Atom (Sym (Idx rfifo_entries (TpExpList (Atom (Int 6))) Rng0)))) (Ele (Atom (Sym (Var rfifo_used))))))) (Cond (Atom (Sym (Var rfifo_full))) (Atom (Num false 32 (Dec false 64))) (Atom (Sym (Var bytes_left)))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Idx _04_ (TpExpList null) (RngC (Atom (Int 6)) (Atom (Int 0))))) (Conc (Clist (TpConcList (Ele (Atom (Sym (Idx rfifo_entries (TpExpList (Atom (Int 6))) Rng0)))) (Ele (Atom (Sym (Var rfifo_used))))))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var fifo_rdata)) (Atom (Num false 8 (Hex false 00))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var new_rom)) (Atom (Num false 1 (Hex false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Var num_bytes)) (Atom (Num false 32 (Dec false 0))) NoDE)))) (Assign (TpAssign NoDE (TpEqAssigns (TpEqAssign (Lname (Idx rfifo_entries (TpExpList null) (RngC (Atom (Int 5)) (Atom (Int 0))))) (Atom (Sym (Var rfifo_used))) NoDE))))) (macros null))))
thirdparty/RTL2CDFG/v2cdfg/tmp/s_exp/timescale_ast_clean.s 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data/Led_ast.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
(* src = "../verilog_data/Led.v:1.1-15.10" *)
module led_chaser(clk, rst, led);
(* src = "../verilog_data/Led.v:7.1-13.4" *)
wire [7:0] _0_;
(* src = "../verilog_data/Led.v:2.16-2.19" *)
input clk;
wire clk;
(* src = "../verilog_data/Led.v:4.22-4.25" *)
output [7:0] led;
reg [7:0] led;
(* src = "../verilog_data/Led.v:3.16-3.19" *)
input rst;
wire rst;
(* src = "../verilog_data/Led.v:7.1-13.4" *)
always @(posedge clk)
led <= _0_;
assign _0_ = rst ? (* full_case = 32'd1 *) (* src = "../verilog_data/Led.v:8.9-8.12|../verilog_data/Led.v:8.5-12.8" *) 8'h01 : { led[6:0], led[7] };
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data/test_ast.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
(* src = "./test.v:1.1-49.10" *)
module soc_design_JTAG_sim_scfifo_r(clk, fifo_rd, rst_n, fifo_EF, fifo_rdata, rfifo_full, rfifo_used);
(* src = "./test.v:26.1-41.4" *)
wire [31:0] _00_;
(* src = "./test.v:26.1-41.4" *)
wire _01_;
wire [31:0] _02_;
(* src = "./test.v:37.25-37.42" *)
wire [31:0] _03_;
(* src = "./test.v:44.24-44.57" *)
(* unused_bits = "6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *)
wire [31:0] _04_;
(* src = "./test.v:17.18-17.28" *)
reg [31:0] bytes_left;
(* src = "./test.v:14.18-14.21" *)
input clk;
wire clk;
(* src = "./test.v:10.18-10.25" *)
output fifo_EF;
wire fifo_EF;
(* src = "./test.v:15.18-15.25" *)
input fifo_rd;
wire fifo_rd;
(* src = "./test.v:19.18-19.27" *)
reg fifo_rd_d;
(* src = "./test.v:11.18-11.28" *)
output [7:0] fifo_rdata;
wire [7:0] fifo_rdata;
(* src = "./test.v:21.18-21.25" *)
wire new_rom;
(* src = "./test.v:22.18-22.27" *)
wire [31:0] num_bytes;
(* src = "./test.v:23.18-23.31" *)
(* unused_bits = "6" *)
wire [6:0] rfifo_entries;
(* src = "./test.v:12.18-12.28" *)
output rfifo_full;
wire rfifo_full;
(* src = "./test.v:13.18-13.28" *)
output [5:0] rfifo_used;
wire [5:0] rfifo_used;
(* src = "./test.v:16.18-16.23" *)
input rst_n;
wire rst_n;
assign fifo_EF = ! (* src = "./test.v:42.18-42.37" *) bytes_left;
assign rfifo_full = bytes_left > (* src = "./test.v:43.21-43.39" *) 7'h40;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
bytes_left <= _00_;
(* src = "./test.v:26.1-41.4" *)
always @(posedge clk)
fifo_rd_d <= _01_;
assign _02_ = fifo_rd_d ? (* src = "./test.v:36.11-36.20|./test.v:36.7-37.43" *) _03_ : bytes_left;
assign _00_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) _02_ : 32'd0;
assign _01_ = rst_n ? (* full_case = 32'd1 *) (* src = "./test.v:28.7-28.17|./test.v:28.3-40.8" *) fifo_rd : 1'h0;
assign _03_ = bytes_left - (* src = "./test.v:37.25-37.42" *) 1'h1;
assign { _04_[31:7], rfifo_entries[6], rfifo_used } = rfifo_full ? (* src = "./test.v:44.24-44.57" *) 32'd64 : bytes_left;
assign _04_[6:0] = { rfifo_entries[6], rfifo_used };
assign fifo_rdata = 8'h00;
assign new_rom = 1'h0;
assign num_bytes = 32'd0;
assign rfifo_entries[5:0] = rfifo_used;
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data/timescale_ast.v 0 → 100644
/* Generated by Yosys 0.57+178 (git sha1 93dca50b9, clang++ 18.1.8 -fPIC -O3) */
(* dynports = 1 *)
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:62.1-186.10" *)
module eth_fifo(data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:74.27-74.34" *)
input [31:0] data_in;
wire [31:0] data_in;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:76.27-76.35" *)
output [31:0] data_out;
reg [31:0] data_out;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:69.27-69.30" *)
input clk;
wire clk;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:70.27-70.32" *)
input reset;
wire reset;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:71.27-71.32" *)
input write;
wire write;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:72.27-72.31" *)
input read;
wire read;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:73.27-73.32" *)
input clear;
wire clear;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:77.27-77.38" *)
output almost_full;
wire almost_full;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:78.27-78.31" *)
output full;
wire full;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:79.27-79.39" *)
output almost_empty;
wire almost_empty;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:80.27-80.32" *)
output empty;
wire empty;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:81.27-81.30" *)
output [3:0] cnt;
reg [3:0] cnt;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [31:0] _0000_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [31:0] _0001_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [2:0] _0002_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [31:0] _0003_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [31:0] _0004_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:97.1-110.4" *)
wire [3:0] _0005_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:175.3-181.6" *)
wire [31:0] _0006_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:113.1-123.4" *)
wire [2:0] _0007_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:125.1-135.4" *)
wire [2:0] _0008_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [2:0] _0009_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [31:0] _0010_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:165.3-172.6" *)
wire [31:0] _0011_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:109.14-109.21" *)
(* unused_bits = "4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *)
wire [31:0] _0012_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:122.21-122.40" *)
wire [2:0] _0013_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:134.22-134.42" *)
wire [2:0] _0014_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:121.6-121.19" *)
wire _0015_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:133.6-133.19" *)
wire _0016_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21" *)
wire _0017_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:170.7-170.20" *)
wire _0018_;
wire [31:0] _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire [31:0] _0119_;
wire [31:0] _0120_;
wire [31:0] _0121_;
wire [31:0] _0122_;
wire [31:0] _0123_;
wire [31:0] _0124_;
wire [31:0] _0125_;
wire [31:0] _0126_;
wire [31:0] _0127_;
wire [31:0] _0128_;
wire [31:0] _0129_;
wire [31:0] _0130_;
wire [31:0] _0131_;
wire [31:0] _0132_;
wire [31:0] _0133_;
wire [31:0] _0134_;
wire [31:0] _0135_;
wire [31:0] _0136_;
wire [31:0] _0137_;
wire [31:0] _0138_;
wire [31:0] _0139_;
wire [31:0] _0140_;
wire [31:0] _0141_;
wire [31:0] _0142_;
wire [31:0] _0143_;
wire [31:0] _0144_;
wire [31:0] _0145_;
wire [31:0] _0146_;
wire [31:0] _0147_;
wire [31:0] _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
wire _0654_;
wire _0655_;
wire _0656_;
wire _0657_;
wire _0658_;
wire _0659_;
wire _0660_;
wire [31:0] _0661_;
wire [31:0] _0662_;
wire [31:0] _0663_;
wire [31:0] _0664_;
wire [31:0] _0665_;
wire [31:0] _0666_;
wire [31:0] _0667_;
wire [31:0] _0668_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:178.19-178.23" *)
wire [31:0] _0669_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:180.19-180.23" *)
wire [31:0] _0670_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:121.13-121.19" *)
wire _0671_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:133.14-133.19" *)
wire _0672_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:170.15-170.20" *)
wire _0673_;
wire [31:0] _0674_;
wire [31:0] _0675_;
wire [2:0] _0676_;
wire [2:0] _0677_;
wire [2:0] _0678_;
wire [3:0] _0679_;
wire [3:0] _0680_;
wire _0681_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:107.14-107.21" *)
(* unused_bits = "4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *)
wire [31:0] _0682_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:103.37-103.47" *)
wire _0683_;
reg [31:0] \fifo[0] ;
reg [31:0] \fifo[1] ;
reg [31:0] \fifo[2] ;
reg [31:0] \fifo[3] ;
reg [31:0] \fifo[4] ;
reg [31:0] \fifo[5] ;
reg [31:0] \fifo[6] ;
reg [31:0] \fifo[7] ;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:93.27-93.39" *)
reg [2:0] read_pointer;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:94.27-94.40" *)
reg [2:0] write_pointer;
assign _0012_ = cnt + (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:109.14-109.21" *) 32'd1;
assign _0013_ = read_pointer + (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:122.21-122.40" *) 1'h1;
assign _0014_ = write_pointer + (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:134.22-134.42" *) 1'h1;
assign _0015_ = read & (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:121.6-121.19" *) _0671_;
assign _0016_ = write & (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:133.6-133.19" *) _0672_;
assign _0017_ = write & (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21" *) clear;
assign _0018_ = write & (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:170.7-170.20" *) _0673_;
assign _0084_ = _0119_[0] == 1'h0;
assign _0085_ = _0119_[1] == 1'h0;
assign _0086_ = _0119_[2] == 1'h0;
assign _0087_ = _0119_[3] == 1'h0;
assign _0088_ = _0119_[4] == 1'h0;
assign _0089_ = _0119_[5] == 1'h0;
assign _0090_ = _0119_[6] == 1'h0;
assign _0091_ = _0119_[7] == 1'h0;
assign _0092_ = _0119_[8] == 1'h0;
assign _0093_ = _0119_[9] == 1'h0;
assign _0094_ = _0119_[10] == 1'h0;
assign _0095_ = _0119_[11] == 1'h0;
assign _0096_ = _0119_[12] == 1'h0;
assign _0097_ = _0119_[13] == 1'h0;
assign _0098_ = _0119_[14] == 1'h0;
assign _0099_ = _0119_[15] == 1'h0;
assign _0100_ = _0119_[16] == 1'h0;
assign _0101_ = _0119_[17] == 1'h0;
assign _0102_ = _0119_[18] == 1'h0;
assign _0103_ = _0119_[19] == 1'h0;
assign _0104_ = _0119_[20] == 1'h0;
assign _0105_ = _0119_[21] == 1'h0;
assign _0106_ = _0119_[22] == 1'h0;
assign _0107_ = _0119_[23] == 1'h0;
assign _0108_ = _0119_[24] == 1'h0;
assign _0109_ = _0119_[25] == 1'h0;
assign _0110_ = _0119_[26] == 1'h0;
assign _0111_ = _0119_[27] == 1'h0;
assign _0112_ = _0119_[28] == 1'h0;
assign _0113_ = _0119_[29] == 1'h0;
assign _0114_ = _0119_[30] == 1'h0;
assign _0115_ = _0119_[31] == 1'h0;
assign _0116_ = _0119_[0] == 1'h1;
assign _0117_ = _0119_[1] == 1'h1;
assign _0118_ = _0119_[2] == 1'h1;
assign _0021_ = _0083_ & _0059_;
assign _0022_ = _0066_ & _0076_;
assign _0023_ = _0022_ & _0035_;
assign _0024_ = _0023_ & _0043_;
assign _0025_ = _0024_ & _0059_;
assign _0026_ = _0071_ & _0076_;
assign _0027_ = _0026_ & _0035_;
assign _0028_ = _0027_ & _0043_;
assign _0029_ = _0028_ & _0059_;
assign _0030_ = _0084_ & _0085_;
assign _0031_ = _0086_ & _0087_;
assign _0032_ = _0030_ & _0031_;
assign _0033_ = _0088_ & _0089_;
assign _0034_ = _0090_ & _0091_;
assign _0035_ = _0033_ & _0034_;
assign _0036_ = _0032_ & _0035_;
assign _0037_ = _0092_ & _0093_;
assign _0038_ = _0094_ & _0095_;
assign _0039_ = _0037_ & _0038_;
assign _0040_ = _0096_ & _0097_;
assign _0041_ = _0098_ & _0099_;
assign _0042_ = _0040_ & _0041_;
assign _0043_ = _0039_ & _0042_;
assign _0044_ = _0036_ & _0043_;
assign _0045_ = _0100_ & _0101_;
assign _0046_ = _0102_ & _0103_;
assign _0047_ = _0045_ & _0046_;
assign _0048_ = _0104_ & _0105_;
assign _0049_ = _0106_ & _0107_;
assign _0050_ = _0048_ & _0049_;
assign _0051_ = _0047_ & _0050_;
assign _0052_ = _0108_ & _0109_;
assign _0053_ = _0110_ & _0111_;
assign _0054_ = _0052_ & _0053_;
assign _0055_ = _0112_ & _0113_;
assign _0056_ = _0114_ & _0115_;
assign _0057_ = _0055_ & _0056_;
assign _0058_ = _0054_ & _0057_;
assign _0059_ = _0051_ & _0058_;
assign _0060_ = _0044_ & _0059_;
assign _0061_ = _0116_ & _0085_;
assign _0062_ = _0061_ & _0031_;
assign _0063_ = _0062_ & _0035_;
assign _0064_ = _0063_ & _0043_;
assign _0065_ = _0064_ & _0059_;
assign _0066_ = _0084_ & _0117_;
assign _0067_ = _0066_ & _0031_;
assign _0068_ = _0067_ & _0035_;
assign _0069_ = _0068_ & _0043_;
assign _0070_ = _0069_ & _0059_;
assign _0071_ = _0116_ & _0117_;
assign _0072_ = _0071_ & _0031_;
assign _0073_ = _0072_ & _0035_;
assign _0074_ = _0073_ & _0043_;
assign _0075_ = _0074_ & _0059_;
assign _0076_ = _0118_ & _0087_;
assign _0077_ = _0030_ & _0076_;
assign _0078_ = _0077_ & _0035_;
assign _0079_ = _0078_ & _0043_;
assign _0080_ = _0079_ & _0059_;
assign _0081_ = _0061_ & _0076_;
assign _0082_ = _0081_ & _0035_;
assign _0083_ = _0082_ & _0043_;
assign _0020_ = | _0004_;
assign _0119_ = _0020_ ? { 29'h00000000, _0002_ } : 32'd0;
assign _0120_ = _0020_ ? _0003_ : _0000_;
assign _0019_ = _0020_ ? _0004_ : _0001_;
assign almost_empty = cnt == (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:138.23-138.31" *) 4'h1;
assign full = cnt == (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:139.16-139.28" *) 4'h8;
assign _0670_ = read_pointer[2] ? _0122_ : _0121_;
assign _0121_ = read_pointer[1] ? _0124_ : _0123_;
assign _0122_ = read_pointer[1] ? _0126_ : _0125_;
assign _0123_ = read_pointer[0] ? _0128_ : _0127_;
assign _0124_ = read_pointer[0] ? _0130_ : _0129_;
assign _0125_ = read_pointer[0] ? _0132_ : _0131_;
assign _0126_ = read_pointer[0] ? _0134_ : _0133_;
assign _0669_ = 1'h0 ? _0136_ : _0135_;
assign _0135_ = 1'h0 ? _0138_ : _0137_;
assign _0136_ = 1'h0 ? _0140_ : _0139_;
assign _0137_ = 1'h0 ? _0142_ : _0141_;
assign _0138_ = 1'h0 ? _0144_ : _0143_;
assign _0139_ = 1'h0 ? _0146_ : _0145_;
assign _0140_ = 1'h0 ? _0148_ : _0147_;
assign _0149_ = _0060_ & _0019_[0];
assign _0150_ = _0060_ & _0019_[10];
assign _0151_ = _0060_ & _0019_[11];
assign _0152_ = _0060_ & _0019_[12];
assign _0153_ = _0060_ & _0019_[13];
assign _0154_ = _0060_ & _0019_[14];
assign _0155_ = _0060_ & _0019_[15];
assign _0156_ = _0060_ & _0019_[16];
assign _0157_ = _0060_ & _0019_[17];
assign _0158_ = _0060_ & _0019_[18];
assign _0159_ = _0060_ & _0019_[19];
assign _0160_ = _0060_ & _0019_[1];
assign _0161_ = _0060_ & _0019_[20];
assign _0162_ = _0060_ & _0019_[21];
assign _0163_ = _0060_ & _0019_[22];
assign _0164_ = _0060_ & _0019_[23];
assign _0165_ = _0060_ & _0019_[24];
assign _0166_ = _0060_ & _0019_[25];
assign _0167_ = _0060_ & _0019_[26];
assign _0168_ = _0060_ & _0019_[27];
assign _0169_ = _0060_ & _0019_[28];
assign _0170_ = _0060_ & _0019_[29];
assign _0171_ = _0060_ & _0019_[2];
assign _0172_ = _0060_ & _0019_[30];
assign _0173_ = _0060_ & _0019_[31];
assign _0174_ = _0060_ & _0019_[3];
assign _0175_ = _0060_ & _0019_[4];
assign _0176_ = _0060_ & _0019_[5];
assign _0177_ = _0060_ & _0019_[6];
assign _0178_ = _0060_ & _0019_[7];
assign _0179_ = _0060_ & _0019_[8];
assign _0180_ = _0060_ & _0019_[9];
assign _0181_ = _0065_ & _0019_[0];
assign _0182_ = _0065_ & _0019_[10];
assign _0183_ = _0065_ & _0019_[11];
assign _0184_ = _0065_ & _0019_[12];
assign _0185_ = _0065_ & _0019_[13];
assign _0186_ = _0065_ & _0019_[14];
assign _0187_ = _0065_ & _0019_[15];
assign _0188_ = _0065_ & _0019_[16];
assign _0189_ = _0065_ & _0019_[17];
assign _0190_ = _0065_ & _0019_[18];
assign _0191_ = _0065_ & _0019_[19];
assign _0192_ = _0065_ & _0019_[1];
assign _0193_ = _0065_ & _0019_[20];
assign _0194_ = _0065_ & _0019_[21];
assign _0195_ = _0065_ & _0019_[22];
assign _0196_ = _0065_ & _0019_[23];
assign _0197_ = _0065_ & _0019_[24];
assign _0198_ = _0065_ & _0019_[25];
assign _0199_ = _0065_ & _0019_[26];
assign _0200_ = _0065_ & _0019_[27];
assign _0201_ = _0065_ & _0019_[28];
assign _0202_ = _0065_ & _0019_[29];
assign _0203_ = _0065_ & _0019_[2];
assign _0204_ = _0065_ & _0019_[30];
assign _0205_ = _0065_ & _0019_[31];
assign _0206_ = _0065_ & _0019_[3];
assign _0207_ = _0065_ & _0019_[4];
assign _0208_ = _0065_ & _0019_[5];
assign _0209_ = _0065_ & _0019_[6];
assign _0210_ = _0065_ & _0019_[7];
assign _0211_ = _0065_ & _0019_[8];
assign _0212_ = _0065_ & _0019_[9];
assign _0213_ = _0070_ & _0019_[0];
assign _0214_ = _0070_ & _0019_[10];
assign _0215_ = _0070_ & _0019_[11];
assign _0216_ = _0070_ & _0019_[12];
assign _0217_ = _0070_ & _0019_[13];
assign _0218_ = _0070_ & _0019_[14];
assign _0219_ = _0070_ & _0019_[15];
assign _0220_ = _0070_ & _0019_[16];
assign _0221_ = _0070_ & _0019_[17];
assign _0222_ = _0070_ & _0019_[18];
assign _0223_ = _0070_ & _0019_[19];
assign _0224_ = _0070_ & _0019_[1];
assign _0225_ = _0070_ & _0019_[20];
assign _0226_ = _0070_ & _0019_[21];
assign _0227_ = _0070_ & _0019_[22];
assign _0228_ = _0070_ & _0019_[23];
assign _0229_ = _0070_ & _0019_[24];
assign _0230_ = _0070_ & _0019_[25];
assign _0231_ = _0070_ & _0019_[26];
assign _0232_ = _0070_ & _0019_[27];
assign _0233_ = _0070_ & _0019_[28];
assign _0234_ = _0070_ & _0019_[29];
assign _0235_ = _0070_ & _0019_[2];
assign _0236_ = _0070_ & _0019_[30];
assign _0237_ = _0070_ & _0019_[31];
assign _0238_ = _0070_ & _0019_[3];
assign _0239_ = _0070_ & _0019_[4];
assign _0240_ = _0070_ & _0019_[5];
assign _0241_ = _0070_ & _0019_[6];
assign _0242_ = _0070_ & _0019_[7];
assign _0243_ = _0070_ & _0019_[8];
assign _0244_ = _0070_ & _0019_[9];
assign _0245_ = _0075_ & _0019_[0];
assign _0246_ = _0075_ & _0019_[10];
assign _0247_ = _0075_ & _0019_[11];
assign _0248_ = _0075_ & _0019_[12];
assign _0249_ = _0075_ & _0019_[13];
assign _0250_ = _0075_ & _0019_[14];
assign _0251_ = _0075_ & _0019_[15];
assign _0252_ = _0075_ & _0019_[16];
assign _0253_ = _0075_ & _0019_[17];
assign _0254_ = _0075_ & _0019_[18];
assign _0255_ = _0075_ & _0019_[19];
assign _0256_ = _0075_ & _0019_[1];
assign _0257_ = _0075_ & _0019_[20];
assign _0258_ = _0075_ & _0019_[21];
assign _0259_ = _0075_ & _0019_[22];
assign _0260_ = _0075_ & _0019_[23];
assign _0261_ = _0075_ & _0019_[24];
assign _0262_ = _0075_ & _0019_[25];
assign _0263_ = _0075_ & _0019_[26];
assign _0264_ = _0075_ & _0019_[27];
assign _0265_ = _0075_ & _0019_[28];
assign _0266_ = _0075_ & _0019_[29];
assign _0267_ = _0075_ & _0019_[2];
assign _0268_ = _0075_ & _0019_[30];
assign _0269_ = _0075_ & _0019_[31];
assign _0270_ = _0075_ & _0019_[3];
assign _0271_ = _0075_ & _0019_[4];
assign _0272_ = _0075_ & _0019_[5];
assign _0273_ = _0075_ & _0019_[6];
assign _0274_ = _0075_ & _0019_[7];
assign _0275_ = _0075_ & _0019_[8];
assign _0276_ = _0075_ & _0019_[9];
assign _0277_ = _0080_ & _0019_[0];
assign _0278_ = _0080_ & _0019_[10];
assign _0279_ = _0080_ & _0019_[11];
assign _0280_ = _0080_ & _0019_[12];
assign _0281_ = _0080_ & _0019_[13];
assign _0282_ = _0080_ & _0019_[14];
assign _0283_ = _0080_ & _0019_[15];
assign _0284_ = _0080_ & _0019_[16];
assign _0285_ = _0080_ & _0019_[17];
assign _0286_ = _0080_ & _0019_[18];
assign _0287_ = _0080_ & _0019_[19];
assign _0288_ = _0080_ & _0019_[1];
assign _0289_ = _0080_ & _0019_[20];
assign _0290_ = _0080_ & _0019_[21];
assign _0291_ = _0080_ & _0019_[22];
assign _0292_ = _0080_ & _0019_[23];
assign _0293_ = _0080_ & _0019_[24];
assign _0294_ = _0080_ & _0019_[25];
assign _0295_ = _0080_ & _0019_[26];
assign _0296_ = _0080_ & _0019_[27];
assign _0297_ = _0080_ & _0019_[28];
assign _0298_ = _0080_ & _0019_[29];
assign _0299_ = _0080_ & _0019_[2];
assign _0300_ = _0080_ & _0019_[30];
assign _0301_ = _0080_ & _0019_[31];
assign _0302_ = _0080_ & _0019_[3];
assign _0303_ = _0080_ & _0019_[4];
assign _0304_ = _0080_ & _0019_[5];
assign _0305_ = _0080_ & _0019_[6];
assign _0306_ = _0080_ & _0019_[7];
assign _0307_ = _0080_ & _0019_[8];
assign _0308_ = _0080_ & _0019_[9];
assign _0309_ = _0021_ & _0019_[0];
assign _0310_ = _0021_ & _0019_[10];
assign _0311_ = _0021_ & _0019_[11];
assign _0312_ = _0021_ & _0019_[12];
assign _0313_ = _0021_ & _0019_[13];
assign _0314_ = _0021_ & _0019_[14];
assign _0315_ = _0021_ & _0019_[15];
assign _0316_ = _0021_ & _0019_[16];
assign _0317_ = _0021_ & _0019_[17];
assign _0318_ = _0021_ & _0019_[18];
assign _0319_ = _0021_ & _0019_[19];
assign _0320_ = _0021_ & _0019_[1];
assign _0321_ = _0021_ & _0019_[20];
assign _0322_ = _0021_ & _0019_[21];
assign _0323_ = _0021_ & _0019_[22];
assign _0324_ = _0021_ & _0019_[23];
assign _0325_ = _0021_ & _0019_[24];
assign _0326_ = _0021_ & _0019_[25];
assign _0327_ = _0021_ & _0019_[26];
assign _0328_ = _0021_ & _0019_[27];
assign _0329_ = _0021_ & _0019_[28];
assign _0330_ = _0021_ & _0019_[29];
assign _0331_ = _0021_ & _0019_[2];
assign _0332_ = _0021_ & _0019_[30];
assign _0333_ = _0021_ & _0019_[31];
assign _0334_ = _0021_ & _0019_[3];
assign _0335_ = _0021_ & _0019_[4];
assign _0336_ = _0021_ & _0019_[5];
assign _0337_ = _0021_ & _0019_[6];
assign _0338_ = _0021_ & _0019_[7];
assign _0339_ = _0021_ & _0019_[8];
assign _0340_ = _0021_ & _0019_[9];
assign _0341_ = _0025_ & _0019_[0];
assign _0342_ = _0025_ & _0019_[10];
assign _0343_ = _0025_ & _0019_[11];
assign _0344_ = _0025_ & _0019_[12];
assign _0345_ = _0025_ & _0019_[13];
assign _0346_ = _0025_ & _0019_[14];
assign _0347_ = _0025_ & _0019_[15];
assign _0348_ = _0025_ & _0019_[16];
assign _0349_ = _0025_ & _0019_[17];
assign _0350_ = _0025_ & _0019_[18];
assign _0351_ = _0025_ & _0019_[19];
assign _0352_ = _0025_ & _0019_[1];
assign _0353_ = _0025_ & _0019_[20];
assign _0354_ = _0025_ & _0019_[21];
assign _0355_ = _0025_ & _0019_[22];
assign _0356_ = _0025_ & _0019_[23];
assign _0357_ = _0025_ & _0019_[24];
assign _0358_ = _0025_ & _0019_[25];
assign _0359_ = _0025_ & _0019_[26];
assign _0360_ = _0025_ & _0019_[27];
assign _0361_ = _0025_ & _0019_[28];
assign _0362_ = _0025_ & _0019_[29];
assign _0363_ = _0025_ & _0019_[2];
assign _0364_ = _0025_ & _0019_[30];
assign _0365_ = _0025_ & _0019_[31];
assign _0366_ = _0025_ & _0019_[3];
assign _0367_ = _0025_ & _0019_[4];
assign _0368_ = _0025_ & _0019_[5];
assign _0369_ = _0025_ & _0019_[6];
assign _0370_ = _0025_ & _0019_[7];
assign _0371_ = _0025_ & _0019_[8];
assign _0372_ = _0025_ & _0019_[9];
assign _0373_ = _0029_ & _0019_[0];
assign _0374_ = _0029_ & _0019_[10];
assign _0375_ = _0029_ & _0019_[11];
assign _0376_ = _0029_ & _0019_[12];
assign _0377_ = _0029_ & _0019_[13];
assign _0378_ = _0029_ & _0019_[14];
assign _0379_ = _0029_ & _0019_[15];
assign _0380_ = _0029_ & _0019_[16];
assign _0381_ = _0029_ & _0019_[17];
assign _0382_ = _0029_ & _0019_[18];
assign _0383_ = _0029_ & _0019_[19];
assign _0384_ = _0029_ & _0019_[1];
assign _0385_ = _0029_ & _0019_[20];
assign _0386_ = _0029_ & _0019_[21];
assign _0387_ = _0029_ & _0019_[22];
assign _0388_ = _0029_ & _0019_[23];
assign _0389_ = _0029_ & _0019_[24];
assign _0390_ = _0029_ & _0019_[25];
assign _0391_ = _0029_ & _0019_[26];
assign _0392_ = _0029_ & _0019_[27];
assign _0393_ = _0029_ & _0019_[28];
assign _0394_ = _0029_ & _0019_[29];
assign _0395_ = _0029_ & _0019_[2];
assign _0396_ = _0029_ & _0019_[30];
assign _0397_ = _0029_ & _0019_[31];
assign _0398_ = _0029_ & _0019_[3];
assign _0399_ = _0029_ & _0019_[4];
assign _0400_ = _0029_ & _0019_[5];
assign _0401_ = _0029_ & _0019_[6];
assign _0402_ = _0029_ & _0019_[7];
assign _0403_ = _0029_ & _0019_[8];
assign _0404_ = _0029_ & _0019_[9];
assign _0405_ = _0149_ ? _0120_[0] : \fifo[0] [0];
assign _0406_ = _0150_ ? _0120_[10] : \fifo[0] [10];
assign _0407_ = _0151_ ? _0120_[11] : \fifo[0] [11];
assign _0408_ = _0152_ ? _0120_[12] : \fifo[0] [12];
assign _0409_ = _0153_ ? _0120_[13] : \fifo[0] [13];
assign _0410_ = _0154_ ? _0120_[14] : \fifo[0] [14];
assign _0411_ = _0155_ ? _0120_[15] : \fifo[0] [15];
assign _0412_ = _0156_ ? _0120_[16] : \fifo[0] [16];
assign _0413_ = _0157_ ? _0120_[17] : \fifo[0] [17];
assign _0414_ = _0158_ ? _0120_[18] : \fifo[0] [18];
assign _0415_ = _0159_ ? _0120_[19] : \fifo[0] [19];
assign _0416_ = _0160_ ? _0120_[1] : \fifo[0] [1];
assign _0417_ = _0161_ ? _0120_[20] : \fifo[0] [20];
assign _0418_ = _0162_ ? _0120_[21] : \fifo[0] [21];
assign _0419_ = _0163_ ? _0120_[22] : \fifo[0] [22];
assign _0420_ = _0164_ ? _0120_[23] : \fifo[0] [23];
assign _0421_ = _0165_ ? _0120_[24] : \fifo[0] [24];
assign _0422_ = _0166_ ? _0120_[25] : \fifo[0] [25];
assign _0423_ = _0167_ ? _0120_[26] : \fifo[0] [26];
assign _0424_ = _0168_ ? _0120_[27] : \fifo[0] [27];
assign _0425_ = _0169_ ? _0120_[28] : \fifo[0] [28];
assign _0426_ = _0170_ ? _0120_[29] : \fifo[0] [29];
assign _0427_ = _0171_ ? _0120_[2] : \fifo[0] [2];
assign _0428_ = _0172_ ? _0120_[30] : \fifo[0] [30];
assign _0429_ = _0173_ ? _0120_[31] : \fifo[0] [31];
assign _0430_ = _0174_ ? _0120_[3] : \fifo[0] [3];
assign _0431_ = _0175_ ? _0120_[4] : \fifo[0] [4];
assign _0432_ = _0176_ ? _0120_[5] : \fifo[0] [5];
assign _0433_ = _0177_ ? _0120_[6] : \fifo[0] [6];
assign _0434_ = _0178_ ? _0120_[7] : \fifo[0] [7];
assign _0435_ = _0179_ ? _0120_[8] : \fifo[0] [8];
assign _0436_ = _0180_ ? _0120_[9] : \fifo[0] [9];
assign _0437_ = _0181_ ? _0120_[0] : \fifo[1] [0];
assign _0438_ = _0182_ ? _0120_[10] : \fifo[1] [10];
assign _0439_ = _0183_ ? _0120_[11] : \fifo[1] [11];
assign _0440_ = _0184_ ? _0120_[12] : \fifo[1] [12];
assign _0441_ = _0185_ ? _0120_[13] : \fifo[1] [13];
assign _0442_ = _0186_ ? _0120_[14] : \fifo[1] [14];
assign _0443_ = _0187_ ? _0120_[15] : \fifo[1] [15];
assign _0444_ = _0188_ ? _0120_[16] : \fifo[1] [16];
assign _0445_ = _0189_ ? _0120_[17] : \fifo[1] [17];
assign _0446_ = _0190_ ? _0120_[18] : \fifo[1] [18];
assign _0447_ = _0191_ ? _0120_[19] : \fifo[1] [19];
assign _0448_ = _0192_ ? _0120_[1] : \fifo[1] [1];
assign _0449_ = _0193_ ? _0120_[20] : \fifo[1] [20];
assign _0450_ = _0194_ ? _0120_[21] : \fifo[1] [21];
assign _0451_ = _0195_ ? _0120_[22] : \fifo[1] [22];
assign _0452_ = _0196_ ? _0120_[23] : \fifo[1] [23];
assign _0453_ = _0197_ ? _0120_[24] : \fifo[1] [24];
assign _0454_ = _0198_ ? _0120_[25] : \fifo[1] [25];
assign _0455_ = _0199_ ? _0120_[26] : \fifo[1] [26];
assign _0456_ = _0200_ ? _0120_[27] : \fifo[1] [27];
assign _0457_ = _0201_ ? _0120_[28] : \fifo[1] [28];
assign _0458_ = _0202_ ? _0120_[29] : \fifo[1] [29];
assign _0459_ = _0203_ ? _0120_[2] : \fifo[1] [2];
assign _0460_ = _0204_ ? _0120_[30] : \fifo[1] [30];
assign _0461_ = _0205_ ? _0120_[31] : \fifo[1] [31];
assign _0462_ = _0206_ ? _0120_[3] : \fifo[1] [3];
assign _0463_ = _0207_ ? _0120_[4] : \fifo[1] [4];
assign _0464_ = _0208_ ? _0120_[5] : \fifo[1] [5];
assign _0465_ = _0209_ ? _0120_[6] : \fifo[1] [6];
assign _0466_ = _0210_ ? _0120_[7] : \fifo[1] [7];
assign _0467_ = _0211_ ? _0120_[8] : \fifo[1] [8];
assign _0468_ = _0212_ ? _0120_[9] : \fifo[1] [9];
assign _0469_ = _0213_ ? _0120_[0] : \fifo[2] [0];
assign _0470_ = _0214_ ? _0120_[10] : \fifo[2] [10];
assign _0471_ = _0215_ ? _0120_[11] : \fifo[2] [11];
assign _0472_ = _0216_ ? _0120_[12] : \fifo[2] [12];
assign _0473_ = _0217_ ? _0120_[13] : \fifo[2] [13];
assign _0474_ = _0218_ ? _0120_[14] : \fifo[2] [14];
assign _0475_ = _0219_ ? _0120_[15] : \fifo[2] [15];
assign _0476_ = _0220_ ? _0120_[16] : \fifo[2] [16];
assign _0477_ = _0221_ ? _0120_[17] : \fifo[2] [17];
assign _0478_ = _0222_ ? _0120_[18] : \fifo[2] [18];
assign _0479_ = _0223_ ? _0120_[19] : \fifo[2] [19];
assign _0480_ = _0224_ ? _0120_[1] : \fifo[2] [1];
assign _0481_ = _0225_ ? _0120_[20] : \fifo[2] [20];
assign _0482_ = _0226_ ? _0120_[21] : \fifo[2] [21];
assign _0483_ = _0227_ ? _0120_[22] : \fifo[2] [22];
assign _0484_ = _0228_ ? _0120_[23] : \fifo[2] [23];
assign _0485_ = _0229_ ? _0120_[24] : \fifo[2] [24];
assign _0486_ = _0230_ ? _0120_[25] : \fifo[2] [25];
assign _0487_ = _0231_ ? _0120_[26] : \fifo[2] [26];
assign _0488_ = _0232_ ? _0120_[27] : \fifo[2] [27];
assign _0489_ = _0233_ ? _0120_[28] : \fifo[2] [28];
assign _0490_ = _0234_ ? _0120_[29] : \fifo[2] [29];
assign _0491_ = _0235_ ? _0120_[2] : \fifo[2] [2];
assign _0492_ = _0236_ ? _0120_[30] : \fifo[2] [30];
assign _0493_ = _0237_ ? _0120_[31] : \fifo[2] [31];
assign _0494_ = _0238_ ? _0120_[3] : \fifo[2] [3];
assign _0495_ = _0239_ ? _0120_[4] : \fifo[2] [4];
assign _0496_ = _0240_ ? _0120_[5] : \fifo[2] [5];
assign _0497_ = _0241_ ? _0120_[6] : \fifo[2] [6];
assign _0498_ = _0242_ ? _0120_[7] : \fifo[2] [7];
assign _0499_ = _0243_ ? _0120_[8] : \fifo[2] [8];
assign _0500_ = _0244_ ? _0120_[9] : \fifo[2] [9];
assign _0501_ = _0245_ ? _0120_[0] : \fifo[3] [0];
assign _0502_ = _0246_ ? _0120_[10] : \fifo[3] [10];
assign _0503_ = _0247_ ? _0120_[11] : \fifo[3] [11];
assign _0504_ = _0248_ ? _0120_[12] : \fifo[3] [12];
assign _0505_ = _0249_ ? _0120_[13] : \fifo[3] [13];
assign _0506_ = _0250_ ? _0120_[14] : \fifo[3] [14];
assign _0507_ = _0251_ ? _0120_[15] : \fifo[3] [15];
assign _0508_ = _0252_ ? _0120_[16] : \fifo[3] [16];
assign _0509_ = _0253_ ? _0120_[17] : \fifo[3] [17];
assign _0510_ = _0254_ ? _0120_[18] : \fifo[3] [18];
assign _0511_ = _0255_ ? _0120_[19] : \fifo[3] [19];
assign _0512_ = _0256_ ? _0120_[1] : \fifo[3] [1];
assign _0513_ = _0257_ ? _0120_[20] : \fifo[3] [20];
assign _0514_ = _0258_ ? _0120_[21] : \fifo[3] [21];
assign _0515_ = _0259_ ? _0120_[22] : \fifo[3] [22];
assign _0516_ = _0260_ ? _0120_[23] : \fifo[3] [23];
assign _0517_ = _0261_ ? _0120_[24] : \fifo[3] [24];
assign _0518_ = _0262_ ? _0120_[25] : \fifo[3] [25];
assign _0519_ = _0263_ ? _0120_[26] : \fifo[3] [26];
assign _0520_ = _0264_ ? _0120_[27] : \fifo[3] [27];
assign _0521_ = _0265_ ? _0120_[28] : \fifo[3] [28];
assign _0522_ = _0266_ ? _0120_[29] : \fifo[3] [29];
assign _0523_ = _0267_ ? _0120_[2] : \fifo[3] [2];
assign _0524_ = _0268_ ? _0120_[30] : \fifo[3] [30];
assign _0525_ = _0269_ ? _0120_[31] : \fifo[3] [31];
assign _0526_ = _0270_ ? _0120_[3] : \fifo[3] [3];
assign _0527_ = _0271_ ? _0120_[4] : \fifo[3] [4];
assign _0528_ = _0272_ ? _0120_[5] : \fifo[3] [5];
assign _0529_ = _0273_ ? _0120_[6] : \fifo[3] [6];
assign _0530_ = _0274_ ? _0120_[7] : \fifo[3] [7];
assign _0531_ = _0275_ ? _0120_[8] : \fifo[3] [8];
assign _0532_ = _0276_ ? _0120_[9] : \fifo[3] [9];
assign _0533_ = _0277_ ? _0120_[0] : \fifo[4] [0];
assign _0534_ = _0278_ ? _0120_[10] : \fifo[4] [10];
assign _0535_ = _0279_ ? _0120_[11] : \fifo[4] [11];
assign _0536_ = _0280_ ? _0120_[12] : \fifo[4] [12];
assign _0537_ = _0281_ ? _0120_[13] : \fifo[4] [13];
assign _0538_ = _0282_ ? _0120_[14] : \fifo[4] [14];
assign _0539_ = _0283_ ? _0120_[15] : \fifo[4] [15];
assign _0540_ = _0284_ ? _0120_[16] : \fifo[4] [16];
assign _0541_ = _0285_ ? _0120_[17] : \fifo[4] [17];
assign _0542_ = _0286_ ? _0120_[18] : \fifo[4] [18];
assign _0543_ = _0287_ ? _0120_[19] : \fifo[4] [19];
assign _0544_ = _0288_ ? _0120_[1] : \fifo[4] [1];
assign _0545_ = _0289_ ? _0120_[20] : \fifo[4] [20];
assign _0546_ = _0290_ ? _0120_[21] : \fifo[4] [21];
assign _0547_ = _0291_ ? _0120_[22] : \fifo[4] [22];
assign _0548_ = _0292_ ? _0120_[23] : \fifo[4] [23];
assign _0549_ = _0293_ ? _0120_[24] : \fifo[4] [24];
assign _0550_ = _0294_ ? _0120_[25] : \fifo[4] [25];
assign _0551_ = _0295_ ? _0120_[26] : \fifo[4] [26];
assign _0552_ = _0296_ ? _0120_[27] : \fifo[4] [27];
assign _0553_ = _0297_ ? _0120_[28] : \fifo[4] [28];
assign _0554_ = _0298_ ? _0120_[29] : \fifo[4] [29];
assign _0555_ = _0299_ ? _0120_[2] : \fifo[4] [2];
assign _0556_ = _0300_ ? _0120_[30] : \fifo[4] [30];
assign _0557_ = _0301_ ? _0120_[31] : \fifo[4] [31];
assign _0558_ = _0302_ ? _0120_[3] : \fifo[4] [3];
assign _0559_ = _0303_ ? _0120_[4] : \fifo[4] [4];
assign _0560_ = _0304_ ? _0120_[5] : \fifo[4] [5];
assign _0561_ = _0305_ ? _0120_[6] : \fifo[4] [6];
assign _0562_ = _0306_ ? _0120_[7] : \fifo[4] [7];
assign _0563_ = _0307_ ? _0120_[8] : \fifo[4] [8];
assign _0564_ = _0308_ ? _0120_[9] : \fifo[4] [9];
assign _0565_ = _0309_ ? _0120_[0] : \fifo[5] [0];
assign _0566_ = _0310_ ? _0120_[10] : \fifo[5] [10];
assign _0567_ = _0311_ ? _0120_[11] : \fifo[5] [11];
assign _0568_ = _0312_ ? _0120_[12] : \fifo[5] [12];
assign _0569_ = _0313_ ? _0120_[13] : \fifo[5] [13];
assign _0570_ = _0314_ ? _0120_[14] : \fifo[5] [14];
assign _0571_ = _0315_ ? _0120_[15] : \fifo[5] [15];
assign _0572_ = _0316_ ? _0120_[16] : \fifo[5] [16];
assign _0573_ = _0317_ ? _0120_[17] : \fifo[5] [17];
assign _0574_ = _0318_ ? _0120_[18] : \fifo[5] [18];
assign _0575_ = _0319_ ? _0120_[19] : \fifo[5] [19];
assign _0576_ = _0320_ ? _0120_[1] : \fifo[5] [1];
assign _0577_ = _0321_ ? _0120_[20] : \fifo[5] [20];
assign _0578_ = _0322_ ? _0120_[21] : \fifo[5] [21];
assign _0579_ = _0323_ ? _0120_[22] : \fifo[5] [22];
assign _0580_ = _0324_ ? _0120_[23] : \fifo[5] [23];
assign _0581_ = _0325_ ? _0120_[24] : \fifo[5] [24];
assign _0582_ = _0326_ ? _0120_[25] : \fifo[5] [25];
assign _0583_ = _0327_ ? _0120_[26] : \fifo[5] [26];
assign _0584_ = _0328_ ? _0120_[27] : \fifo[5] [27];
assign _0585_ = _0329_ ? _0120_[28] : \fifo[5] [28];
assign _0586_ = _0330_ ? _0120_[29] : \fifo[5] [29];
assign _0587_ = _0331_ ? _0120_[2] : \fifo[5] [2];
assign _0588_ = _0332_ ? _0120_[30] : \fifo[5] [30];
assign _0589_ = _0333_ ? _0120_[31] : \fifo[5] [31];
assign _0590_ = _0334_ ? _0120_[3] : \fifo[5] [3];
assign _0591_ = _0335_ ? _0120_[4] : \fifo[5] [4];
assign _0592_ = _0336_ ? _0120_[5] : \fifo[5] [5];
assign _0593_ = _0337_ ? _0120_[6] : \fifo[5] [6];
assign _0594_ = _0338_ ? _0120_[7] : \fifo[5] [7];
assign _0595_ = _0339_ ? _0120_[8] : \fifo[5] [8];
assign _0596_ = _0340_ ? _0120_[9] : \fifo[5] [9];
assign _0597_ = _0341_ ? _0120_[0] : \fifo[6] [0];
assign _0598_ = _0342_ ? _0120_[10] : \fifo[6] [10];
assign _0599_ = _0343_ ? _0120_[11] : \fifo[6] [11];
assign _0600_ = _0344_ ? _0120_[12] : \fifo[6] [12];
assign _0601_ = _0345_ ? _0120_[13] : \fifo[6] [13];
assign _0602_ = _0346_ ? _0120_[14] : \fifo[6] [14];
assign _0603_ = _0347_ ? _0120_[15] : \fifo[6] [15];
assign _0604_ = _0348_ ? _0120_[16] : \fifo[6] [16];
assign _0605_ = _0349_ ? _0120_[17] : \fifo[6] [17];
assign _0606_ = _0350_ ? _0120_[18] : \fifo[6] [18];
assign _0607_ = _0351_ ? _0120_[19] : \fifo[6] [19];
assign _0608_ = _0352_ ? _0120_[1] : \fifo[6] [1];
assign _0609_ = _0353_ ? _0120_[20] : \fifo[6] [20];
assign _0610_ = _0354_ ? _0120_[21] : \fifo[6] [21];
assign _0611_ = _0355_ ? _0120_[22] : \fifo[6] [22];
assign _0612_ = _0356_ ? _0120_[23] : \fifo[6] [23];
assign _0613_ = _0357_ ? _0120_[24] : \fifo[6] [24];
assign _0614_ = _0358_ ? _0120_[25] : \fifo[6] [25];
assign _0615_ = _0359_ ? _0120_[26] : \fifo[6] [26];
assign _0616_ = _0360_ ? _0120_[27] : \fifo[6] [27];
assign _0617_ = _0361_ ? _0120_[28] : \fifo[6] [28];
assign _0618_ = _0362_ ? _0120_[29] : \fifo[6] [29];
assign _0619_ = _0363_ ? _0120_[2] : \fifo[6] [2];
assign _0620_ = _0364_ ? _0120_[30] : \fifo[6] [30];
assign _0621_ = _0365_ ? _0120_[31] : \fifo[6] [31];
assign _0622_ = _0366_ ? _0120_[3] : \fifo[6] [3];
assign _0623_ = _0367_ ? _0120_[4] : \fifo[6] [4];
assign _0624_ = _0368_ ? _0120_[5] : \fifo[6] [5];
assign _0625_ = _0369_ ? _0120_[6] : \fifo[6] [6];
assign _0626_ = _0370_ ? _0120_[7] : \fifo[6] [7];
assign _0627_ = _0371_ ? _0120_[8] : \fifo[6] [8];
assign _0628_ = _0372_ ? _0120_[9] : \fifo[6] [9];
assign _0629_ = _0373_ ? _0120_[0] : \fifo[7] [0];
assign _0630_ = _0374_ ? _0120_[10] : \fifo[7] [10];
assign _0631_ = _0375_ ? _0120_[11] : \fifo[7] [11];
assign _0632_ = _0376_ ? _0120_[12] : \fifo[7] [12];
assign _0633_ = _0377_ ? _0120_[13] : \fifo[7] [13];
assign _0634_ = _0378_ ? _0120_[14] : \fifo[7] [14];
assign _0635_ = _0379_ ? _0120_[15] : \fifo[7] [15];
assign _0636_ = _0380_ ? _0120_[16] : \fifo[7] [16];
assign _0637_ = _0381_ ? _0120_[17] : \fifo[7] [17];
assign _0638_ = _0382_ ? _0120_[18] : \fifo[7] [18];
assign _0639_ = _0383_ ? _0120_[19] : \fifo[7] [19];
assign _0640_ = _0384_ ? _0120_[1] : \fifo[7] [1];
assign _0641_ = _0385_ ? _0120_[20] : \fifo[7] [20];
assign _0642_ = _0386_ ? _0120_[21] : \fifo[7] [21];
assign _0643_ = _0387_ ? _0120_[22] : \fifo[7] [22];
assign _0644_ = _0388_ ? _0120_[23] : \fifo[7] [23];
assign _0645_ = _0389_ ? _0120_[24] : \fifo[7] [24];
assign _0646_ = _0390_ ? _0120_[25] : \fifo[7] [25];
assign _0647_ = _0391_ ? _0120_[26] : \fifo[7] [26];
assign _0648_ = _0392_ ? _0120_[27] : \fifo[7] [27];
assign _0649_ = _0393_ ? _0120_[28] : \fifo[7] [28];
assign _0650_ = _0394_ ? _0120_[29] : \fifo[7] [29];
assign _0651_ = _0395_ ? _0120_[2] : \fifo[7] [2];
assign _0652_ = _0396_ ? _0120_[30] : \fifo[7] [30];
assign _0653_ = _0397_ ? _0120_[31] : \fifo[7] [31];
assign _0654_ = _0398_ ? _0120_[3] : \fifo[7] [3];
assign _0655_ = _0399_ ? _0120_[4] : \fifo[7] [4];
assign _0656_ = _0400_ ? _0120_[5] : \fifo[7] [5];
assign _0657_ = _0401_ ? _0120_[6] : \fifo[7] [6];
assign _0658_ = _0402_ ? _0120_[7] : \fifo[7] [7];
assign _0659_ = _0403_ ? _0120_[8] : \fifo[7] [8];
assign _0660_ = _0404_ ? _0120_[9] : \fifo[7] [9];
always @(posedge clk)
\fifo[0] <= _0661_;
always @(posedge clk)
\fifo[1] <= _0662_;
always @(posedge clk)
\fifo[2] <= _0663_;
always @(posedge clk)
\fifo[3] <= _0664_;
always @(posedge clk)
\fifo[4] <= _0665_;
always @(posedge clk)
\fifo[5] <= _0666_;
always @(posedge clk)
\fifo[6] <= _0667_;
always @(posedge clk)
\fifo[7] <= _0668_;
assign _0672_ = ~ (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:133.14-133.19" *) full;
assign empty = ~ (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:137.16-137.23" *) _0671_;
assign _0673_ = ~ (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:170.15-170.20" *) full;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:125.1-135.4" *)
always @(posedge clk, posedge reset)
if (reset) write_pointer <= 3'h0;
else write_pointer <= _0008_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:113.1-123.4" *)
always @(posedge clk, posedge reset)
if (reset) read_pointer <= 3'h0;
else read_pointer <= _0007_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:97.1-110.4" *)
always @(posedge clk, posedge reset)
if (reset) cnt <= 4'h0;
else cnt <= _0005_;
(* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:175.3-181.6" *)
always @(posedge clk)
data_out <= _0006_;
assign _0006_ = clear ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:177.8-177.13|../../../cases/eth_fifo/rtl/eth_fifo.v:177.5-180.38" *) _0669_ : _0670_;
assign _0674_ = _0018_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:170.7-170.20|../../../cases/eth_fifo/rtl/eth_fifo.v:170.4-171.38" *) 32'd4294967295 : 32'd0;
assign _0011_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) 32'hxxxxxxxx : _0674_;
assign _0675_ = _0018_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:170.7-170.20|../../../cases/eth_fifo/rtl/eth_fifo.v:170.4-171.38" *) data_in : 32'hxxxxxxxx;
assign _0010_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) 32'hxxxxxxxx : _0675_;
assign _0676_ = _0018_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:170.7-170.20|../../../cases/eth_fifo/rtl/eth_fifo.v:170.4-171.38" *) write_pointer : 3'hx;
assign _0009_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) 3'hx : _0676_;
assign _0001_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) 32'd4294967295 : 32'd0;
assign _0000_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) data_in : 32'hxxxxxxxx;
assign _0004_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) 32'd0 : _0011_;
assign _0003_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) 32'hxxxxxxxx : _0010_;
assign _0002_ = _0017_ ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:167.8-167.21|../../../cases/eth_fifo/rtl/eth_fifo.v:167.5-171.38" *) 3'hx : _0009_;
assign _0677_ = _0016_ ? (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:133.6-133.19|../../../cases/eth_fifo/rtl/eth_fifo.v:133.3-134.43" *) _0014_ : write_pointer;
assign _0008_ = clear ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:130.6-130.11|../../../cases/eth_fifo/rtl/eth_fifo.v:130.3-134.43" *) { 2'h0, write } : _0677_;
assign _0678_ = _0015_ ? (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:121.6-121.19|../../../cases/eth_fifo/rtl/eth_fifo.v:121.3-122.41" *) _0013_ : read_pointer;
assign _0007_ = clear ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:118.6-118.11|../../../cases/eth_fifo/rtl/eth_fifo.v:118.3-122.41" *) { 2'h0, read } : _0678_;
assign _0679_ = read ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:106.8-106.12|../../../cases/eth_fifo/rtl/eth_fifo.v:106.5-109.22" *) _0682_[3:0] : _0012_[3:0];
assign _0680_ = _0681_ ? (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:105.6-105.18|../../../cases/eth_fifo/rtl/eth_fifo.v:105.3-109.22" *) _0679_ : cnt;
assign _0005_ = clear ? (* full_case = 32'd1 *) (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:102.6-102.11|../../../cases/eth_fifo/rtl/eth_fifo.v:102.3-109.22" *) { 3'h0, _0683_ } : _0680_;
assign almost_full = & (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:140.23-140.42" *) cnt[2:0];
assign _0671_ = | (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:137.18-137.22" *) cnt;
assign _0682_ = cnt - (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:107.14-107.21" *) 32'd1;
assign _0683_ = read ^ (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:103.37-103.47" *) write;
assign _0681_ = read ^ (* src = "../../../cases/eth_fifo/rtl/eth_fifo.v:105.6-105.18" *) write;
assign _0127_ = \fifo[0] ;
assign _0128_ = \fifo[1] ;
assign _0129_ = \fifo[2] ;
assign _0130_ = \fifo[3] ;
assign _0131_ = \fifo[4] ;
assign _0132_ = \fifo[5] ;
assign _0133_ = \fifo[6] ;
assign _0134_ = \fifo[7] ;
assign _0141_ = \fifo[0] ;
assign _0142_ = \fifo[1] ;
assign _0143_ = \fifo[2] ;
assign _0144_ = \fifo[3] ;
assign _0145_ = \fifo[4] ;
assign _0146_ = \fifo[5] ;
assign _0147_ = \fifo[6] ;
assign _0148_ = \fifo[7] ;
assign _0661_ = { _0429_, _0428_, _0426_, _0425_, _0424_, _0423_, _0422_, _0421_, _0420_, _0419_, _0418_, _0417_, _0415_, _0414_, _0413_, _0412_, _0411_, _0410_, _0409_, _0408_, _0407_, _0406_, _0436_, _0435_, _0434_, _0433_, _0432_, _0431_, _0430_, _0427_, _0416_, _0405_ };
assign _0662_ = { _0461_, _0460_, _0458_, _0457_, _0456_, _0455_, _0454_, _0453_, _0452_, _0451_, _0450_, _0449_, _0447_, _0446_, _0445_, _0444_, _0443_, _0442_, _0441_, _0440_, _0439_, _0438_, _0468_, _0467_, _0466_, _0465_, _0464_, _0463_, _0462_, _0459_, _0448_, _0437_ };
assign _0663_ = { _0493_, _0492_, _0490_, _0489_, _0488_, _0487_, _0486_, _0485_, _0484_, _0483_, _0482_, _0481_, _0479_, _0478_, _0477_, _0476_, _0475_, _0474_, _0473_, _0472_, _0471_, _0470_, _0500_, _0499_, _0498_, _0497_, _0496_, _0495_, _0494_, _0491_, _0480_, _0469_ };
assign _0664_ = { _0525_, _0524_, _0522_, _0521_, _0520_, _0519_, _0518_, _0517_, _0516_, _0515_, _0514_, _0513_, _0511_, _0510_, _0509_, _0508_, _0507_, _0506_, _0505_, _0504_, _0503_, _0502_, _0532_, _0531_, _0530_, _0529_, _0528_, _0527_, _0526_, _0523_, _0512_, _0501_ };
assign _0665_ = { _0557_, _0556_, _0554_, _0553_, _0552_, _0551_, _0550_, _0549_, _0548_, _0547_, _0546_, _0545_, _0543_, _0542_, _0541_, _0540_, _0539_, _0538_, _0537_, _0536_, _0535_, _0534_, _0564_, _0563_, _0562_, _0561_, _0560_, _0559_, _0558_, _0555_, _0544_, _0533_ };
assign _0666_ = { _0589_, _0588_, _0586_, _0585_, _0584_, _0583_, _0582_, _0581_, _0580_, _0579_, _0578_, _0577_, _0575_, _0574_, _0573_, _0572_, _0571_, _0570_, _0569_, _0568_, _0567_, _0566_, _0596_, _0595_, _0594_, _0593_, _0592_, _0591_, _0590_, _0587_, _0576_, _0565_ };
assign _0667_ = { _0621_, _0620_, _0618_, _0617_, _0616_, _0615_, _0614_, _0613_, _0612_, _0611_, _0610_, _0609_, _0607_, _0606_, _0605_, _0604_, _0603_, _0602_, _0601_, _0600_, _0599_, _0598_, _0628_, _0627_, _0626_, _0625_, _0624_, _0623_, _0622_, _0619_, _0608_, _0597_ };
assign _0668_ = { _0653_, _0652_, _0650_, _0649_, _0648_, _0647_, _0646_, _0645_, _0644_, _0643_, _0642_, _0641_, _0639_, _0638_, _0637_, _0636_, _0635_, _0634_, _0633_, _0632_, _0631_, _0630_, _0660_, _0659_, _0658_, _0657_, _0656_, _0655_, _0654_, _0651_, _0640_, _0629_ };
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data_clean/Led_ast_clean.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
module led_chaser(clk, rst, led);
wire [7:0] _0_;
input clk;
wire clk;
output [7:0] led;
reg [7:0] led;
input rst;
wire rst;
always @(posedge clk)
led <= _0_;
assign _0_ = rst ? 8'h01 : { led[6:0], led[7] };
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data_clean/test_ast_clean.v 0 → 100644
/* Generated by Yosys 0.33 (git sha1 2584903a060) */
module soc_design_JTAG_sim_scfifo_r(clk, fifo_rd, rst_n, fifo_EF, fifo_rdata, rfifo_full, rfifo_used);
wire [31:0] _00_;
wire _01_;
wire [31:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
reg [31:0] bytes_left;
input clk;
wire clk;
output fifo_EF;
wire fifo_EF;
input fifo_rd;
wire fifo_rd;
reg fifo_rd_d;
output [7:0] fifo_rdata;
wire [7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [6:0] rfifo_entries;
output rfifo_full;
wire rfifo_full;
output [5:0] rfifo_used;
wire [5:0] rfifo_used;
input rst_n;
wire rst_n;
assign fifo_EF = ! bytes_left;
assign rfifo_full = bytes_left > 7'h40;
always @(posedge clk)
bytes_left <= _00_;
always @(posedge clk)
fifo_rd_d <= _01_;
assign _02_ = fifo_rd_d ? _03_ : bytes_left;
assign _00_ = rst_n ? _02_ : 32'd0;
assign _01_ = rst_n ? fifo_rd : 1'h0;
assign _03_ = bytes_left - 1'h1;
assign { _04_[31:7], rfifo_entries[6], rfifo_used } = rfifo_full ? 32'd64 : bytes_left;
assign _04_[6:0] = { rfifo_entries[6], rfifo_used };
assign fifo_rdata = 8'h00;
assign new_rom = 1'h0;
assign num_bytes = 32'd0;
assign rfifo_entries[5:0] = rfifo_used;
endmodule
thirdparty/RTL2CDFG/v2cdfg/tmp/yosys_output_data_clean/timescale_ast_clean.v 0 → 100644
/* Generated by Yosys 0.57+178 (git sha1 93dca50b9, clang++ 18.1.8 -fPIC -O3) */
module eth_fifo(data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
reg [31:0] data_out;
input clk;
wire clk;
input reset;
wire reset;
input write;
wire write;
input read;
wire read;
input clear;
wire clear;
output almost_full;
wire almost_full;
output full;
wire full;
output almost_empty;
wire almost_empty;
output empty;
wire empty;
output [3:0] cnt;
reg [3:0] cnt;
wire [31:0] _0000_;
wire [31:0] _0001_;
wire [2:0] _0002_;
wire [31:0] _0003_;
wire [31:0] _0004_;
wire [3:0] _0005_;
wire [31:0] _0006_;
wire [2:0] _0007_;
wire [2:0] _0008_;
wire [2:0] _0009_;
wire [31:0] _0010_;
wire [31:0] _0011_;
wire [31:0] _0012_;
wire [2:0] _0013_;
wire [2:0] _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire [31:0] _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire [31:0] _0119_;
wire [31:0] _0120_;
wire [31:0] _0121_;
wire [31:0] _0122_;
wire [31:0] _0123_;
wire [31:0] _0124_;
wire [31:0] _0125_;
wire [31:0] _0126_;
wire [31:0] _0127_;
wire [31:0] _0128_;
wire [31:0] _0129_;
wire [31:0] _0130_;
wire [31:0] _0131_;
wire [31:0] _0132_;
wire [31:0] _0133_;
wire [31:0] _0134_;
wire [31:0] _0135_;
wire [31:0] _0136_;
wire [31:0] _0137_;
wire [31:0] _0138_;
wire [31:0] _0139_;
wire [31:0] _0140_;
wire [31:0] _0141_;
wire [31:0] _0142_;
wire [31:0] _0143_;
wire [31:0] _0144_;
wire [31:0] _0145_;
wire [31:0] _0146_;
wire [31:0] _0147_;
wire [31:0] _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
wire _0654_;
wire _0655_;
wire _0656_;
wire _0657_;
wire _0658_;
wire _0659_;
wire _0660_;
wire [31:0] _0661_;
wire [31:0] _0662_;
wire [31:0] _0663_;
wire [31:0] _0664_;
wire [31:0] _0665_;
wire [31:0] _0666_;
wire [31:0] _0667_;
wire [31:0] _0668_;
wire [31:0] _0669_;
wire [31:0] _0670_;
wire _0671_;
wire _0672_;
wire _0673_;
wire [31:0] _0674_;
wire [31:0] _0675_;
wire [2:0] _0676_;
wire [2:0] _0677_;
wire [2:0] _0678_;
wire [3:0] _0679_;
wire [3:0] _0680_;
wire _0681_;
wire [31:0] _0682_;
wire _0683_;
reg [31:0] \fifo[0] ;
reg [31:0] \fifo[1] ;
reg [31:0] \fifo[2] ;
reg [31:0] \fifo[3] ;
reg [31:0] \fifo[4] ;
reg [31:0] \fifo[5] ;
reg [31:0] \fifo[6] ;
reg [31:0] \fifo[7] ;
reg [2:0] read_pointer;
reg [2:0] write_pointer;
assign _0012_ = cnt + 32'd1;
assign _0013_ = read_pointer + 1'h1;
assign _0014_ = write_pointer + 1'h1;
assign _0015_ = read & _0671_;
assign _0016_ = write & _0672_;
assign _0017_ = write & clear;
assign _0018_ = write & _0673_;
assign _0084_ = _0119_[0] == 1'h0;
assign _0085_ = _0119_[1] == 1'h0;
assign _0086_ = _0119_[2] == 1'h0;
assign _0087_ = _0119_[3] == 1'h0;
assign _0088_ = _0119_[4] == 1'h0;
assign _0089_ = _0119_[5] == 1'h0;
assign _0090_ = _0119_[6] == 1'h0;
assign _0091_ = _0119_[7] == 1'h0;
assign _0092_ = _0119_[8] == 1'h0;
assign _0093_ = _0119_[9] == 1'h0;
assign _0094_ = _0119_[10] == 1'h0;
assign _0095_ = _0119_[11] == 1'h0;
assign _0096_ = _0119_[12] == 1'h0;
assign _0097_ = _0119_[13] == 1'h0;
assign _0098_ = _0119_[14] == 1'h0;
assign _0099_ = _0119_[15] == 1'h0;
assign _0100_ = _0119_[16] == 1'h0;
assign _0101_ = _0119_[17] == 1'h0;
assign _0102_ = _0119_[18] == 1'h0;
assign _0103_ = _0119_[19] == 1'h0;
assign _0104_ = _0119_[20] == 1'h0;
assign _0105_ = _0119_[21] == 1'h0;
assign _0106_ = _0119_[22] == 1'h0;
assign _0107_ = _0119_[23] == 1'h0;
assign _0108_ = _0119_[24] == 1'h0;
assign _0109_ = _0119_[25] == 1'h0;
assign _0110_ = _0119_[26] == 1'h0;
assign _0111_ = _0119_[27] == 1'h0;
assign _0112_ = _0119_[28] == 1'h0;
assign _0113_ = _0119_[29] == 1'h0;
assign _0114_ = _0119_[30] == 1'h0;
assign _0115_ = _0119_[31] == 1'h0;
assign _0116_ = _0119_[0] == 1'h1;
assign _0117_ = _0119_[1] == 1'h1;
assign _0118_ = _0119_[2] == 1'h1;
assign _0021_ = _0083_ & _0059_;
assign _0022_ = _0066_ & _0076_;
assign _0023_ = _0022_ & _0035_;
assign _0024_ = _0023_ & _0043_;
assign _0025_ = _0024_ & _0059_;
assign _0026_ = _0071_ & _0076_;
assign _0027_ = _0026_ & _0035_;
assign _0028_ = _0027_ & _0043_;
assign _0029_ = _0028_ & _0059_;
assign _0030_ = _0084_ & _0085_;
assign _0031_ = _0086_ & _0087_;
assign _0032_ = _0030_ & _0031_;
assign _0033_ = _0088_ & _0089_;
assign _0034_ = _0090_ & _0091_;
assign _0035_ = _0033_ & _0034_;
assign _0036_ = _0032_ & _0035_;
assign _0037_ = _0092_ & _0093_;
assign _0038_ = _0094_ & _0095_;
assign _0039_ = _0037_ & _0038_;
assign _0040_ = _0096_ & _0097_;
assign _0041_ = _0098_ & _0099_;
assign _0042_ = _0040_ & _0041_;
assign _0043_ = _0039_ & _0042_;
assign _0044_ = _0036_ & _0043_;
assign _0045_ = _0100_ & _0101_;
assign _0046_ = _0102_ & _0103_;
assign _0047_ = _0045_ & _0046_;
assign _0048_ = _0104_ & _0105_;
assign _0049_ = _0106_ & _0107_;
assign _0050_ = _0048_ & _0049_;
assign _0051_ = _0047_ & _0050_;
assign _0052_ = _0108_ & _0109_;
assign _0053_ = _0110_ & _0111_;
assign _0054_ = _0052_ & _0053_;
assign _0055_ = _0112_ & _0113_;
assign _0056_ = _0114_ & _0115_;
assign _0057_ = _0055_ & _0056_;
assign _0058_ = _0054_ & _0057_;
assign _0059_ = _0051_ & _0058_;
assign _0060_ = _0044_ & _0059_;
assign _0061_ = _0116_ & _0085_;
assign _0062_ = _0061_ & _0031_;
assign _0063_ = _0062_ & _0035_;
assign _0064_ = _0063_ & _0043_;
assign _0065_ = _0064_ & _0059_;
assign _0066_ = _0084_ & _0117_;
assign _0067_ = _0066_ & _0031_;
assign _0068_ = _0067_ & _0035_;
assign _0069_ = _0068_ & _0043_;
assign _0070_ = _0069_ & _0059_;
assign _0071_ = _0116_ & _0117_;
assign _0072_ = _0071_ & _0031_;
assign _0073_ = _0072_ & _0035_;
assign _0074_ = _0073_ & _0043_;
assign _0075_ = _0074_ & _0059_;
assign _0076_ = _0118_ & _0087_;
assign _0077_ = _0030_ & _0076_;
assign _0078_ = _0077_ & _0035_;
assign _0079_ = _0078_ & _0043_;
assign _0080_ = _0079_ & _0059_;
assign _0081_ = _0061_ & _0076_;
assign _0082_ = _0081_ & _0035_;
assign _0083_ = _0082_ & _0043_;
assign _0020_ = | _0004_;
assign _0119_ = _0020_ ? { 29'h00000000, _0002_ } : 32'd0;
assign _0120_ = _0020_ ? _0003_ : _0000_;
assign _0019_ = _0020_ ? _0004_ : _0001_;
assign almost_empty = cnt == 4'h1;
assign full = cnt == 4'h8;
assign _0670_ = read_pointer[2] ? _0122_ : _0121_;
assign _0121_ = read_pointer[1] ? _0124_ : _0123_;
assign _0122_ = read_pointer[1] ? _0126_ : _0125_;
assign _0123_ = read_pointer[0] ? _0128_ : _0127_;
assign _0124_ = read_pointer[0] ? _0130_ : _0129_;
assign _0125_ = read_pointer[0] ? _0132_ : _0131_;
assign _0126_ = read_pointer[0] ? _0134_ : _0133_;
assign _0669_ = 1'h0 ? _0136_ : _0135_;
assign _0135_ = 1'h0 ? _0138_ : _0137_;
assign _0136_ = 1'h0 ? _0140_ : _0139_;
assign _0137_ = 1'h0 ? _0142_ : _0141_;
assign _0138_ = 1'h0 ? _0144_ : _0143_;
assign _0139_ = 1'h0 ? _0146_ : _0145_;
assign _0140_ = 1'h0 ? _0148_ : _0147_;
assign _0149_ = _0060_ & _0019_[0];
assign _0150_ = _0060_ & _0019_[10];
assign _0151_ = _0060_ & _0019_[11];
assign _0152_ = _0060_ & _0019_[12];
assign _0153_ = _0060_ & _0019_[13];
assign _0154_ = _0060_ & _0019_[14];
assign _0155_ = _0060_ & _0019_[15];
assign _0156_ = _0060_ & _0019_[16];
assign _0157_ = _0060_ & _0019_[17];
assign _0158_ = _0060_ & _0019_[18];
assign _0159_ = _0060_ & _0019_[19];
assign _0160_ = _0060_ & _0019_[1];
assign _0161_ = _0060_ & _0019_[20];
assign _0162_ = _0060_ & _0019_[21];
assign _0163_ = _0060_ & _0019_[22];
assign _0164_ = _0060_ & _0019_[23];
assign _0165_ = _0060_ & _0019_[24];
assign _0166_ = _0060_ & _0019_[25];
assign _0167_ = _0060_ & _0019_[26];
assign _0168_ = _0060_ & _0019_[27];
assign _0169_ = _0060_ & _0019_[28];
assign _0170_ = _0060_ & _0019_[29];
assign _0171_ = _0060_ & _0019_[2];
assign _0172_ = _0060_ & _0019_[30];
assign _0173_ = _0060_ & _0019_[31];
assign _0174_ = _0060_ & _0019_[3];
assign _0175_ = _0060_ & _0019_[4];
assign _0176_ = _0060_ & _0019_[5];
assign _0177_ = _0060_ & _0019_[6];
assign _0178_ = _0060_ & _0019_[7];
assign _0179_ = _0060_ & _0019_[8];
assign _0180_ = _0060_ & _0019_[9];
assign _0181_ = _0065_ & _0019_[0];
assign _0182_ = _0065_ & _0019_[10];
assign _0183_ = _0065_ & _0019_[11];
assign _0184_ = _0065_ & _0019_[12];
assign _0185_ = _0065_ & _0019_[13];
assign _0186_ = _0065_ & _0019_[14];
assign _0187_ = _0065_ & _0019_[15];
assign _0188_ = _0065_ & _0019_[16];
assign _0189_ = _0065_ & _0019_[17];
assign _0190_ = _0065_ & _0019_[18];
assign _0191_ = _0065_ & _0019_[19];
assign _0192_ = _0065_ & _0019_[1];
assign _0193_ = _0065_ & _0019_[20];
assign _0194_ = _0065_ & _0019_[21];
assign _0195_ = _0065_ & _0019_[22];
assign _0196_ = _0065_ & _0019_[23];
assign _0197_ = _0065_ & _0019_[24];
assign _0198_ = _0065_ & _0019_[25];
assign _0199_ = _0065_ & _0019_[26];
assign _0200_ = _0065_ & _0019_[27];
assign _0201_ = _0065_ & _0019_[28];
assign _0202_ = _0065_ & _0019_[29];
assign _0203_ = _0065_ & _0019_[2];
assign _0204_ = _0065_ & _0019_[30];
assign _0205_ = _0065_ & _0019_[31];
assign _0206_ = _0065_ & _0019_[3];
assign _0207_ = _0065_ & _0019_[4];
assign _0208_ = _0065_ & _0019_[5];
assign _0209_ = _0065_ & _0019_[6];
assign _0210_ = _0065_ & _0019_[7];
assign _0211_ = _0065_ & _0019_[8];
assign _0212_ = _0065_ & _0019_[9];
assign _0213_ = _0070_ & _0019_[0];
assign _0214_ = _0070_ & _0019_[10];
assign _0215_ = _0070_ & _0019_[11];
assign _0216_ = _0070_ & _0019_[12];
assign _0217_ = _0070_ & _0019_[13];
assign _0218_ = _0070_ & _0019_[14];
assign _0219_ = _0070_ & _0019_[15];
assign _0220_ = _0070_ & _0019_[16];
assign _0221_ = _0070_ & _0019_[17];
assign _0222_ = _0070_ & _0019_[18];
assign _0223_ = _0070_ & _0019_[19];
assign _0224_ = _0070_ & _0019_[1];
assign _0225_ = _0070_ & _0019_[20];
assign _0226_ = _0070_ & _0019_[21];
assign _0227_ = _0070_ & _0019_[22];
assign _0228_ = _0070_ & _0019_[23];
assign _0229_ = _0070_ & _0019_[24];
assign _0230_ = _0070_ & _0019_[25];
assign _0231_ = _0070_ & _0019_[26];
assign _0232_ = _0070_ & _0019_[27];
assign _0233_ = _0070_ & _0019_[28];
assign _0234_ = _0070_ & _0019_[29];
assign _0235_ = _0070_ & _0019_[2];
assign _0236_ = _0070_ & _0019_[30];
assign _0237_ = _0070_ & _0019_[31];
assign _0238_ = _0070_ & _0019_[3];
assign _0239_ = _0070_ & _0019_[4];
assign _0240_ = _0070_ & _0019_[5];
assign _0241_ = _0070_ & _0019_[6];
assign _0242_ = _0070_ & _0019_[7];
assign _0243_ = _0070_ & _0019_[8];
assign _0244_ = _0070_ & _0019_[9];
assign _0245_ = _0075_ & _0019_[0];
assign _0246_ = _0075_ & _0019_[10];
assign _0247_ = _0075_ & _0019_[11];
assign _0248_ = _0075_ & _0019_[12];
assign _0249_ = _0075_ & _0019_[13];
assign _0250_ = _0075_ & _0019_[14];
assign _0251_ = _0075_ & _0019_[15];
assign _0252_ = _0075_ & _0019_[16];
assign _0253_ = _0075_ & _0019_[17];
assign _0254_ = _0075_ & _0019_[18];
assign _0255_ = _0075_ & _0019_[19];
assign _0256_ = _0075_ & _0019_[1];
assign _0257_ = _0075_ & _0019_[20];
assign _0258_ = _0075_ & _0019_[21];
assign _0259_ = _0075_ & _0019_[22];
assign _0260_ = _0075_ & _0019_[23];
assign _0261_ = _0075_ & _0019_[24];
assign _0262_ = _0075_ & _0019_[25];
assign _0263_ = _0075_ & _0019_[26];
assign _0264_ = _0075_ & _0019_[27];
assign _0265_ = _0075_ & _0019_[28];
assign _0266_ = _0075_ & _0019_[29];
assign _0267_ = _0075_ & _0019_[2];
assign _0268_ = _0075_ & _0019_[30];
assign _0269_ = _0075_ & _0019_[31];
assign _0270_ = _0075_ & _0019_[3];
assign _0271_ = _0075_ & _0019_[4];
assign _0272_ = _0075_ & _0019_[5];
assign _0273_ = _0075_ & _0019_[6];
assign _0274_ = _0075_ & _0019_[7];
assign _0275_ = _0075_ & _0019_[8];
assign _0276_ = _0075_ & _0019_[9];
assign _0277_ = _0080_ & _0019_[0];
assign _0278_ = _0080_ & _0019_[10];
assign _0279_ = _0080_ & _0019_[11];
assign _0280_ = _0080_ & _0019_[12];
assign _0281_ = _0080_ & _0019_[13];
assign _0282_ = _0080_ & _0019_[14];
assign _0283_ = _0080_ & _0019_[15];
assign _0284_ = _0080_ & _0019_[16];
assign _0285_ = _0080_ & _0019_[17];
assign _0286_ = _0080_ & _0019_[18];
assign _0287_ = _0080_ & _0019_[19];
assign _0288_ = _0080_ & _0019_[1];
assign _0289_ = _0080_ & _0019_[20];
assign _0290_ = _0080_ & _0019_[21];
assign _0291_ = _0080_ & _0019_[22];
assign _0292_ = _0080_ & _0019_[23];
assign _0293_ = _0080_ & _0019_[24];
assign _0294_ = _0080_ & _0019_[25];
assign _0295_ = _0080_ & _0019_[26];
assign _0296_ = _0080_ & _0019_[27];
assign _0297_ = _0080_ & _0019_[28];
assign _0298_ = _0080_ & _0019_[29];
assign _0299_ = _0080_ & _0019_[2];
assign _0300_ = _0080_ & _0019_[30];
assign _0301_ = _0080_ & _0019_[31];
assign _0302_ = _0080_ & _0019_[3];
assign _0303_ = _0080_ & _0019_[4];
assign _0304_ = _0080_ & _0019_[5];
assign _0305_ = _0080_ & _0019_[6];
assign _0306_ = _0080_ & _0019_[7];
assign _0307_ = _0080_ & _0019_[8];
assign _0308_ = _0080_ & _0019_[9];
assign _0309_ = _0021_ & _0019_[0];
assign _0310_ = _0021_ & _0019_[10];
assign _0311_ = _0021_ & _0019_[11];
assign _0312_ = _0021_ & _0019_[12];
assign _0313_ = _0021_ & _0019_[13];
assign _0314_ = _0021_ & _0019_[14];
assign _0315_ = _0021_ & _0019_[15];
assign _0316_ = _0021_ & _0019_[16];
assign _0317_ = _0021_ & _0019_[17];
assign _0318_ = _0021_ & _0019_[18];
assign _0319_ = _0021_ & _0019_[19];
assign _0320_ = _0021_ & _0019_[1];
assign _0321_ = _0021_ & _0019_[20];
assign _0322_ = _0021_ & _0019_[21];
assign _0323_ = _0021_ & _0019_[22];
assign _0324_ = _0021_ & _0019_[23];
assign _0325_ = _0021_ & _0019_[24];
assign _0326_ = _0021_ & _0019_[25];
assign _0327_ = _0021_ & _0019_[26];
assign _0328_ = _0021_ & _0019_[27];
assign _0329_ = _0021_ & _0019_[28];
assign _0330_ = _0021_ & _0019_[29];
assign _0331_ = _0021_ & _0019_[2];
assign _0332_ = _0021_ & _0019_[30];
assign _0333_ = _0021_ & _0019_[31];
assign _0334_ = _0021_ & _0019_[3];
assign _0335_ = _0021_ & _0019_[4];
assign _0336_ = _0021_ & _0019_[5];
assign _0337_ = _0021_ & _0019_[6];
assign _0338_ = _0021_ & _0019_[7];
assign _0339_ = _0021_ & _0019_[8];
assign _0340_ = _0021_ & _0019_[9];
assign _0341_ = _0025_ & _0019_[0];
assign _0342_ = _0025_ & _0019_[10];
assign _0343_ = _0025_ & _0019_[11];
assign _0344_ = _0025_ & _0019_[12];
assign _0345_ = _0025_ & _0019_[13];
assign _0346_ = _0025_ & _0019_[14];
assign _0347_ = _0025_ & _0019_[15];
assign _0348_ = _0025_ & _0019_[16];
assign _0349_ = _0025_ & _0019_[17];
assign _0350_ = _0025_ & _0019_[18];
assign _0351_ = _0025_ & _0019_[19];
assign _0352_ = _0025_ & _0019_[1];
assign _0353_ = _0025_ & _0019_[20];
assign _0354_ = _0025_ & _0019_[21];
assign _0355_ = _0025_ & _0019_[22];
assign _0356_ = _0025_ & _0019_[23];
assign _0357_ = _0025_ & _0019_[24];
assign _0358_ = _0025_ & _0019_[25];
assign _0359_ = _0025_ & _0019_[26];
assign _0360_ = _0025_ & _0019_[27];
assign _0361_ = _0025_ & _0019_[28];
assign _0362_ = _0025_ & _0019_[29];
assign _0363_ = _0025_ & _0019_[2];
assign _0364_ = _0025_ & _0019_[30];
assign _0365_ = _0025_ & _0019_[31];
assign _0366_ = _0025_ & _0019_[3];
assign _0367_ = _0025_ & _0019_[4];
assign _0368_ = _0025_ & _0019_[5];
assign _0369_ = _0025_ & _0019_[6];
assign _0370_ = _0025_ & _0019_[7];
assign _0371_ = _0025_ & _0019_[8];
assign _0372_ = _0025_ & _0019_[9];
assign _0373_ = _0029_ & _0019_[0];
assign _0374_ = _0029_ & _0019_[10];
assign _0375_ = _0029_ & _0019_[11];
assign _0376_ = _0029_ & _0019_[12];
assign _0377_ = _0029_ & _0019_[13];
assign _0378_ = _0029_ & _0019_[14];
assign _0379_ = _0029_ & _0019_[15];
assign _0380_ = _0029_ & _0019_[16];
assign _0381_ = _0029_ & _0019_[17];
assign _0382_ = _0029_ & _0019_[18];
assign _0383_ = _0029_ & _0019_[19];
assign _0384_ = _0029_ & _0019_[1];
assign _0385_ = _0029_ & _0019_[20];
assign _0386_ = _0029_ & _0019_[21];
assign _0387_ = _0029_ & _0019_[22];
assign _0388_ = _0029_ & _0019_[23];
assign _0389_ = _0029_ & _0019_[24];
assign _0390_ = _0029_ & _0019_[25];
assign _0391_ = _0029_ & _0019_[26];
assign _0392_ = _0029_ & _0019_[27];
assign _0393_ = _0029_ & _0019_[28];
assign _0394_ = _0029_ & _0019_[29];
assign _0395_ = _0029_ & _0019_[2];
assign _0396_ = _0029_ & _0019_[30];
assign _0397_ = _0029_ & _0019_[31];
assign _0398_ = _0029_ & _0019_[3];
assign _0399_ = _0029_ & _0019_[4];
assign _0400_ = _0029_ & _0019_[5];
assign _0401_ = _0029_ & _0019_[6];
assign _0402_ = _0029_ & _0019_[7];
assign _0403_ = _0029_ & _0019_[8];
assign _0404_ = _0029_ & _0019_[9];
assign _0405_ = _0149_ ? _0120_[0] : \fifo[0] [0];
assign _0406_ = _0150_ ? _0120_[10] : \fifo[0] [10];
assign _0407_ = _0151_ ? _0120_[11] : \fifo[0] [11];
assign _0408_ = _0152_ ? _0120_[12] : \fifo[0] [12];
assign _0409_ = _0153_ ? _0120_[13] : \fifo[0] [13];
assign _0410_ = _0154_ ? _0120_[14] : \fifo[0] [14];
assign _0411_ = _0155_ ? _0120_[15] : \fifo[0] [15];
assign _0412_ = _0156_ ? _0120_[16] : \fifo[0] [16];
assign _0413_ = _0157_ ? _0120_[17] : \fifo[0] [17];
assign _0414_ = _0158_ ? _0120_[18] : \fifo[0] [18];
assign _0415_ = _0159_ ? _0120_[19] : \fifo[0] [19];
assign _0416_ = _0160_ ? _0120_[1] : \fifo[0] [1];
assign _0417_ = _0161_ ? _0120_[20] : \fifo[0] [20];
assign _0418_ = _0162_ ? _0120_[21] : \fifo[0] [21];
assign _0419_ = _0163_ ? _0120_[22] : \fifo[0] [22];
assign _0420_ = _0164_ ? _0120_[23] : \fifo[0] [23];
assign _0421_ = _0165_ ? _0120_[24] : \fifo[0] [24];
assign _0422_ = _0166_ ? _0120_[25] : \fifo[0] [25];
assign _0423_ = _0167_ ? _0120_[26] : \fifo[0] [26];
assign _0424_ = _0168_ ? _0120_[27] : \fifo[0] [27];
assign _0425_ = _0169_ ? _0120_[28] : \fifo[0] [28];
assign _0426_ = _0170_ ? _0120_[29] : \fifo[0] [29];
assign _0427_ = _0171_ ? _0120_[2] : \fifo[0] [2];
assign _0428_ = _0172_ ? _0120_[30] : \fifo[0] [30];
assign _0429_ = _0173_ ? _0120_[31] : \fifo[0] [31];
assign _0430_ = _0174_ ? _0120_[3] : \fifo[0] [3];
assign _0431_ = _0175_ ? _0120_[4] : \fifo[0] [4];
assign _0432_ = _0176_ ? _0120_[5] : \fifo[0] [5];
assign _0433_ = _0177_ ? _0120_[6] : \fifo[0] [6];
assign _0434_ = _0178_ ? _0120_[7] : \fifo[0] [7];
assign _0435_ = _0179_ ? _0120_[8] : \fifo[0] [8];
assign _0436_ = _0180_ ? _0120_[9] : \fifo[0] [9];
assign _0437_ = _0181_ ? _0120_[0] : \fifo[1] [0];
assign _0438_ = _0182_ ? _0120_[10] : \fifo[1] [10];
assign _0439_ = _0183_ ? _0120_[11] : \fifo[1] [11];
assign _0440_ = _0184_ ? _0120_[12] : \fifo[1] [12];
assign _0441_ = _0185_ ? _0120_[13] : \fifo[1] [13];
assign _0442_ = _0186_ ? _0120_[14] : \fifo[1] [14];
assign _0443_ = _0187_ ? _0120_[15] : \fifo[1] [15];
assign _0444_ = _0188_ ? _0120_[16] : \fifo[1] [16];
assign _0445_ = _0189_ ? _0120_[17] : \fifo[1] [17];
assign _0446_ = _0190_ ? _0120_[18] : \fifo[1] [18];
assign _0447_ = _0191_ ? _0120_[19] : \fifo[1] [19];
assign _0448_ = _0192_ ? _0120_[1] : \fifo[1] [1];
assign _0449_ = _0193_ ? _0120_[20] : \fifo[1] [20];
assign _0450_ = _0194_ ? _0120_[21] : \fifo[1] [21];
assign _0451_ = _0195_ ? _0120_[22] : \fifo[1] [22];
assign _0452_ = _0196_ ? _0120_[23] : \fifo[1] [23];
assign _0453_ = _0197_ ? _0120_[24] : \fifo[1] [24];
assign _0454_ = _0198_ ? _0120_[25] : \fifo[1] [25];
assign _0455_ = _0199_ ? _0120_[26] : \fifo[1] [26];
assign _0456_ = _0200_ ? _0120_[27] : \fifo[1] [27];
assign _0457_ = _0201_ ? _0120_[28] : \fifo[1] [28];
assign _0458_ = _0202_ ? _0120_[29] : \fifo[1] [29];
assign _0459_ = _0203_ ? _0120_[2] : \fifo[1] [2];
assign _0460_ = _0204_ ? _0120_[30] : \fifo[1] [30];
assign _0461_ = _0205_ ? _0120_[31] : \fifo[1] [31];
assign _0462_ = _0206_ ? _0120_[3] : \fifo[1] [3];
assign _0463_ = _0207_ ? _0120_[4] : \fifo[1] [4];
assign _0464_ = _0208_ ? _0120_[5] : \fifo[1] [5];
assign _0465_ = _0209_ ? _0120_[6] : \fifo[1] [6];
assign _0466_ = _0210_ ? _0120_[7] : \fifo[1] [7];
assign _0467_ = _0211_ ? _0120_[8] : \fifo[1] [8];
assign _0468_ = _0212_ ? _0120_[9] : \fifo[1] [9];
assign _0469_ = _0213_ ? _0120_[0] : \fifo[2] [0];
assign _0470_ = _0214_ ? _0120_[10] : \fifo[2] [10];
assign _0471_ = _0215_ ? _0120_[11] : \fifo[2] [11];
assign _0472_ = _0216_ ? _0120_[12] : \fifo[2] [12];
assign _0473_ = _0217_ ? _0120_[13] : \fifo[2] [13];
assign _0474_ = _0218_ ? _0120_[14] : \fifo[2] [14];
assign _0475_ = _0219_ ? _0120_[15] : \fifo[2] [15];
assign _0476_ = _0220_ ? _0120_[16] : \fifo[2] [16];
assign _0477_ = _0221_ ? _0120_[17] : \fifo[2] [17];
assign _0478_ = _0222_ ? _0120_[18] : \fifo[2] [18];
assign _0479_ = _0223_ ? _0120_[19] : \fifo[2] [19];
assign _0480_ = _0224_ ? _0120_[1] : \fifo[2] [1];
assign _0481_ = _0225_ ? _0120_[20] : \fifo[2] [20];
assign _0482_ = _0226_ ? _0120_[21] : \fifo[2] [21];
assign _0483_ = _0227_ ? _0120_[22] : \fifo[2] [22];
assign _0484_ = _0228_ ? _0120_[23] : \fifo[2] [23];
assign _0485_ = _0229_ ? _0120_[24] : \fifo[2] [24];
assign _0486_ = _0230_ ? _0120_[25] : \fifo[2] [25];
assign _0487_ = _0231_ ? _0120_[26] : \fifo[2] [26];
assign _0488_ = _0232_ ? _0120_[27] : \fifo[2] [27];
assign _0489_ = _0233_ ? _0120_[28] : \fifo[2] [28];
assign _0490_ = _0234_ ? _0120_[29] : \fifo[2] [29];
assign _0491_ = _0235_ ? _0120_[2] : \fifo[2] [2];
assign _0492_ = _0236_ ? _0120_[30] : \fifo[2] [30];
assign _0493_ = _0237_ ? _0120_[31] : \fifo[2] [31];
assign _0494_ = _0238_ ? _0120_[3] : \fifo[2] [3];
assign _0495_ = _0239_ ? _0120_[4] : \fifo[2] [4];
assign _0496_ = _0240_ ? _0120_[5] : \fifo[2] [5];
assign _0497_ = _0241_ ? _0120_[6] : \fifo[2] [6];
assign _0498_ = _0242_ ? _0120_[7] : \fifo[2] [7];
assign _0499_ = _0243_ ? _0120_[8] : \fifo[2] [8];
assign _0500_ = _0244_ ? _0120_[9] : \fifo[2] [9];
assign _0501_ = _0245_ ? _0120_[0] : \fifo[3] [0];
assign _0502_ = _0246_ ? _0120_[10] : \fifo[3] [10];
assign _0503_ = _0247_ ? _0120_[11] : \fifo[3] [11];
assign _0504_ = _0248_ ? _0120_[12] : \fifo[3] [12];
assign _0505_ = _0249_ ? _0120_[13] : \fifo[3] [13];
assign _0506_ = _0250_ ? _0120_[14] : \fifo[3] [14];
assign _0507_ = _0251_ ? _0120_[15] : \fifo[3] [15];
assign _0508_ = _0252_ ? _0120_[16] : \fifo[3] [16];
assign _0509_ = _0253_ ? _0120_[17] : \fifo[3] [17];
assign _0510_ = _0254_ ? _0120_[18] : \fifo[3] [18];
assign _0511_ = _0255_ ? _0120_[19] : \fifo[3] [19];
assign _0512_ = _0256_ ? _0120_[1] : \fifo[3] [1];
assign _0513_ = _0257_ ? _0120_[20] : \fifo[3] [20];
assign _0514_ = _0258_ ? _0120_[21] : \fifo[3] [21];
assign _0515_ = _0259_ ? _0120_[22] : \fifo[3] [22];
assign _0516_ = _0260_ ? _0120_[23] : \fifo[3] [23];
assign _0517_ = _0261_ ? _0120_[24] : \fifo[3] [24];
assign _0518_ = _0262_ ? _0120_[25] : \fifo[3] [25];
assign _0519_ = _0263_ ? _0120_[26] : \fifo[3] [26];
assign _0520_ = _0264_ ? _0120_[27] : \fifo[3] [27];
assign _0521_ = _0265_ ? _0120_[28] : \fifo[3] [28];
assign _0522_ = _0266_ ? _0120_[29] : \fifo[3] [29];
assign _0523_ = _0267_ ? _0120_[2] : \fifo[3] [2];
assign _0524_ = _0268_ ? _0120_[30] : \fifo[3] [30];
assign _0525_ = _0269_ ? _0120_[31] : \fifo[3] [31];
assign _0526_ = _0270_ ? _0120_[3] : \fifo[3] [3];
assign _0527_ = _0271_ ? _0120_[4] : \fifo[3] [4];
assign _0528_ = _0272_ ? _0120_[5] : \fifo[3] [5];
assign _0529_ = _0273_ ? _0120_[6] : \fifo[3] [6];
assign _0530_ = _0274_ ? _0120_[7] : \fifo[3] [7];
assign _0531_ = _0275_ ? _0120_[8] : \fifo[3] [8];
assign _0532_ = _0276_ ? _0120_[9] : \fifo[3] [9];
assign _0533_ = _0277_ ? _0120_[0] : \fifo[4] [0];
assign _0534_ = _0278_ ? _0120_[10] : \fifo[4] [10];
assign _0535_ = _0279_ ? _0120_[11] : \fifo[4] [11];
assign _0536_ = _0280_ ? _0120_[12] : \fifo[4] [12];
assign _0537_ = _0281_ ? _0120_[13] : \fifo[4] [13];
assign _0538_ = _0282_ ? _0120_[14] : \fifo[4] [14];
assign _0539_ = _0283_ ? _0120_[15] : \fifo[4] [15];
assign _0540_ = _0284_ ? _0120_[16] : \fifo[4] [16];
assign _0541_ = _0285_ ? _0120_[17] : \fifo[4] [17];
assign _0542_ = _0286_ ? _0120_[18] : \fifo[4] [18];
assign _0543_ = _0287_ ? _0120_[19] : \fifo[4] [19];
assign _0544_ = _0288_ ? _0120_[1] : \fifo[4] [1];
assign _0545_ = _0289_ ? _0120_[20] : \fifo[4] [20];
assign _0546_ = _0290_ ? _0120_[21] : \fifo[4] [21];
assign _0547_ = _0291_ ? _0120_[22] : \fifo[4] [22];
assign _0548_ = _0292_ ? _0120_[23] : \fifo[4] [23];
assign _0549_ = _0293_ ? _0120_[24] : \fifo[4] [24];
assign _0550_ = _0294_ ? _0120_[25] : \fifo[4] [25];
assign _0551_ = _0295_ ? _0120_[26] : \fifo[4] [26];
assign _0552_ = _0296_ ? _0120_[27] : \fifo[4] [27];
assign _0553_ = _0297_ ? _0120_[28] : \fifo[4] [28];
assign _0554_ = _0298_ ? _0120_[29] : \fifo[4] [29];
assign _0555_ = _0299_ ? _0120_[2] : \fifo[4] [2];
assign _0556_ = _0300_ ? _0120_[30] : \fifo[4] [30];
assign _0557_ = _0301_ ? _0120_[31] : \fifo[4] [31];
assign _0558_ = _0302_ ? _0120_[3] : \fifo[4] [3];
assign _0559_ = _0303_ ? _0120_[4] : \fifo[4] [4];
assign _0560_ = _0304_ ? _0120_[5] : \fifo[4] [5];
assign _0561_ = _0305_ ? _0120_[6] : \fifo[4] [6];
assign _0562_ = _0306_ ? _0120_[7] : \fifo[4] [7];
assign _0563_ = _0307_ ? _0120_[8] : \fifo[4] [8];
assign _0564_ = _0308_ ? _0120_[9] : \fifo[4] [9];
assign _0565_ = _0309_ ? _0120_[0] : \fifo[5] [0];
assign _0566_ = _0310_ ? _0120_[10] : \fifo[5] [10];
assign _0567_ = _0311_ ? _0120_[11] : \fifo[5] [11];
assign _0568_ = _0312_ ? _0120_[12] : \fifo[5] [12];
assign _0569_ = _0313_ ? _0120_[13] : \fifo[5] [13];
assign _0570_ = _0314_ ? _0120_[14] : \fifo[5] [14];
assign _0571_ = _0315_ ? _0120_[15] : \fifo[5] [15];
assign _0572_ = _0316_ ? _0120_[16] : \fifo[5] [16];
assign _0573_ = _0317_ ? _0120_[17] : \fifo[5] [17];
assign _0574_ = _0318_ ? _0120_[18] : \fifo[5] [18];
assign _0575_ = _0319_ ? _0120_[19] : \fifo[5] [19];
assign _0576_ = _0320_ ? _0120_[1] : \fifo[5] [1];
assign _0577_ = _0321_ ? _0120_[20] : \fifo[5] [20];
assign _0578_ = _0322_ ? _0120_[21] : \fifo[5] [21];
assign _0579_ = _0323_ ? _0120_[22] : \fifo[5] [22];
assign _0580_ = _0324_ ? _0120_[23] : \fifo[5] [23];
assign _0581_ = _0325_ ? _0120_[24] : \fifo[5] [24];
assign _0582_ = _0326_ ? _0120_[25] : \fifo[5] [25];
assign _0583_ = _0327_ ? _0120_[26] : \fifo[5] [26];
assign _0584_ = _0328_ ? _0120_[27] : \fifo[5] [27];
assign _0585_ = _0329_ ? _0120_[28] : \fifo[5] [28];
assign _0586_ = _0330_ ? _0120_[29] : \fifo[5] [29];
assign _0587_ = _0331_ ? _0120_[2] : \fifo[5] [2];
assign _0588_ = _0332_ ? _0120_[30] : \fifo[5] [30];
assign _0589_ = _0333_ ? _0120_[31] : \fifo[5] [31];
assign _0590_ = _0334_ ? _0120_[3] : \fifo[5] [3];
assign _0591_ = _0335_ ? _0120_[4] : \fifo[5] [4];
assign _0592_ = _0336_ ? _0120_[5] : \fifo[5] [5];
assign _0593_ = _0337_ ? _0120_[6] : \fifo[5] [6];
assign _0594_ = _0338_ ? _0120_[7] : \fifo[5] [7];
assign _0595_ = _0339_ ? _0120_[8] : \fifo[5] [8];
assign _0596_ = _0340_ ? _0120_[9] : \fifo[5] [9];
assign _0597_ = _0341_ ? _0120_[0] : \fifo[6] [0];
assign _0598_ = _0342_ ? _0120_[10] : \fifo[6] [10];
assign _0599_ = _0343_ ? _0120_[11] : \fifo[6] [11];
assign _0600_ = _0344_ ? _0120_[12] : \fifo[6] [12];
assign _0601_ = _0345_ ? _0120_[13] : \fifo[6] [13];
assign _0602_ = _0346_ ? _0120_[14] : \fifo[6] [14];
assign _0603_ = _0347_ ? _0120_[15] : \fifo[6] [15];
assign _0604_ = _0348_ ? _0120_[16] : \fifo[6] [16];
assign _0605_ = _0349_ ? _0120_[17] : \fifo[6] [17];
assign _0606_ = _0350_ ? _0120_[18] : \fifo[6] [18];
assign _0607_ = _0351_ ? _0120_[19] : \fifo[6] [19];
assign _0608_ = _0352_ ? _0120_[1] : \fifo[6] [1];
assign _0609_ = _0353_ ? _0120_[20] : \fifo[6] [20];
assign _0610_ = _0354_ ? _0120_[21] : \fifo[6] [21];
assign _0611_ = _0355_ ? _0120_[22] : \fifo[6] [22];
assign _0612_ = _0356_ ? _0120_[23] : \fifo[6] [23];
assign _0613_ = _0357_ ? _0120_[24] : \fifo[6] [24];
assign _0614_ = _0358_ ? _0120_[25] : \fifo[6] [25];
assign _0615_ = _0359_ ? _0120_[26] : \fifo[6] [26];
assign _0616_ = _0360_ ? _0120_[27] : \fifo[6] [27];
assign _0617_ = _0361_ ? _0120_[28] : \fifo[6] [28];
assign _0618_ = _0362_ ? _0120_[29] : \fifo[6] [29];
assign _0619_ = _0363_ ? _0120_[2] : \fifo[6] [2];
assign _0620_ = _0364_ ? _0120_[30] : \fifo[6] [30];
assign _0621_ = _0365_ ? _0120_[31] : \fifo[6] [31];
assign _0622_ = _0366_ ? _0120_[3] : \fifo[6] [3];
assign _0623_ = _0367_ ? _0120_[4] : \fifo[6] [4];
assign _0624_ = _0368_ ? _0120_[5] : \fifo[6] [5];
assign _0625_ = _0369_ ? _0120_[6] : \fifo[6] [6];
assign _0626_ = _0370_ ? _0120_[7] : \fifo[6] [7];
assign _0627_ = _0371_ ? _0120_[8] : \fifo[6] [8];
assign _0628_ = _0372_ ? _0120_[9] : \fifo[6] [9];
assign _0629_ = _0373_ ? _0120_[0] : \fifo[7] [0];
assign _0630_ = _0374_ ? _0120_[10] : \fifo[7] [10];
assign _0631_ = _0375_ ? _0120_[11] : \fifo[7] [11];
assign _0632_ = _0376_ ? _0120_[12] : \fifo[7] [12];
assign _0633_ = _0377_ ? _0120_[13] : \fifo[7] [13];
assign _0634_ = _0378_ ? _0120_[14] : \fifo[7] [14];
assign _0635_ = _0379_ ? _0120_[15] : \fifo[7] [15];
assign _0636_ = _0380_ ? _0120_[16] : \fifo[7] [16];
assign _0637_ = _0381_ ? _0120_[17] : \fifo[7] [17];
assign _0638_ = _0382_ ? _0120_[18] : \fifo[7] [18];
assign _0639_ = _0383_ ? _0120_[19] : \fifo[7] [19];
assign _0640_ = _0384_ ? _0120_[1] : \fifo[7] [1];
assign _0641_ = _0385_ ? _0120_[20] : \fifo[7] [20];
assign _0642_ = _0386_ ? _0120_[21] : \fifo[7] [21];
assign _0643_ = _0387_ ? _0120_[22] : \fifo[7] [22];
assign _0644_ = _0388_ ? _0120_[23] : \fifo[7] [23];
assign _0645_ = _0389_ ? _0120_[24] : \fifo[7] [24];
assign _0646_ = _0390_ ? _0120_[25] : \fifo[7] [25];
assign _0647_ = _0391_ ? _0120_[26] : \fifo[7] [26];
assign _0648_ = _0392_ ? _0120_[27] : \fifo[7] [27];
assign _0649_ = _0393_ ? _0120_[28] : \fifo[7] [28];
assign _0650_ = _0394_ ? _0120_[29] : \fifo[7] [29];
assign _0651_ = _0395_ ? _0120_[2] : \fifo[7] [2];
assign _0652_ = _0396_ ? _0120_[30] : \fifo[7] [30];
assign _0653_ = _0397_ ? _0120_[31] : \fifo[7] [31];
assign _0654_ = _0398_ ? _0120_[3] : \fifo[7] [3];
assign _0655_ = _0399_ ? _0120_[4] : \fifo[7] [4];
assign _0656_ = _0400_ ? _0120_[5] : \fifo[7] [5];
assign _0657_ = _0401_ ? _0120_[6] : \fifo[7] [6];
assign _0658_ = _0402_ ? _0120_[7] : \fifo[7] [7];
assign _0659_ = _0403_ ? _0120_[8] : \fifo[7] [8];
assign _0660_ = _0404_ ? _0120_[9] : \fifo[7] [9];
always @(posedge clk)
\fifo[0] <= _0661_;
always @(posedge clk)
\fifo[1] <= _0662_;
always @(posedge clk)
\fifo[2] <= _0663_;
always @(posedge clk)
\fifo[3] <= _0664_;
always @(posedge clk)
\fifo[4] <= _0665_;
always @(posedge clk)
\fifo[5] <= _0666_;
always @(posedge clk)
\fifo[6] <= _0667_;
always @(posedge clk)
\fifo[7] <= _0668_;
assign _0672_ = ~ full;
assign empty = ~ _0671_;
assign _0673_ = ~ full;
always @(posedge clk, posedge reset)
if (reset) write_pointer <= 3'h0;
else write_pointer <= _0008_;
always @(posedge clk, posedge reset)
if (reset) read_pointer <= 3'h0;
else read_pointer <= _0007_;
always @(posedge clk, posedge reset)
if (reset) cnt <= 4'h0;
else cnt <= _0005_;
always @(posedge clk)
data_out <= _0006_;
assign _0006_ = clear ? _0669_ : _0670_;
assign _0674_ = _0018_ ? 32'd4294967295 : 32'd0;
assign _0011_ = _0017_ ? 32'hxxxxxxxx : _0674_;
assign _0675_ = _0018_ ? data_in : 32'hxxxxxxxx;
assign _0010_ = _0017_ ? 32'hxxxxxxxx : _0675_;
assign _0676_ = _0018_ ? write_pointer : 3'hx;
assign _0009_ = _0017_ ? 3'hx : _0676_;
assign _0001_ = _0017_ ? 32'd4294967295 : 32'd0;
assign _0000_ = _0017_ ? data_in : 32'hxxxxxxxx;
assign _0004_ = _0017_ ? 32'd0 : _0011_;
assign _0003_ = _0017_ ? 32'hxxxxxxxx : _0010_;
assign _0002_ = _0017_ ? 3'hx : _0009_;
assign _0677_ = _0016_ ? _0014_ : write_pointer;
assign _0008_ = clear ? { 2'h0, write } : _0677_;
assign _0678_ = _0015_ ? _0013_ : read_pointer;
assign _0007_ = clear ? { 2'h0, read } : _0678_;
assign _0679_ = read ? _0682_[3:0] : _0012_[3:0];
assign _0680_ = _0681_ ? _0679_ : cnt;
assign _0005_ = clear ? { 3'h0, _0683_ } : _0680_;
assign almost_full = & cnt[2:0];
assign _0671_ = | cnt;
assign _0682_ = cnt - 32'd1;
assign _0683_ = read ^ write;
assign _0681_ = read ^ write;
assign _0127_ = \fifo[0] ;
assign _0128_ = \fifo[1] ;
assign _0129_ = \fifo[2] ;
assign _0130_ = \fifo[3] ;
assign _0131_ = \fifo[4] ;
assign _0132_ = \fifo[5] ;
assign _0133_ = \fifo[6] ;
assign _0134_ = \fifo[7] ;
assign _0141_ = \fifo[0] ;
assign _0142_ = \fifo[1] ;
assign _0143_ = \fifo[2] ;
assign _0144_ = \fifo[3] ;
assign _0145_ = \fifo[4] ;
assign _0146_ = \fifo[5] ;
assign _0147_ = \fifo[6] ;
assign _0148_ = \fifo[7] ;
assign _0661_ = { _0429_, _0428_, _0426_, _0425_, _0424_, _0423_, _0422_, _0421_, _0420_, _0419_, _0418_, _0417_, _0415_, _0414_, _0413_, _0412_, _0411_, _0410_, _0409_, _0408_, _0407_, _0406_, _0436_, _0435_, _0434_, _0433_, _0432_, _0431_, _0430_, _0427_, _0416_, _0405_ };
assign _0662_ = { _0461_, _0460_, _0458_, _0457_, _0456_, _0455_, _0454_, _0453_, _0452_, _0451_, _0450_, _0449_, _0447_, _0446_, _0445_, _0444_, _0443_, _0442_, _0441_, _0440_, _0439_, _0438_, _0468_, _0467_, _0466_, _0465_, _0464_, _0463_, _0462_, _0459_, _0448_, _0437_ };
assign _0663_ = { _0493_, _0492_, _0490_, _0489_, _0488_, _0487_, _0486_, _0485_, _0484_, _0483_, _0482_, _0481_, _0479_, _0478_, _0477_, _0476_, _0475_, _0474_, _0473_, _0472_, _0471_, _0470_, _0500_, _0499_, _0498_, _0497_, _0496_, _0495_, _0494_, _0491_, _0480_, _0469_ };
assign _0664_ = { _0525_, _0524_, _0522_, _0521_, _0520_, _0519_, _0518_, _0517_, _0516_, _0515_, _0514_, _0513_, _0511_, _0510_, _0509_, _0508_, _0507_, _0506_, _0505_, _0504_, _0503_, _0502_, _0532_, _0531_, _0530_, _0529_, _0528_, _0527_, _0526_, _0523_, _0512_, _0501_ };
assign _0665_ = { _0557_, _0556_, _0554_, _0553_, _0552_, _0551_, _0550_, _0549_, _0548_, _0547_, _0546_, _0545_, _0543_, _0542_, _0541_, _0540_, _0539_, _0538_, _0537_, _0536_, _0535_, _0534_, _0564_, _0563_, _0562_, _0561_, _0560_, _0559_, _0558_, _0555_, _0544_, _0533_ };
assign _0666_ = { _0589_, _0588_, _0586_, _0585_, _0584_, _0583_, _0582_, _0581_, _0580_, _0579_, _0578_, _0577_, _0575_, _0574_, _0573_, _0572_, _0571_, _0570_, _0569_, _0568_, _0567_, _0566_, _0596_, _0595_, _0594_, _0593_, _0592_, _0591_, _0590_, _0587_, _0576_, _0565_ };
assign _0667_ = { _0621_, _0620_, _0618_, _0617_, _0616_, _0615_, _0614_, _0613_, _0612_, _0611_, _0610_, _0609_, _0607_, _0606_, _0605_, _0604_, _0603_, _0602_, _0601_, _0600_, _0599_, _0598_, _0628_, _0627_, _0626_, _0625_, _0624_, _0623_, _0622_, _0619_, _0608_, _0597_ };
assign _0668_ = { _0653_, _0652_, _0650_, _0649_, _0648_, _0647_, _0646_, _0645_, _0644_, _0643_, _0642_, _0641_, _0639_, _0638_, _0637_, _0636_, _0635_, _0634_, _0633_, _0632_, _0631_, _0630_, _0660_, _0659_, _0658_, _0657_, _0656_, _0655_, _0654_, _0651_, _0640_, _0629_ };
endmodule
thirdparty/RTL2CDFG/verilog_data/ALU.v 0 → 100755
module ALU (
input [31:0] A,
input [31:0] B,
input [1:0] ALUOp,
output reg [31:0] Result,
);
always @(*) begin
if (ALUOp == 2'b00)
Result <= A + B;
else if (ALUOp == 2'b01)
Result <= A - B;
else if (ALUOp == 2'b10)
Result <= A & B;
else
Result <= A % B;
end
endmodule
thirdparty/RTL2CDFG/verilog_data/Led.v 0 → 100755
module led_chaser (
input wire clk, // clock signal
input wire rst, // reset signal
output reg [7:0] led // 8-bit LED output
);
always @(posedge clk) begin
if (rst) begin
led <= 8'b00000001; // on reset, light the first LED
end else begin
led <= {led[6:0], led[7]}; // on each rising clock edge, shift LED to the right
end
end
endmodule
thirdparty/RTL2CDFG/verilog_data/comparator.v 0 → 100644
module comparator (
p,
a,
b,
clk,
);
parameter integer N = 8;
input [N-1:0] a, b;
input clk;
output p;
// assign q = (a<b)?v2cdfg/yosys_data1/comparator.v1'b0:1'b1;
always @(posedge clk) begin
if (a < b) begin
p = 1'b0;
end else begin
p = 1'b1;
end
end
endmodule
thirdparty/RTL2CDFG/verilog_data/fsm-3.v 0 → 100755
module three_state_fsm (
input wire clk, // clock signal
input wire rst, // reset signal
input wire in, // input signal
output reg [1:0] state // current state output
);
// state encoding
localparam STATE0 = 2'b00;
localparam STATE1 = 2'b01;
localparam STATE2 = 2'b10;
// state machine logic
always @(posedge clk) begin
if (rst) begin
state <= STATE0; // on reset, state machine returns to IDLE state
end else begin
// state transition logic
if (state == STATE0) begin
if (in)
state <= STATE1; // if input is high, transition from STATE0 to STATE1
end else if (state == STATE1) begin
if (in)
state <= STATE2; // if input is high, transition from STATE1 to STATE2
end else if (state == STATE2) begin
if (in)
state <= STATE0; // if input is high, transition from STATE2 to STATE0
end else begin
state <= STATE0;
end
end
end
endmodule
thirdparty/RTL2CDFG/verilog_data/full_adder_4.v 0 → 100644
// Top Level Verilog code for N-bit Ripple Carry Full Adder using Structural Modeling
module full_adder (
a,
b,
cin,
s,
cout
);
parameter integer N = 4; // N-bit adder
input [N-1:0] a, b; // N-bit inputs a and b
input cin; // input carry
output [N-1:0] s; // N-bit sum
output cout; // output final carry
wire [N:0] carry; // carry chain
genvar i; // generate variable
generate
assign carry[0] = cin; // initial carry equals cin
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
assign s[i] = (a[i] ^ b[i]) ^ carry[i]; // compute sum of each bit
assign carry[i+1] = (b[i] & carry[i]) | (a[i] & b[i]) | (a[i] & carry[i]); // compute carry
end
assign cout = carry[N]; // final carry output
endgenerate
endmodule
thirdparty/RTL2CDFG/verilog_data/test.v 0 → 100644
module soc_design_JTAG_sim_scfifo_r (
clk,
fifo_rd,
rst_n,
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
always @(posedge clk)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
endmodule
\ No newline at end of file
thirdparty/RTL2CDFG/yosys_data/test.v 0 → 100644
module soc_design_JTAG_sim_scfifo_r (
clk,
fifo_rd,
rst_n,
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
always @(posedge clk)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
endmodule
\ No newline at end of file
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