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Zhengyue Zhao
mmu-val_v1
Commits
5ceb7c32
Commit
5ceb7c32
authored
Dec 13, 2021
by
Zhengyue Zhao
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5ceb7c32
module
RISCV_mmu_top
(
clock
,
reset
,
driver_on
)
;
input
clock
;
input
reset
;
input
driver_on
;
wire
[
31
:
0
]
axi_read_data
;
wire
axi_read_data_valid
;
wire
axi_write_data_bvalid
;
wire
[
31
:
0
]
satp
;
wire
[
31
:
0
]
mstatus
;
wire
[
31
:
0
]
sstatus
;
wire
[
1
:
0
]
instruction_type
;
wire
[
1
:
0
]
this_priviledge
;
wire
[
31
:
0
]
logic_axi_read_data_address
;
wire
[
31
:
0
]
logic_axi_write_data_address
;
wire
[
31
:
0
]
logic_axi_write_data
;
wire
logic_axi_read_data_address_valid
;
wire
logic_axi_write_data_valid
;
wire
[
1
:
0
]
store_data_size_in
;
RISCV_mmu_driver
rmd
(
.
driver_on
(
driver_on
)
,
.
axi_read_data
(
axi_read_data
)
,
.
axi_read_data_valid
(
axi_read_data_valid
)
,
.
axi_write_data_bvalid
(
axi_write_data_bvalid
)
,
.
satp
(
satp
)
,
.
mstatus
(
mstatus
)
,
.
sstatus
(
sstatus
)
,
.
instruction_type
(
instruction_type
)
,
.
this_priviledge
(
this_priviledge
)
,
.
logic_axi_read_data_address
(
logic_axi_read_data_address
)
,
.
logic_axi_write_data_address
(
logic_axi_write_data_address
)
,
.
logic_axi_write_data
(
logic_axi_write_data
)
,
.
logic_axi_read_data_address_valid
(
logic_axi_read_data_address_valid
)
,
.
logic_axi_write_data_valid
(
logic_axi_write_data_valid
)
,
.
store_data_size_in
(
store_data_size_in
)
)
;
wire
[
31
:
0
]
axi_read_data_address
;
wire
axi_read_data_address_valid
;
wire
[
31
:
0
]
axi_write_data_address
;
wire
[
31
:
0
]
axi_write_data
;
wire
axi_write_data_valid
;
wire
[
1
:
0
]
store_data_size
=
store_data_size_in
;
wire
[
31
:
0
]
logic_axi_read_data
;
wire
logic_axi_write_data_bvalid
;
wire
logic_axi_read_data_valid
;
wire
logic_axi_read_data_page_fault
;
wire
logic_axi_write_data_page_fault
;
RISCV_mmu_for_val
rm
(
.
clock
(
clock
)
,
.
reset
(
reset
)
,
.
axi_read_data
(
axi_read_data
)
,
.
axi_read_data_valid
(
axi_read_data_valid
)
,
.
axi_write_data_bvalid
(
axi_write_data_bvalid
)
,
.
satp
(
satp
)
,
.
mstatus
(
mstatus
)
,
.
sstatus
(
sstatus
)
,
.
instruction_type
(
instruction_type
)
,
.
this_priviledge
(
this_priviledge
)
,
.
logic_axi_read_data_address
(
logic_axi_read_data_address
)
,
.
logic_axi_write_data_address
(
logic_axi_write_data_address
)
,
.
logic_axi_write_data
(
logic_axi_write_data
)
,
.
logic_axi_read_data_address_valid
(
logic_axi_read_data_address_valid
)
,
.
logic_axi_write_data_valid
(
logic_axi_write_data_valid
)
,
.
axi_read_data_address
(
axi_read_data_address
)
,
.
axi_read_data_address_valid
(
axi_read_data_address_valid
)
,
.
axi_write_data_address
(
axi_write_data_address
)
,
.
axi_write_data
(
axi_write_data
)
,
.
axi_write_data_valid
(
axi_write_data_valid
)
,
.
store_data_size_in
(
store_data_size_in
)
,
.
store_data_size
(
store_data_size
)
,
.
logic_axi_read_data
(
logic_axi_read_data
)
,
.
logic_axi_write_data_bvalid
(
logic_axi_write_data_bvalid
)
,
.
logic_axi_read_data_valid
(
logic_axi_read_data_valid
)
,
.
logic_axi_read_data_page_fault
(
logic_axi_read_data_page_fault
)
,
.
logic_axi_write_data_page_fault
(
logic_axi_write_data_page_fault
)
)
;
wire
[
31
:
0
]
PTE_address
;
wire
PTE_valid
;
wire
[
1
:
0
]
PTE_ply
;
wire
[
31
:
0
]
PTE_out
;
wire
PTE_out_valid
;
assign
PTE_address
=
axi_read_data_address
;
assign
PTE_valid
=
axi_read_data_address_valid
;
assign
PTE_ply
=
(
axi_read_data_address
[
1
])
||
axi_read_data_address
[
2
]
||
axi_read_data_address
[
3
]
;
assign
axi_read_data
=
PTE_out
;
assign
axi_read_data_valid
=
PTE_out_valid
;
RISCV_pt
rp
(
.
PTE_address
(
PTE_address
)
,
.
PTE_valid
(
PTE_valid
)
,
.
PTE_ply
(
PTE_ply
)
,
.
PTE_out
(
PTE_out
)
,
.
PTE_out_valid
(
PTE_out_valid
)
)
;
wire
[
31
:
0
]
read_address
;
wire
read_valid
;
wire
[
31
:
0
]
write_address
,
write_data
;
wire
write_valid
;
wire
[
31
:
0
]
read_data
;
wire
read_data_valid
;
wire
write_data_bvalid
;
assign
read_address
=
axi_read_data_address
;
assign
read_valid
=
axi_read_data_address_valid
;
assign
write_address
=
axi_write_data_valid
;
assign
write_data
=
axi_write_data
;
assign
write_valid
=
axi_write_data_valid
;
assign
read_data
=
axi_read_data
;
assign
read_data_valid
=
axi_read_data_valid
;
assign
write_data_bvalid
=
axi_write_data_bvalid
;
RISCV_mm
rmm
(
.
reset
(
reset
)
,
.
clk
(
clock
)
,
.
read_address
(
read_address
)
,
.
read_valid
(
read_valid
)
,
.
write_address
(
write_address
)
,
.
write_data
(
write_data
)
,
.
write_valid
(
write_valid
)
,
.
store_data_size
(
store_data_size
)
,
.
read_data
(
read_data
)
,
.
read_data_valid
(
read_data_valid
)
,
.
write_data_bvalid
(
write_data_bvalid
)
)
;
endmodule
\ No newline at end of file
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