1. 26 Aug, 2019 1 commit
    • [VTA][TSIM] Introduce Virtual Memory for TSIM Driver (#3686) · 92b6ca71
      * initial virtual memory;
      
      * initial integration;
      
      * include the header file in cmake;
      
      * implement allocation with virtual to logical address mapping;
      
      * virtual memory for tsim_driver;
      
      * implement the missing memory release function;
      
      * readability improvement;
      
      * readability improvement;
      
      * address review comments;
      
      * improved robustness in virtual memory allocation;
      
      * remove VTA_TSIM_USE_VIRTUAL_MEMORY macro and use virtual memory for tsim by default;
      
      * link tvm against vta library;
      
      * merge with master
      
      * build virtual memory system without linking tvm against vta;
      
      * minor change;
      
      * reuse VTA_PAGE_BYTES;
      
      * using DRAM class from sim_driver as VirtualMemoryManager;
      
      * satisfy linter;
      
      * add comments in code;
      
      * undo changes to Makefile
      
      * undo changes to Makefile
      
      * retrigger ci;
      
      * retrigger ci;
      
      * directly call into VirtualMemoryManager::Global()
      Liangfu Chen committed
  2. 24 Aug, 2019 1 commit
  3. 23 Aug, 2019 5 commits
  4. 22 Aug, 2019 3 commits
  5. 21 Aug, 2019 3 commits
  6. 20 Aug, 2019 2 commits
  7. 19 Aug, 2019 5 commits
  8. 18 Aug, 2019 1 commit
  9. 17 Aug, 2019 2 commits
  10. 16 Aug, 2019 3 commits
  11. 15 Aug, 2019 3 commits
  12. 14 Aug, 2019 6 commits
  13. 13 Aug, 2019 5 commits
    • syntax fix (#3765) · 4c01e8ee
      Benjamin Tu committed
    • [VTA][Chisel] run all unittests by default (#3766) · e9782030
      * [VTA][Chisel] run all unittests by default
      
      * better naming
      
      * add generated unittest folder to clean rule
      Luis Vega committed
    • fix some pass docs (#3767) · 8a46444f
      Zhi committed
    • [VTA][TSIM][Build] Towards TSIM CI testing (#3704) · e518fe1c
      * building TSIM specific library along with fast simulator to quickly switch between dlls
      
      * cmake controlled TSIM libraries
      
      * always build tsim driver in either simulation modes
      
      * build DLLs based on CMAKE flags
      
      * updating the jenkinsfile
      
      * small restructuring
      
      * reducing the cmake flags
      
      * update instructions
      
      * reverting to 3 flags
      
      * update Jenkinsfile
      
      * adding new line
      
      * enabling TSIM unit and integration tests
      
      * fix description
      
      * temporarily disabling task_python_vta tests in CPU Build stage
      
      * move CPU tests in unit test stage
      
      * stage  reorg
      
      * better make
      
      * disabling TSIM tests for now
      
      * reverting some restructuring
      
      * fix
      Thierry Moreau committed
    • [VTA] [Chisel] Improved Data Gen, Added ALU Test (#3743) · 5f9c5e43
      * added alutest
      
      * fix indent
      
      * name change for cycle
      
      * improved data gen and infra
      
      * added alutest
      
      * fix indent
      
      * name change for cycle
      
      * improved data gen and infra
      
      * fix space
      
      * fix indent
      
      * fixes
      
      * aluRef
      
      * fix randomarary
      
      * add
      
      * Revert "add"
      
      This reverts commit 87077daebbe055dee11f80e37da3a6291138e0f0.
      
      * Revert "fix randomarary"
      
      This reverts commit df386c1e660eb6ebcff1a1f905610573676f1589.
      
      * Revert "aluRef"
      
      This reverts commit 8665f0d4a7b12b796b2cb1ca6bf9cfe5613ee389.
      
      * should fix dlmc-core
      Benjamin Tu committed