* Add graph tuning

* Add tests

* Fix tests

* Fix pylint

* Small fix for docstring

* Minor fix

* Support fetching workload from relay expr

* Simplify benchmark layout transformation

* Add relay support

* Fix infer layout func name

* Refactor internal data representation

* Fix issues

* Add PBQP solver

* Fix layout transform check

* Add PBQPTuner test

* Fix lint

* Update tutorial

* Fix tutorial

* Fix lint

* Add relay test

* Remove nnvm since nnvm graph can be converted to relay function

* Modify benchmark layout wrt new layout_transform api

* Fix lint

* Update docstring for DP tuner

* Refactor traverse graph

* Support graph tuning for multiple target operators

* Fix fetching workloads

* Add x86 depthwise_conv2d infer_layout

* Fix x86 depthwise_conv2d autotvm

* Fix PBQP tuner

* Fix DP tuner

* Generate dummy layout transform record

* Update tutorial

* Modify layout records name

* Add ASF header

* Add ASF header for testing files

* Fix test

* Fix topi fetching

* Some refactors

* Fix lint

* Fix tutorial

* Rename test files

* Fix doc typo

* Add test case note link

Issue:
Once change LOG_BLOCK_IN or LOG_BLOCK_OUT into > 4 value, when run vta
“Simple Matrix Multiply” or load vta, vta would crash at vta_conv2d.py.

Analysis:
This issue caused by resnet18 logic of vta_conv2d.py which have
in_filter minmum size that is 16. > 4 value would cause such in_filter
check failed then make xfer_size be empty and find_schedules function
return a empty list finally cause crash.

Solution:
add the empty list check.

This was a typo in the original custom datatypes PR.

[VTA][TSIM] Use Module instead of RawModule for testbench by creating an empty bundle for the IO (#3242)

* use Module instead of RawModule for testbench by creating an empty bundle for the IO

* change default back to verilog

* [Doc][Relay] Add VM doc

* Add Apache header

* Apply suggestions from code review

Co-Authored-By: Steven S. Lyubomirsky <slyubomirsky@gmail.com>
Co-Authored-By: 雾雨魔理沙 <lolisa@marisa.moe>
Co-Authored-By: Logan Weber <36520469+weberlo@users.noreply.github.com>
Co-Authored-By: Zhi <5145158+zhiics@users.noreply.github.com>

* Junru's comment

* More fix

* More fix

* More fix

* last fix

* Apply suggestions from code review

Co-Authored-By: 雾雨魔理沙 <lolisa@marisa.moe>

* Apply suggestions from code review

Co-Authored-By: Logan Weber <36520469+weberlo@users.noreply.github.com>

* Add code links

* Remove unused bp

* Update docs/dev/virtual_machine.rst

Co-Authored-By: Logan Weber <36520469+weberlo@users.noreply.github.com>

* Explain TODO

* Yong's comment

Co-Authored-By: Yong Wu <55wuyong@163.com>

* Comment

* [ARITH] Improve div/mod in rewrite simplifier

* Fix lint error

* Fuller file name in src/arithmetic/modular_set.h

Co-Authored-By: Wei Chen <ipondering.weic@gmail.com>

* Generalize some rules

* Replace gcd factoring with specialized rules

* Mark rules that don't work for non-truncated division

* More tests

* Add Crop op converter

* lint

* x

* Fixed a typo

* Remove outdated url link.

* [RELAY]Frontend darknet

* CI test file updated & CI error fixed

* avg_pool pad fix

* Changed repo_url and doc formatting

* Update add_asf_header.py

* Update add_asf_header.py

Modified pick best to accumulate the best configurations from both the input and output file. (#3225)

* sort bugfix for not rearranging input data

* separate sort schedule

* fix lint

* use identity op instead

* fix lint

* remove redundent code

* Support the 1x1 int8 conv with NHWC layout and weight packing

fix linter

* fix the memoize issue

* fix the failed nhwc test

* add the schedule for pack to unbreak other tests

* skip avx512 compile

* Support the 1x1 int8 conv with NHWC layout and weight packing

fix linter

* fix the memoize issue

* fix the failed nhwc test

* add the schedule for pack to unbreak other tests

* skip avx512 compile

* Unify the data_layout and kernel_layout relation

* add asf header

* fix the comment

* retrigger the build/test

* Convert TFLite NCHW to NHWC

* Minor comment fix

* remove on_device op after annotation

* Update src/relay/pass/device_annotation.cc

Co-Authored-By: MORINAGA <34588258+imorinaga@users.noreply.github.com>

* [Relay][TOPI] operator All

* Update tests/python/frontend/tensorflow/test_forward.py

Co-Authored-By: yongwww <55wuyong@163.com>

* fix comments

* change to level 4