- 10 Oct, 2017 1 commit
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* [ARITH] Improve detect linear equation * fix doc
Tianqi Chen committed
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- 03 Aug, 2017 1 commit
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Tianqi Chen committed
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- 18 Jul, 2017 1 commit
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* prefetch interface added * prefetch python comments modified. prefetch info data structure maintained. * start injecting prefetches. first step (domain touch) implemented. * domain touch tested. * Prefetch ir_mutator and ir_visitor dispatch registered. * modify domain touched from passing a func_ref to passing a tensor * modify domain touched from passing a func_ref to passing a tensor * modify Tensor copy to Tensor ref * temp commit for rebase * debug info removed, typo fixed, ready to rebase * prefetch flatten test add! * roll back builtin functions to side effect functions * lint error fixed! * add cache line size to storage flatten argument * forgot modifications add * change code style to dmlc-like; get rid of can_prove, use manually compute instead * python lint error fixed * modify instrinsic name to pass tests * [TEST] get rid of str(), replace them by accessing attributes * change map to list comprehension * redundant numpy import removed
Jian Weng committed
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- 21 Apr, 2017 1 commit
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Tianqi Chen committed
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- 26 Mar, 2017 1 commit
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* [CODEGEN] Refactor common codegen, Verilog Codegen * fix make * fix mk * update enable signal * change function name to at neg edge * Move test to correct place
Tianqi Chen committed
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- 05 Mar, 2017 1 commit
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* [IterVar/REFACTOR] Add types to IterVar * [ARITH/REFACTOR] Move IntSet to include * [REFACTOR/OP] Move Op detail to seperate folder. * fix test
Tianqi Chen committed
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- 04 Mar, 2017 1 commit
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* loop_partition draft * divide loop variable into constant domain and variable domain & consider multiple partitions * process doubt interval * fix and refactor, add relax_map arg in BoundDeduce * fix testcase and comment * rebase to zero, convert to SSA * change the logic of generating loop code & fix issues * add a testcase for relax map in deducebound && fix issues * clean code * const auto& * add test_multi_if
Ziheng Jiang committed
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- 01 Mar, 2017 1 commit
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* [ARITH/VISITOR] Modular Analysis, ExprFunctor, StmtFunctor * retrigger * [IRFunctor] Migrated CodegenC * [IRFUNCTOR] Migrate CodeGenLLVM * [IRFunctor] Migrate canonical * [IRFunctor] Migrate vectorize * [IRFunctor] migrate CodeGenStackVM
Tianqi Chen committed
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- 17 Feb, 2017 1 commit
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* [PYTHON/API] Add compare and logic build-in op for Expr * remove 'and', 'or' * add deducer * [WIP] bound_deducer.cc * move IntervalSet and StrideSet into int_set_internal.h * add multiple failure for VariablePathFinder, add EvalSign * consider round in deduce, add success flag * remove Visit_(Div) * add comment, update HalideIR * expose intset to python * check the sign of every expr * set return type as ExprSignType * fine tune * add min & max python api for interval set * support for conditional expr * refactor test * add checker for BoundDeducer * add python check test * fix * fix * change range to interval; remove converter * remove converter declaration * remove int_set_internal.h
Ziheng Jiang committed
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