* Add contrib sort functions to android rpc app.

* replaced tab with spaces oops.

* add mac count for conv 2d transpose

* add the explanation of missing parameter in docstring

* typo

* fix pylint

* [Relay][Pass] Only allow Module -> Module for opts managed by pass infra

* revert gradient pass

[PASS] Use new infra for lower warp memory
[ARITH] EvalSet recursively evaluates set in case dom_map contains set that need to be relaxed.

* fix autotvm

* fix bug when heap_items is empty

* init

init

lint

rename

ci

fix

add

add some doc

save

add some test

add some test

lint

lint

lint

* fix build

* save

* fix

* Nested rfactor fix, update predicates as well as source.

* Linter

* Syntax fix.

* Add sequence_mask

use exactly the same arguments as mxnet

fix

* fix lint

* fix lint

* add mxnet conversion + relay

* update

* update doc

* fix pylint

* fix doc

* address comment

* try to address comments

* try to enable shape check for valid_length

* fix

* try to fix

* fix bug

* try to fix

* address comment

* address comment

* simplify build script, remove python 2 support

* remove py2 file

* update py3

* fix relay reduce axis bug

* add tests for reduce bug

Discovered via: __flake8 . --count --select=E9,F63,F72,F82 --show-source --statistics__

Legacy __print__ statements are syntax errors in Python 3 but __print()__ function works as expected in both Python 2 and Python 3.

[Symptom]
after follow the tsim example readme, doing verilator install by 'sudo apt-get-install verilator'
Once enable 'debug' or manually add 'printf' logic in chisel module, verilator would report
following error.
'syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER'

[Fix]
upgrade verilator to 4.012, issue fixed.

[Solution]
Link README.md verilator install steps with verilator home website
install instruction.

Discovered via: __flake8 . --count --select=E9,F63,F72,F82 --show-source --statistics__

* [AutoTVM] Fix a bug in simulated annealing

* Update sa_model_optimizer.py

* [VTA] Add VTA PYNQ metal_test bitstream program logic and fix couple compile issue.

Issue:
VTAProgram not exist and cause compile error.
No logic to program the bitstream into FPGA.
metal test still use pynq 2.1 library which not support on latest
pynq 2.4.

Solution:
remove old VTAProgram.
when setting is pynq, program the bitstream during compile.
change DMA link library to libcma.

* Address review commends.

Summary:

In multi-threaded applications where we have multiple inferences on the
same model in parallel (consider e.g. a TTS system handling multiple
requests), it can be useful to share the parameters of a model amongst
these multiple instances. This improves the cache utilization behaviour
of the system, as multiple cores can use the same set of weights instead
of evicting the identical copies of weights in a shared cache.

As the underlying `NDArray` instances in `data_entry_` implement a
ref-counted based sharing system, this is a simple modification of the
`GraphRuntime::LoadParams` logic to instead copy parameters from an
existing GraphRuntime instance. This is a little ugly in that we need
both the pre-existing GraphRuntime instance, as well as the 'serialized'
params (since we need to know the set of names we should copy), but
without imposing additional assumptions (i.e. storing the set of param
names in GraphRuntime, and enforcing that shared param names are
identical to the parameters set in the preceding `LoadParams` call),
this seems unavoidable.

Test Plan:

Unit test added.