- 15 Apr, 2017 1 commit
-
-
* [DOC] Initial doc system * Migrate API * Update docs
Tianqi Chen committed
-
- 26 Mar, 2017 1 commit
-
-
* [CODEGEN] Refactor common codegen, Verilog Codegen * fix make * fix mk * update enable signal * change function name to at neg edge * Move test to correct place
Tianqi Chen committed
-
- 31 Jan, 2017 1 commit
-
-
[TEST/PYTHON] Add unittest folder, add a build pipeline. Rename Buffer.ptr to Buffer.data to be consistent with Array. (#29)
Tianqi Chen committed
-
- 18 Jan, 2017 1 commit
-
-
* [PASS] Assign unique names to variables in ConvertSSA pass * revert change to ConverSSA pass
Haichen Shen committed
-
- 16 Jan, 2017 1 commit
-
-
* [PASS] Export simplify and equal to python * fix naming convention
Haichen Shen committed
-
- 10 Jan, 2017 1 commit
-
-
* [PASS] Schedule Ops init working version * bugfix in PassUp
Tianqi Chen committed
-
- 27 Nov, 2016 1 commit
-
-
tqchen committed
-