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wenyuanbo
tic
Commits
dc5bdb6b
Commit
dc5bdb6b
authored
Apr 07, 2018
by
tqchen
Committed by
Tianqi Chen
Jul 11, 2018
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Upgrade TVM to latest version
parent
75ea6e45
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4 changed files
with
4 additions
and
5 deletions
+4
-5
vta/Makefile
+1
-1
vta/apps/pynq_rpc/start_rpc_server.sh
+1
-1
vta/examples/resnet18/pynq/imagenet_predict.py
+1
-2
vta/python/vta/build.py
+1
-1
No files found.
vta/Makefile
View file @
dc5bdb6b
...
...
@@ -58,7 +58,7 @@ VTA_LIB_SRC = $(wildcard src/*.cc src/tvm/*.cc)
ifeq
($(TARGET),
VTA_PYNQ_TARGET)
VTA_LIB_SRC
+=
$
(
wildcard src/pynq/
*
.cc
)
LDFLAGS
+=
-L
/usr/lib
-lsds_lib
LDFLAGS
+=
-L
/opt/python3.6/lib/python3.6/site-packages/pynq/
lib
/
-l
:libdma.so
LDFLAGS
+=
-L
/opt/python3.6/lib/python3.6/site-packages/pynq/
drivers
/
-l
:libdma.so
endif
VTA_LIB_OBJ
=
$
(
patsubst %.cc, build/%.o,
$(VTA_LIB_SRC)
)
...
...
vta/apps/pynq_rpc/start_rpc_server.sh
View file @
dc5bdb6b
#!/bin/bash
export
PYTHONPATH
=
${
PYTHONPATH
}
:/home/xilinx/tvm/python
export
LD_LIBRARY_PATH
=
${
LD_LIBRARY_PATH
}
:/opt/python3.6/lib/python3.6/site-packages/pynq/
lib
/
export
LD_LIBRARY_PATH
=
${
LD_LIBRARY_PATH
}
:/opt/python3.6/lib/python3.6/site-packages/pynq/
drivers
/
python
-m
tvm.exec.rpc_server
--load-library
/home/xilinx/vta/lib/libvta.so
vta/examples/resnet18/pynq/imagenet_predict.py
View file @
dc5bdb6b
...
...
@@ -29,7 +29,7 @@ BITSTREAM_FILE = 'vta.bit'
for
file
in
[
TEST_FILE
,
CATEG_FILE
,
RESNET_GRAPH_FILE
,
RESNET_PARAMS_FILE
,
BITSTREAM_FILE
]:
if
not
os
.
path
.
isfile
(
file
):
print
(
"Downloading {}"
.
format
(
file
))
wget
.
download
(
url
+
file
)
wget
.
download
(
url
+
file
)
# Program the FPGA remotely
assert
tvm
.
module
.
enabled
(
"rpc"
)
...
...
@@ -129,7 +129,6 @@ with nnvm.compiler.build_config(opt_level=3):
sym
,
target
,
shape_dict
,
dtype_dict
,
params
=
params
)
remote
=
rpc
.
connect
(
host
,
port
)
temp
=
util
.
tempdir
()
lib
.
save
(
temp
.
relpath
(
"graphlib.o"
))
remote
.
upload
(
temp
.
relpath
(
"graphlib.o"
))
...
...
vta/python/vta/build.py
View file @
dc5bdb6b
...
...
@@ -52,4 +52,4 @@ def debug_mode(debug_flag):
# Add a lower pass to sync uop
build_module
.
BuildConfig
.
current
.
add_lower_pass
=
debug_mode
(
0
)
build_module
.
current_build_config
()
.
add_lower_pass
=
debug_mode
(
0
)
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