Commit dc5bdb6b by tqchen Committed by Tianqi Chen

Upgrade TVM to latest version

parent 75ea6e45
......@@ -58,7 +58,7 @@ VTA_LIB_SRC = $(wildcard src/*.cc src/tvm/*.cc)
ifeq ($(TARGET), VTA_PYNQ_TARGET)
VTA_LIB_SRC += $(wildcard src/pynq/*.cc)
LDFLAGS += -L/usr/lib -lsds_lib
LDFLAGS += -L/opt/python3.6/lib/python3.6/site-packages/pynq/lib/ -l:libdma.so
LDFLAGS += -L/opt/python3.6/lib/python3.6/site-packages/pynq/drivers/ -l:libdma.so
endif
VTA_LIB_OBJ = $(patsubst %.cc, build/%.o, $(VTA_LIB_SRC))
......
#!/bin/bash
export PYTHONPATH=${PYTHONPATH}:/home/xilinx/tvm/python
export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:/opt/python3.6/lib/python3.6/site-packages/pynq/lib/
export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:/opt/python3.6/lib/python3.6/site-packages/pynq/drivers/
python -m tvm.exec.rpc_server --load-library /home/xilinx/vta/lib/libvta.so
......@@ -29,7 +29,7 @@ BITSTREAM_FILE = 'vta.bit'
for file in [TEST_FILE, CATEG_FILE, RESNET_GRAPH_FILE, RESNET_PARAMS_FILE, BITSTREAM_FILE]:
if not os.path.isfile(file):
print ("Downloading {}".format(file))
wget.download(url+file)
wget.download(url+file)
# Program the FPGA remotely
assert tvm.module.enabled("rpc")
......@@ -129,7 +129,6 @@ with nnvm.compiler.build_config(opt_level=3):
sym, target, shape_dict, dtype_dict,
params=params)
remote = rpc.connect(host, port)
temp = util.tempdir()
lib.save(temp.relpath("graphlib.o"))
remote.upload(temp.relpath("graphlib.o"))
......
......@@ -52,4 +52,4 @@ def debug_mode(debug_flag):
# Add a lower pass to sync uop
build_module.BuildConfig.current.add_lower_pass = debug_mode(0)
build_module.current_build_config().add_lower_pass = debug_mode(0)
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