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Unverified Commit bf132251 by Tianqi Chen Committed by GitHub
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[CI] Improve VTA build message and scripts. (#5170) 

* [CI] Improve VTA build message and scripts.

* Use absolute path to set the env var
parent c38f2f39
Showing with 50 additions and 38 deletions
cmake/modules/VTA.cmake
...@@ -20,17 +20,21 @@ find_program(PYTHON NAMES python python3 python3.6) ...@@ -20,17 +20,21 @@ find_program(PYTHON NAMES python python3 python3.6)
# Throw error if VTA_HW_PATH is not set # Throw error if VTA_HW_PATH is not set
if(NOT DEFINED ENV{VTA_HW_PATH}) if(NOT DEFINED ENV{VTA_HW_PATH})
set(ENV{VTA_HW_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/vta/vta-hw) set(VTA_HW_PATH ${CMAKE_CURRENT_SOURCE_DIR}/vta/vta-hw)
else()
set(VTA_HW_PATH $ENV{VTA_HW_PATH})
endif() endif()
message(STATUS "VTA build with VTA_HW_PATH=" ${VTA_HW_PATH})
if(MSVC) if(MSVC)
message(STATUS "VTA build is skipped in Windows..") message(STATUS "VTA build is skipped in Windows..")
elseif(PYTHON) elseif(PYTHON)
set(VTA_CONFIG ${PYTHON} $ENV{VTA_HW_PATH}/config/vta_config.py) set(VTA_CONFIG ${PYTHON} ${VTA_HW_PATH}/config/vta_config.py)
if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/vta_config.json) if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/vta_config.json)
message(STATUS "Use VTA config " ${CMAKE_CURRENT_BINARY_DIR}/vta_config.json) message(STATUS "Use VTA config " ${CMAKE_CURRENT_BINARY_DIR}/vta_config.json)
set(VTA_CONFIG ${PYTHON} $ENV{VTA_HW_PATH}/config/vta_config.py set(VTA_CONFIG ${PYTHON} ${VTA_HW_PATH}/config/vta_config.py
--use-cfg=${CMAKE_CURRENT_BINARY_DIR}/vta_config.json) --use-cfg=${CMAKE_CURRENT_BINARY_DIR}/vta_config.json)
endif() endif()
...@@ -45,14 +49,14 @@ elseif(PYTHON) ...@@ -45,14 +49,14 @@ elseif(PYTHON)
# Fast simulator driver build # Fast simulator driver build
if(USE_VTA_FSIM) if(USE_VTA_FSIM)
# Add fsim driver sources # Add fsim driver sources
file(GLOB FSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/*.cc) file(GLOB FSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/*.cc)
file(GLOB FSIM_RUNTIME_SRCS vta/runtime/*.cc) file(GLOB FSIM_RUNTIME_SRCS vta/runtime/*.cc)
list(APPEND FSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/sim/sim_driver.cc) list(APPEND FSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/sim/sim_driver.cc)
list(APPEND FSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/sim/sim_tlpp.cc) list(APPEND FSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/sim/sim_tlpp.cc)
list(APPEND FSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/vmem/virtual_memory.cc) list(APPEND FSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/vmem/virtual_memory.cc)
# Target lib: vta_fsim # Target lib: vta_fsim
add_library(vta_fsim SHARED ${FSIM_RUNTIME_SRCS}) add_library(vta_fsim SHARED ${FSIM_RUNTIME_SRCS})
target_include_directories(vta_fsim PUBLIC $ENV{VTA_HW_PATH}/include) target_include_directories(vta_fsim PUBLIC ${VTA_HW_PATH}/include)
foreach(__def ${VTA_DEFINITIONS}) foreach(__def ${VTA_DEFINITIONS})
string(SUBSTRING ${__def} 3 -1 __strip_def) string(SUBSTRING ${__def} 3 -1 __strip_def)
target_compile_definitions(vta_fsim PUBLIC ${__strip_def}) target_compile_definitions(vta_fsim PUBLIC ${__strip_def})
...@@ -66,14 +70,14 @@ elseif(PYTHON) ...@@ -66,14 +70,14 @@ elseif(PYTHON)
# Cycle accurate simulator driver build # Cycle accurate simulator driver build
if(USE_VTA_TSIM) if(USE_VTA_TSIM)
# Add tsim driver sources # Add tsim driver sources
file(GLOB TSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/*.cc) file(GLOB TSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/*.cc)
file(GLOB TSIM_RUNTIME_SRCS vta/runtime/*.cc) file(GLOB TSIM_RUNTIME_SRCS vta/runtime/*.cc)
list(APPEND TSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/tsim/tsim_driver.cc) list(APPEND TSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/tsim/tsim_driver.cc)
list(APPEND TSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/dpi/module.cc) list(APPEND TSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/dpi/module.cc)
list(APPEND TSIM_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/vmem/virtual_memory.cc) list(APPEND TSIM_RUNTIME_SRCS ${VTA_HW_PATH}/src/vmem/virtual_memory.cc)
# Target lib: vta_tsim # Target lib: vta_tsim
add_library(vta_tsim SHARED ${TSIM_RUNTIME_SRCS}) add_library(vta_tsim SHARED ${TSIM_RUNTIME_SRCS})
target_include_directories(vta_tsim PUBLIC $ENV{VTA_HW_PATH}/include) target_include_directories(vta_tsim PUBLIC ${VTA_HW_PATH}/include)
foreach(__def ${VTA_DEFINITIONS}) foreach(__def ${VTA_DEFINITIONS})
string(SUBSTRING ${__def} 3 -1 __strip_def) string(SUBSTRING ${__def} 3 -1 __strip_def)
target_compile_definitions(vta_tsim PUBLIC ${__strip_def}) target_compile_definitions(vta_tsim PUBLIC ${__strip_def})
...@@ -85,15 +89,15 @@ elseif(PYTHON) ...@@ -85,15 +89,15 @@ elseif(PYTHON)
# VTA FPGA driver sources # VTA FPGA driver sources
if(USE_VTA_FPGA) if(USE_VTA_FPGA)
file(GLOB FPGA_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/*.cc) file(GLOB FPGA_RUNTIME_SRCS ${VTA_HW_PATH}/src/*.cc)
# Rules for Zynq-class FPGAs with pynq OS support (see pynq.io) # Rules for Zynq-class FPGAs with pynq OS support (see pynq.io)
if(${VTA_TARGET} STREQUAL "pynq" OR if(${VTA_TARGET} STREQUAL "pynq" OR
${VTA_TARGET} STREQUAL "ultra96") ${VTA_TARGET} STREQUAL "ultra96")
list(APPEND FPGA_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/pynq/pynq_driver.cc) list(APPEND FPGA_RUNTIME_SRCS ${VTA_HW_PATH}/src/pynq/pynq_driver.cc)
# Rules for Pynq v2.4 # Rules for Pynq v2.4
find_library(__cma_lib NAMES cma PATH /usr/lib) find_library(__cma_lib NAMES cma PATH /usr/lib)
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
file(GLOB FPGA_RUNTIME_SRCS $ENV{VTA_HW_PATH}/src/de10nano/*.cc $ENV{VTA_HW_PATH}/src/*.cc) file(GLOB FPGA_RUNTIME_SRCS ${VTA_HW_PATH}/src/de10nano/*.cc ${VTA_HW_PATH}/src/*.cc)
endif() endif()
# Target lib: vta # Target lib: vta
add_library(vta SHARED ${FPGA_RUNTIME_SRCS}) add_library(vta SHARED ${FPGA_RUNTIME_SRCS})
...@@ -107,7 +111,7 @@ elseif(PYTHON) ...@@ -107,7 +111,7 @@ elseif(PYTHON)
target_link_libraries(vta ${__cma_lib}) target_link_libraries(vta ${__cma_lib})
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
#target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21) #target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
target_include_directories(vta PUBLIC $ENV{VTA_HW_PATH}/src/de10nano) target_include_directories(vta PUBLIC ${VTA_HW_PATH}/src/de10nano)
target_include_directories(vta PUBLIC 3rdparty) target_include_directories(vta PUBLIC 3rdparty)
target_include_directories(vta PUBLIC target_include_directories(vta PUBLIC
"/usr/local/intelFPGA_lite/18.1/embedded/ds-5/sw/gcc/arm-linux-gnueabihf/include") "/usr/local/intelFPGA_lite/18.1/embedded/ds-5/sw/gcc/arm-linux-gnueabihf/include")
......
tests/lint/check_file_type.py
...@@ -90,12 +90,12 @@ ALLOW_FILE_NAME = { ...@@ -90,12 +90,12 @@ ALLOW_FILE_NAME = {
".gitmodules", ".gitmodules",
"CODEOWNERS", "CODEOWNERS",
".scalafmt.conf", ".scalafmt.conf",
"Cargo.lock" "Cargo.lock",
"with_the_same_user",
} }
# List of specific files allowed in relpath to <proj_root> # List of specific files allowed in relpath to <proj_root>
ALLOW_SPECIFIC_FILE = { ALLOW_SPECIFIC_FILE = {
"docker/with_the_same_user",
"LICENSE", "LICENSE",
"NOTICE", "NOTICE",
"KEYS", "KEYS",
......
tests/scripts/task_clean.sh
...@@ -16,4 +16,4 @@ ...@@ -16,4 +16,4 @@
# specific language governing permissions and limitations # specific language governing permissions and limitations
# under the License. # under the License.
echo "Cleanup data..." echo "Cleanup data..."
cd $1 && rm -rf Cmake* && cd .. cd $1 && rm -rf CMake* && cd ..
tests/scripts/task_python_vta_fsim.sh
...@@ -19,9 +19,9 @@ ...@@ -19,9 +19,9 @@
set -e set -e
set -u set -u
export TVM_PATH=. export TVM_PATH=`pwd`
export PYTHONPATH=${TVM_PATH}/python:${TVM_PATH}/vta/python:${TVM_PATH}/topi/python export PYTHONPATH=${TVM_PATH}/python:${TVM_PATH}/vta/python:${TVM_PATH}/topi/python
export VTA_HW_PATH=vta/vta-hw export VTA_HW_PATH=`pwd`/vta/vta-hw
# cleanup pycache # cleanup pycache
find . -type f -path "*.pyc" | xargs rm -f find . -type f -path "*.pyc" | xargs rm -f
......
tests/scripts/task_python_vta_tsim.sh
...@@ -19,9 +19,9 @@ ...@@ -19,9 +19,9 @@
set -e set -e
set -u set -u
export TVM_PATH=. export TVM_PATH=`pwd`
export PYTHONPATH=${TVM_PATH}/python:${TVM_PATH}/vta/python:${TVM_PATH}/topi/python export PYTHONPATH=${TVM_PATH}/python:${TVM_PATH}/vta/python:${TVM_PATH}/topi/python
export VTA_HW_PATH=vta/vta-hw export VTA_HW_PATH=`pwd`/vta/vta-hw
# cleanup pycache # cleanup pycache
find . -type f -path "*.pyc" | xargs rm -f find . -type f -path "*.pyc" | xargs rm -f
......
vta/vta-hw/hardware/chisel/Makefile
...@@ -64,10 +64,18 @@ CXX_MAJOR := $(shell $(CXX) -dumpversion | sed 's/\..*//') ...@@ -64,10 +64,18 @@ CXX_MAJOR := $(shell $(CXX) -dumpversion | sed 's/\..*//')
CXX_HAS_ALIGN_NEW := $(shell [ $(CXX_MAJOR) -ge 7 ] && echo true) CXX_HAS_ALIGN_NEW := $(shell [ $(CXX_MAJOR) -ge 7 ] && echo true)
config_test = $(TOP_TEST)$(CONFIG) config_test = $(TOP_TEST)$(CONFIG)
vta_dir = $(abspath ../../)
tvm_dir = $(abspath ../../../../)
verilator_build_dir = $(vta_dir)/$(BUILD_NAME)/verilator ifndef TVM_PATH
chisel_build_dir = $(vta_dir)/$(BUILD_NAME)/chisel TVM_PATH := $(abspath ../../../../)
endif
ifndef VTA_HW_PATH
VTA_HW_PATH := $(abspath ../../)
endif
verilator_build_dir = $(VTA_HW_PATH)/$(BUILD_NAME)/verilator
chisel_build_dir = $(VTA_HW_PATH)/$(BUILD_NAME)/chisel
verilator_opt = --cc verilator_opt = --cc
verilator_opt += +define+RANDOMIZE_GARBAGE_ASSIGN verilator_opt += +define+RANDOMIZE_GARBAGE_ASSIGN
...@@ -100,9 +108,9 @@ cxx_flags += -include V$(TOP_TEST).h ...@@ -100,9 +108,9 @@ cxx_flags += -include V$(TOP_TEST).h
cxx_flags += -I$(verilator_build_dir) cxx_flags += -I$(verilator_build_dir)
cxx_flags += -I$(VERILATOR_INC_DIR) cxx_flags += -I$(VERILATOR_INC_DIR)
cxx_flags += -I$(VERILATOR_INC_DIR)/vltstd cxx_flags += -I$(VERILATOR_INC_DIR)/vltstd
cxx_flags += -I$(vta_dir)/include cxx_flags += -I$(VTA_HW_PATH)/include
cxx_flags += -I$(tvm_dir)/include cxx_flags += -I$(TVM_PATH)/include
cxx_flags += -I$(tvm_dir)/3rdparty/dlpack/include cxx_flags += -I$(TVM_PATH)/3rdparty/dlpack/include
ld_flags = -fPIC -shared ld_flags = -fPIC -shared
...@@ -143,14 +151,14 @@ ifneq ($(USE_THREADS), 0) ...@@ -143,14 +151,14 @@ ifneq ($(USE_THREADS), 0)
cxx_objs += $(verilator_build_dir)/verilated_threads.o cxx_objs += $(verilator_build_dir)/verilated_threads.o
endif endif
VPATH = $(VERILATOR_INC_DIR):$(verilator_build_dir):$(vta_dir)/hardware/dpi VPATH = $(VERILATOR_INC_DIR):$(verilator_build_dir):$(VTA_HW_PATH)/hardware/dpi
# The following is to be consistent with cmake # The following is to be consistent with cmake
ifeq ($(shell uname), Darwin) ifeq ($(shell uname), Darwin)
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).dylib lib_path = $(VTA_HW_PATH)/$(BUILD_NAME)/$(VTA_LIBNAME).dylib
cxx_flags += -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk cxx_flags += -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk
else else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so lib_path = $(VTA_HW_PATH)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif endif
default: lint lib default: lint lib
...@@ -191,7 +199,7 @@ clean: ...@@ -191,7 +199,7 @@ clean:
-rm -rf target project/target project/project test_run_dir -rm -rf target project/target project/project test_run_dir
cleanall: cleanall:
-rm -rf $(vta_dir)/$(BUILD_NAME)/chisel -rm -rf $(VTA_HW_PATH)/$(BUILD_NAME)/chisel
-rm -rf $(vta_dir)/$(BUILD_NAME)/libvta_hw.so -rm -rf $(VTA_HW_PATH)/$(BUILD_NAME)/libvta_hw.so
-rm -rf $(vta_dir)/$(BUILD_NAME)/libvta_hw.dylib -rm -rf $(VTA_HW_PATH)/$(BUILD_NAME)/libvta_hw.dylib
-rm -rf $(vta_dir)/$(BUILD_NAME)/verilator -rm -rf $(VTA_HW_PATH)/$(BUILD_NAME)/verilator
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