Skip to content

T
tic
Unverified Commit 683ed4a3 by Thierry Moreau Committed by GitHub
Options

[VTA] VTA hardware/software codebase re-org (#5037)

parent 14ba49c6
Showing with 166 additions and 195 deletions
Makefile
......@@ -81,7 +81,7 @@ jnilint:
python3 3rdparty/dmlc-core/scripts/lint.py tvm4j-jni cpp jvm/native/src
scalalint:
make -C vta/hardware/chisel lint
make -C vta/vta-hw/hardware/chisel lint
lint: cpplint pylint jnilint scalalint
......
apps/vta_rpc/start_rpc_server_to_tracker.sh
......@@ -18,7 +18,7 @@
PROJROOT="$( cd "$( dirname '${BASH_SOURCE[0]}' )/../../" && pwd )"
# Derive target specified by vta_config.json
VTA_CONFIG=${PROJROOT}/vta/config/vta_config.py
VTA_CONFIG=${PROJROOT}/vta/vta-hw/config/vta_config.py
TARGET=$(python ${VTA_CONFIG} --target)
export PYTHONPATH=${PYTHONPATH}:${PROJROOT}/python:${PROJROOT}/vta/python
......
cmake/modules/VTA.cmake
......@@ -18,14 +18,17 @@
# CMake Build rules for VTA
find_program(PYTHON NAMES python python3 python3.6)
# VTA sources directory
set(VTA_DIR ${CMAKE_CURRENT_SOURCE_DIR}/vta/vta-hw)
if(MSVC)
message(STATUS "VTA build is skipped in Windows..")
elseif(PYTHON)
set(VTA_CONFIG ${PYTHON} ${CMAKE_CURRENT_SOURCE_DIR}/vta/config/vta_config.py)
set(VTA_CONFIG ${PYTHON} ${VTA_DIR}/config/vta_config.py)
if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/vta_config.json)
message(STATUS "Use VTA config " ${CMAKE_CURRENT_BINARY_DIR}/vta_config.json)
set(VTA_CONFIG ${PYTHON} ${CMAKE_CURRENT_SOURCE_DIR}/vta/config/vta_config.py
set(VTA_CONFIG ${PYTHON} ${VTA_DIR}/config/vta_config.py
--use-cfg=${CMAKE_CURRENT_BINARY_DIR}/vta_config.json)
endif()
......@@ -40,18 +43,18 @@ elseif(PYTHON)
# Fast simulator driver build
if(USE_VTA_FSIM)
# Add fsim driver sources
file(GLOB FSIM_RUNTIME_SRCS vta/src/*.cc)
list(APPEND FSIM_RUNTIME_SRCS vta/src/sim/sim_driver.cc)
list(APPEND FSIM_RUNTIME_SRCS vta/src/vmem/virtual_memory.cc vta/src/vmem/virtual_memory.h)
list(APPEND FSIM_RUNTIME_SRCS vta/src/sim/sim_tlpp.cc)
file(GLOB FSIM_RUNTIME_SRCS ${VTA_DIR}/src/*.cc)
file(GLOB FSIM_RUNTIME_SRCS vta/runtime/*.cc)
list(APPEND FSIM_RUNTIME_SRCS ${VTA_DIR}/src/sim/sim_driver.cc)
list(APPEND FSIM_RUNTIME_SRCS ${VTA_DIR}/src/sim/sim_tlpp.cc)
list(APPEND FSIM_RUNTIME_SRCS ${VTA_DIR}/src/vmem/virtual_memory.cc)
# Target lib: vta_fsim
add_library(vta_fsim SHARED ${FSIM_RUNTIME_SRCS})
target_include_directories(vta_fsim PUBLIC vta/include)
target_include_directories(vta_fsim PUBLIC ${VTA_DIR}/include)
foreach(__def ${VTA_DEFINITIONS})
string(SUBSTRING ${__def} 3 -1 __strip_def)
target_compile_definitions(vta_fsim PUBLIC ${__strip_def})
endforeach()
include_directories("vta/include")
if(APPLE)
set_target_properties(vta_fsim PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
endif(APPLE)
......@@ -61,18 +64,18 @@ elseif(PYTHON)
# Cycle accurate simulator driver build
if(USE_VTA_TSIM)
# Add tsim driver sources
file(GLOB TSIM_RUNTIME_SRCS vta/src/*.cc)
list(APPEND TSIM_RUNTIME_SRCS vta/src/tsim/tsim_driver.cc)
list(APPEND TSIM_RUNTIME_SRCS vta/src/dpi/module.cc)
list(APPEND TSIM_RUNTIME_SRCS vta/src/vmem/virtual_memory.cc vta/src/vmem/virtual_memory.h)
file(GLOB TSIM_RUNTIME_SRCS ${VTA_DIR}/src/*.cc)
file(GLOB TSIM_RUNTIME_SRCS vta/runtime/*.cc)
list(APPEND TSIM_RUNTIME_SRCS ${VTA_DIR}/src/tsim/tsim_driver.cc)
list(APPEND TSIM_RUNTIME_SRCS ${VTA_DIR}/src/dpi/module.cc)
list(APPEND TSIM_RUNTIME_SRCS ${VTA_DIR}/src/vmem/virtual_memory.cc)
# Target lib: vta_tsim
add_library(vta_tsim SHARED ${TSIM_RUNTIME_SRCS})
target_include_directories(vta_tsim PUBLIC vta/include)
target_include_directories(vta_tsim PUBLIC ${VTA_DIR}/include)
foreach(__def ${VTA_DEFINITIONS})
string(SUBSTRING ${__def} 3 -1 __strip_def)
target_compile_definitions(vta_tsim PUBLIC ${__strip_def})
endforeach()
include_directories("vta/include")
if(APPLE)
set_target_properties(vta_tsim PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
endif(APPLE)
......@@ -80,15 +83,15 @@ elseif(PYTHON)
# VTA FPGA driver sources
if(USE_VTA_FPGA)
file(GLOB FPGA_RUNTIME_SRCS vta/src/*.cc)
file(GLOB FPGA_RUNTIME_SRCS ${VTA_HW_DIR}/src/*.cc)
# Rules for Zynq-class FPGAs with pynq OS support (see pynq.io)
if(${VTA_TARGET} STREQUAL "pynq" OR
${VTA_TARGET} STREQUAL "ultra96")
list(APPEND FPGA_RUNTIME_SRCS vta/src/pynq/pynq_driver.cc)
list(APPEND FPGA_RUNTIME_SRCS ${VTA_HW_DIR}/src/pynq/pynq_driver.cc)
# Rules for Pynq v2.4
find_library(__cma_lib NAMES cma PATH /usr/lib)
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
file(GLOB FPGA_RUNTIME_SRCS vta/src/de10nano/*.cc vta/src/*.cc)
file(GLOB FPGA_RUNTIME_SRCS ${VTA_HW_DIR}/src/de10nano/*.cc ${VTA_HW_DIR}/src/*.cc)
endif()
# Target lib: vta
add_library(vta SHARED ${FPGA_RUNTIME_SRCS})
......@@ -102,7 +105,7 @@ elseif(PYTHON)
target_link_libraries(vta ${__cma_lib})
elseif(${VTA_TARGET} STREQUAL "de10nano") # DE10-Nano rules
#target_compile_definitions(vta PUBLIC VTA_MAX_XFER=2097152) # (1<<21)
target_include_directories(vta PUBLIC vta/src/de10nano)
target_include_directories(vta PUBLIC ${VTA_HW_DIR}/src/de10nano)
target_include_directories(vta PUBLIC 3rdparty)
target_include_directories(vta PUBLIC
"/usr/local/intelFPGA_lite/18.1/embedded/ds-5/sw/gcc/arm-linux-gnueabihf/include")
......
docs/Doxyfile
......@@ -770,7 +770,7 @@ WARN_LOGFILE =
# spaces.
# Note: If this tag is empty the current directory is searched.
INPUT = include/tvm topi/include/topi vta/include/vta
INPUT = include/tvm topi/include/topi vta/vta-hw/include/vta
# This tag can be used to specify the character encoding of the source files
# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
......
docs/vta/dev/config.rst
......@@ -21,7 +21,7 @@ VTA Configuration
The VTA stack incorporates both a hardware accelerator stack and
a TVM based software stack.
VTA incorporates flexibility out of the box: by modifying the
``vta/config/vta_config.json`` high-level configuration file,
``vta/vta-hw/config/vta_config.json`` high-level configuration file,
the user can change the shape of the tensor intrinsic,
clock frequency, pipelining, data type width, and on-chip buffer sizes.
......
docs/vta/dev/hardware.rst
......@@ -53,17 +53,17 @@ HLS Hardware Source Organization
The VTA design is currently specified in Vivado HLS C++, which is only supported
by Xilinx toolchains.
The VTA hardware sources are contained under ``vta/hardware/xilinx/sources``:
The VTA hardware sources are contained under ``vta/vta-hw/hardware/xilinx/sources``:
- ``vta.cc`` contains the definitions for each VTA module, as well as a top
level behavioral model for the top-level VTA design.
- ``vta.h`` contains type definitions using Xilinx ``ap_int`` types, and
function prototypes declarations.
In addition preprocessor macros are defined under ``vta/include/vta/hw_spec.h``.
In addition preprocessor macros are defined under ``vta/vta-hw/include/vta/hw_spec.h``.
Much of these macro definitions are derived from the parameters listed in the
``vta/config/vta_config.json`` file.
The json file is processed by ``vta/config/vta_config.py`` to produce a string of
``vta/vta-hw/config/vta_config.json`` file.
The json file is processed by ``vta/vta-hw/config/vta_config.py`` to produce a string of
compile flags that define the preprocessor macros.
That string is used by the makefile in order to set those high-level
parameters in both the HLS hardware synthesis compiler, and the C++
......@@ -220,7 +220,7 @@ Microarchitectural Overview
---------------------------
We describe the modules that compose the VTA design.
The module definitions are contained in ``vta/hardware/xilinx/sources/vta.cc``.
The module definitions are contained in ``vta/vta-hw/hardware/xilinx/sources/vta.cc``.
Fetch Module
~~~~~~~~~~~~
......@@ -234,7 +234,7 @@ The fetch module is the entry point of VTA to the CPU and is programmed via thre
The CPU prepares the instruction stream in DRAM in a physically-contiguous buffer prepared by the VTA runtime.
When the instruction stream is ready, the CPU writes the start physical address into the ``insns`` register, the length of the instruction stream into the ``insn_count`` register, and asserts the start signal in the ``control`` register.
This procedure starts VTA, which reads in the instruction stream from DRAM via DMA.
This procedure starts VTA, which reads in the instruction stream from DRAM via DMA.
Upon accessing the instruction stream, the fetch module partially decodes instructions, and pushes those instructions into command queues that feed into the load, compute, and store modules:
......
tests/scripts/task_python_vta.sh deleted 100755 → 0
#!/bin/bash
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# regarding copyright ownership. The ASF licenses this file
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
set -e
set -u
export PYTHONPATH=python:vta/python:topi/python
# cleanup pycache
find . -type f -path "*.pyc" | xargs rm -f
rm -rf ~/.tvm
# Rebuild cython
make cython3
# Reset default fsim simulation
cp vta/config/fsim_sample.json vta/config/vta_config.json
# Run unit tests in functional/fast simulator
echo "Running unittest in fsim..."
python3 -m pytest -v vta/tests/python/unittest
# Run unit tests in functional/fast simulator
echo "Running integration test in fsim..."
python3 -m pytest -v vta/tests/python/integration
tests/scripts/task_python_vta_fsim.sh
......@@ -30,7 +30,7 @@ rm -rf ~/.tvm
make cython3
# Reset default fsim simulation
cp vta/config/fsim_sample.json vta/config/vta_config.json
cp vta/vta-hw/config/fsim_sample.json vta/vta-hw/config/vta_config.json
# Run unit tests in functional/fast simulator
echo "Running unittest in fsim..."
......
tests/scripts/task_python_vta_tsim.sh
......@@ -30,16 +30,22 @@ rm -rf ~/.tvm
make cython3
# Set default VTA config to use TSIM cycle accurate sim
cp vta/config/tsim_sample.json vta/config/vta_config.json
cp vta/vta-hw/config/tsim_sample.json vta/vta-hw/config/vta_config.json
# Build and run the TSIM apps (disable until refactor is complete)
# echo "Test the TSIM apps..."
# make -C vta/vta-hw/apps/tsim_example/ run_verilog
# make -C vta/vta-hw/apps/tsim_example/ run_chisel
# make -C vta/vta-hw/apps/gemm/ default
# Check style of scala code
echo "Check style of scala code..."
make -C vta/hardware/chisel lint
make -C vta/vta-hw/hardware/chisel lint
# Build VTA chisel design and verilator simulator
echo "Building VTA chisel design..."
make -C vta/hardware/chisel cleanall
make -C vta/hardware/chisel USE_THREADS=0 lib
make -C vta/vta-hw/hardware/chisel cleanall
make -C vta/vta-hw/hardware/chisel USE_THREADS=0 lib
# Run unit tests in cycle accurate simulator
echo "Running unittest in tsim..."
......@@ -50,4 +56,4 @@ echo "Running integration test in tsim..."
python3 -m pytest -v vta/tests/python/integration
# Reset default fsim simulation
cp vta/config/fsim_sample.json vta/config/vta_config.json
cp vta/vta-hw/config/fsim_sample.json vta/vta-hw/config/vta_config.json
vta/python/vta/environment.py
......@@ -312,7 +312,7 @@ def _init_env():
os.path.abspath(os.path.expanduser(__file__)))
proj_root = os.path.abspath(os.path.join(curr_path, "../../../"))
path_list = [
os.path.join(proj_root, "vta/config/vta_config.json")
os.path.join(proj_root, "vta/vta-hw/config/vta_config.json")
]
path_list = [p for p in path_list if os.path.exists(p)]
if not path_list:
......
vta/python/vta/libinfo.py
......@@ -40,7 +40,7 @@ def _get_lib_name(lib_name):
def find_libvta(lib_vta, optional=False):
"""Find VTA library
"""Find VTA Chisel-based library
Returns
-------
......@@ -56,10 +56,8 @@ def find_libvta(lib_vta, optional=False):
Enable error check
"""
curr_path = os.path.dirname(os.path.abspath(os.path.expanduser(__file__)))
lib_search = [curr_path]
lib_search += [os.path.join(curr_path, "..", "..", "build",)]
lib_search += [os.path.join(curr_path, "..", "..", "..", "build",)]
lib_search += [os.path.join(curr_path, "..", "..", "..", "build", "Release")]
lib_search = [os.path.join(curr_path, "..", "..", "..", "build",)]
lib_search += [os.path.join(curr_path, "..", "..", "vta-hw", "build")]
lib_name = _get_lib_name(lib_vta)
lib_path = [os.path.join(x, lib_name) for x in lib_search]
lib_found = [x for x in lib_path if os.path.exists(x)]
......
vta/python/vta/pkg_config.py
......@@ -66,21 +66,21 @@ class PkgConfig(object):
# Include path
self.include_path = [
"-I%s/include" % proj_root,
"-I%s/vta/include" % proj_root,
"-I%s/vta/vta-hw/include" % proj_root,
"-I%s/3rdparty/dlpack/include" % proj_root,
"-I%s/3rdparty/dmlc-core/include" % proj_root
]
# List of source files that can be used to build standalone library.
self.lib_source = []
self.lib_source += glob.glob("%s/vta/src/*.cc" % proj_root)
self.lib_source += glob.glob("%s/vta/vta-hw/src/*.cc" % proj_root)
if self.TARGET in ["pynq", "ultra96"]:
# add pynq drivers for any board that uses pynq driver stack (see pynq.io)
self.lib_source += glob.glob("%s/vta/src/pynq/*.cc" % (proj_root))
self.lib_source += glob.glob("%s/vta/vta-hw/src/pynq/*.cc" % (proj_root))
elif self.TARGET in ["de10nano"]:
self.lib_source += glob.glob("%s/vta/src/de10nano/*.cc" % (proj_root))
self.lib_source += glob.glob("%s/vta/vta-hw/src/de10nano/*.cc" % (proj_root))
self.include_path += [
"-I%s/vta/src/de10nano" % proj_root,
"-I%s/vta/vta-hw/src/de10nano" % proj_root,
"-I%s/3rdparty" % proj_root
]
......
vta/python/vta/testing/simulator.py
......@@ -37,7 +37,7 @@ def _load_sw():
if env.TARGET == "tsim":
lib_hw = find_libvta("libvta_hw", optional=True)
assert lib_hw # make sure to build vta/hardware/chisel
assert lib_hw # make sure to build vta/vta-hw/hardware/chisel
try:
f = tvm.get_global_func("vta.tsim.init")
m = tvm.runtime.load_module(lib_hw[0], "vta-tsim")
......
vta/src/device_api.cc → vta/runtime/device_api.cc
......@@ -24,8 +24,8 @@
#include <tvm/runtime/registry.h>
#include <dmlc/thread_local.h>
#include <vta/runtime.h>
#include "runtime.h"
#include "../../src/runtime/workspace_pool.h"
......
vta/src/runtime.cc → vta/runtime/runtime.cc
......@@ -26,15 +26,17 @@
*/
#include <vta/driver.h>
#include <vta/hw_spec.h>
#include <vta/runtime.h>
#include <dmlc/logging.h>
#include <tvm/runtime/c_runtime_api.h>
#include <algorithm>
#include <cassert>
#include <cstring>
#include <vector>
#include <memory>
#include "runtime.h"
namespace vta {
// Avoid bad configurations.
......
vta/include/vta/runtime.h → vta/runtime/runtime.h
......@@ -6,9 +6,9 @@
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
*
* http://www.apache.org/licenses/LICENSE-2.0
*
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
......@@ -22,15 +22,15 @@
* \brief VTA runtime library.
*/
#ifndef VTA_RUNTIME_H_
#define VTA_RUNTIME_H_
#ifndef VTA_RUNTIME_RUNTIME_H_
#define VTA_RUNTIME_RUNTIME_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <tvm/runtime/c_runtime_api.h>
#include "driver.h"
#include <vta/driver.h>
#define VTA_MEMCPY_H2D 1
#define VTA_MEMCPY_D2H 2
......@@ -291,4 +291,4 @@ TVM_DLL void VTASynchronize(VTACommandHandle cmd, uint32_t wait_cycles);
#ifdef __cplusplus
}
#endif
#endif // VTA_RUNTIME_H_
#endif // VTA_RUNTIME_RUNTIME_H_
vta/tutorials/autotvm/tune_relay_vta.py
......@@ -181,7 +181,7 @@ def compile_network(env, target, model, start_pack, stop_pack):
tracker_host = os.environ.get("TVM_TRACKER_HOST", '0.0.0.0')
tracker_port = int(os.environ.get("TVM_TRACKER_PORT", 9190))
# Load VTA parameters from the vta/config/vta_config.json file
# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
env = vta.get_env()
# This target is used for cross compilation. You can query it by :code:`gcc -v` on your device.
......
vta/tutorials/frontend/deploy_classification.py
......@@ -68,7 +68,7 @@ assert tvm.runtime.enabled("rpc")
# -------------------------------------
# Execute on CPU vs. VTA, and define the model.
# Load VTA parameters from the vta/config/vta_config.json file
# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
env = vta.get_env()
# Set ``device=arm_cpu`` to run inference on the CPU
......
vta/tutorials/frontend/deploy_detection.py
......@@ -111,7 +111,7 @@ names = [x.strip() for x in content]
# --------------------------------------
# Execute on CPU vs. VTA, and define the model.
# Load VTA parameters from the vta/config/vta_config.json file
# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
env = vta.get_env()
# Set ``device=arm_cpu`` to run inference on the CPU
# or ``device=vta`` to run inference on the FPGA.
......
vta/tutorials/matrix_multiply.py
......@@ -43,7 +43,7 @@ from tvm import rpc
from tvm.contrib import util
from vta.testing import simulator
# Load VTA parameters from the vta/config/vta_config.json file
# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
env = vta.get_env()
# We read the Pynq RPC host IP address and port number from the OS environment
......
vta/tutorials/optimize/convolution_opt.py
......@@ -47,7 +47,7 @@ from tvm import rpc
from tvm.contrib import util
from vta.testing import simulator
# Load VTA parameters from the vta/config/vta_config.json file
# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
env = vta.get_env()
# We read the Pynq RPC host IP address and port number from the OS environment
......
vta/tutorials/optimize/matrix_multiply_opt.py
......@@ -46,7 +46,7 @@ from tvm import rpc
from tvm.contrib import util
from vta.testing import simulator
# Load VTA parameters from the vta/config/vta_config.json file
# Load VTA parameters from the vta/vta-hw/config/vta_config.json file
env = vta.get_env()
# We read the Pynq RPC host IP address and port number from the OS environment
......
vta/apps/gemm/CMakeLists.txt → vta/vta-hw/apps/gemm/CMakeLists.txt
......@@ -18,13 +18,13 @@
cmake_minimum_required(VERSION 3.2)
project(tsim C CXX)
set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../)
set(VTA_DIR ${TVM_DIR}/vta)
set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../../)
set(VTA_HW_DIR ${TVM_DIR}/3rdparty/vta-hw)
include_directories("${TVM_DIR}/include")
include_directories("${TVM_DIR}/3rdparty/dlpack/include")
include_directories("${TVM_DIR}/3rdparty/dmlc-core/include")
include_directories("${TVM_DIR}/vta/src/dpi")
include_directories("${VTA_HW_DIR}/src/dpi")
set(CMAKE_C_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden")
set(CMAKE_CXX_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden -std=c++11")
......@@ -35,11 +35,11 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND
endif()
file(GLOB TSIM_SW_SRC src/driver.cc)
list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/vmem/virtual_memory.cc)
list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/dpi/module.cc)
list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/vmem/virtual_memory.cc)
list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/dpi/module.cc)
add_library(sw SHARED ${TSIM_SW_SRC})
target_include_directories(sw PRIVATE ${VTA_DIR}/include ${VTA_DIR}/src)
target_include_directories(sw PRIVATE ${VTA_HW_DIR}/include ${VTA_HW_DIR}/src)
if(APPLE)
set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
......
vta/apps/gemm/Makefile → vta/vta-hw/apps/gemm/Makefile
......@@ -15,15 +15,15 @@
# specific language governing permissions and limitations
# under the License.
export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
export PYTHONPATH:=$(abspath .)/python:$(PYTHONPATH)
export PYTHONPATH:=$(abspath .)/../../../../python:$(PYTHONPATH)
BUILD_NAME = build
build_dir = $(abspath .)/$(BUILD_NAME)
default: chisel driver
python3 tests/python/chisel_accel.py serial
default: chisel driver serial parallel
serial:
serial:
python3 tests/python/chisel_accel.py serial
parallel:
......
vta/apps/gemm/README.md → vta/vta-hw/apps/gemm/README.md
......@@ -15,9 +15,9 @@
<!--- specific language governing permissions and limitations -->
<!--- under the License. -->
VTA TSIM Application
VTA TSIM Application
======================
Prior to this application, please take a look at `<tvm-root>/vta/apps/tsim_example` for installation
Prior to this application, please take a look at `<tvm-root>/vta/vta-hw/apps/tsim_example` for installation
This is an application that performs Bit Serial Multiplication for GEMM utilizing TSIM.
**Bit Serial Multiplication for GEMM:**
......@@ -28,23 +28,23 @@ We approach this operation with slicing and shifting, like how basic multiplicat
We can sufficiently reduce the cycles required to perform a gemm given that the data bit width is small. This GEMM application uses TSIM for future accerlerator prototypes.
* Test Chisel3 backend with bit serial GEMM
* Go to `<tvm-root>/vta/apps/gemm`
* Go to `<tvm-root>/vta/vta-hw/apps/gemm`
* Run `make`
* If you have already compiled chisel backend (i.e. ran `make`)
* If you have already compiled chisel backend (i.e. ran `make`)
* Bit Serial test with another input set, run `make serial`
* Bit parallel test with another input set, run `make parallel`
* Some steps for creating your own custom TSIM application
* Go to `<tvm-root>/vta/apps/gemm`
* Go to `<tvm-root>/vta/vta-hw/apps/gemm`
* Create custom circuit within `./hardware/chisel/src/scala.main/accel/Compute.scala`
* Map the according Registers in `./hardware/chisel/src/scala.main/accel/RegFile.scala`
* Create your test script
* Map the registers in `./src/driver.cc` and link it with both `RegFile.scala` and the test script
* Understanding of `<tvm-root>/vta/apps/tsim_example`, which performs add by one to a vector, is highly encouraged to create a more complex application
* Understanding of `<tvm-root>/vta/vta-hw/apps/tsim_example`, which performs add by one to a vector, is highly encouraged to create a more complex application
* Some pointers
* Chisel3 tests in `<tvm-root>/vta/apps/gemm/tests/python`
* Chisel3 accelerator backend `<tvm-root>/vta/apps/gemm/hardware/chisel`
* Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/apps/gemm/src/driver.cc`
* Software Python driver (frontend) that handles the accelerator `<tvm-root>/vta/apps/gemm/python/accel`
* Chisel3 tests in `<tvm-root>/vta/vta-hw/apps/gemm/tests/python`
* Chisel3 accelerator backend `<tvm-root>/vta/vta-hw/apps/gemm/hardware/chisel`
* Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/vta-hw/apps/gemm/src/driver.cc`
* Software Python driver (frontend) that handles the accelerator `<tvm-root>vtay/vta-hw/apps/gemm/python/accel`
vta/apps/gemm/hardware/chisel/Makefile → vta/vta-hw/apps/gemm/hardware/chisel/Makefile
......@@ -38,7 +38,7 @@ USE_TRACE = 1
LIBNAME = libhw
vta_dir = $(abspath ../../../../)
tvm_dir = $(abspath ../../../../../)
tvm_dir = $(abspath ../../../../../../)
build_dir = $(abspath .)/$(BUILD_NAME)
verilator_build_dir = $(build_dir)/verilator
chisel_build_dir = $(build_dir)/chisel
......
vta/apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala → vta/vta-hw/apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala
......@@ -89,7 +89,7 @@ class Compute(implicit config: AccelConfig) extends Module {
is (sReadAData) {
when (io.mem.rd.valid) {
state := sReadADone
}
}
}
is (sReadADone) {
when (cntwgt === (length * length) - 1.U) {
......@@ -180,8 +180,8 @@ class Compute(implicit config: AccelConfig) extends Module {
}
io.mem.rd.ready := state === sReadAData | state === sReadBData
mvc.io.inp.data.valid := state === sInpDone // 2 inputs have been processed
mvc.io.wgt.data.valid := state === sInpDone // 2 inputs have been processed
mvc.io.inp.data.valid := state === sInpDone // 2 inputs have been processed
mvc.io.wgt.data.valid := state === sInpDone // 2 inputs have been processed
mvc.io.wgt.data.bits <> reg1
mvc.io.inp.data.bits <> reg2
......@@ -198,7 +198,7 @@ class Compute(implicit config: AccelConfig) extends Module {
accum.io.valid := mvc.io.acc_o.data.valid
// write
io.mem.wr.valid := state === sWriteData
io.mem.wr.valid := state === sWriteData
io.mem.wr.bits := accum.io.sum(cntout)
// count read/write
......
vta/apps/tsim_example/CMakeLists.txt → vta/vta-hw/apps/tsim_example/CMakeLists.txt
......@@ -18,13 +18,13 @@
cmake_minimum_required(VERSION 3.2)
project(tsim C CXX)
set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../)
set(VTA_DIR ${TVM_DIR}/vta)
set(TVM_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../../../)
set(VTA_HW_DIR ${TVM_DIR}/vta/vta-hw)
include_directories("${TVM_DIR}/include")
include_directories("${TVM_DIR}/3rdparty/dlpack/include")
include_directories("${TVM_DIR}/3rdparty/dmlc-core/include")
include_directories("${TVM_DIR}/vta/src/dpi")
include_directories("${VTA_HW_DIR}/src/dpi")
set(CMAKE_C_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden")
set(CMAKE_CXX_FLAGS "-O2 -Wall -fPIC -fvisibility=hidden -std=c++11")
......@@ -35,11 +35,11 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND
endif()
file(GLOB TSIM_SW_SRC src/driver.cc)
list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/vmem/virtual_memory.cc)
list(APPEND TSIM_SW_SRC ${VTA_DIR}/src/dpi/module.cc)
list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/vmem/virtual_memory.cc)
list(APPEND TSIM_SW_SRC ${VTA_HW_DIR}/src/dpi/module.cc)
add_library(sw SHARED ${TSIM_SW_SRC})
target_include_directories(sw PRIVATE ${VTA_DIR}/include ${VTA_DIR}/src)
target_include_directories(sw PRIVATE ${VTA_HW_DIR}/include ${VTA_HW_DIR}/src)
if(APPLE)
set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
......
vta/apps/tsim_example/Makefile → vta/vta-hw/apps/tsim_example/Makefile
......@@ -20,7 +20,9 @@ export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
BUILD_NAME = build
build_dir = $(abspath .)/$(BUILD_NAME)
default: verilog driver
default: run_verilog
run_verilog: verilog driver
python3 tests/python/verilog_accel.py
run_chisel: chisel driver
......
vta/apps/tsim_example/README.md → vta/vta-hw/apps/tsim_example/README.md
......@@ -55,7 +55,7 @@ verilator --version
the supported version of Verilator should be at least 4.012,
if homebrew (OSX) or package-manager (Linux) does not support that version,
please install Verilator 4.012 or later from binary or source base on following
instruction of Verilator wiki.
instruction of Verilator wiki.
https://www.veripool.org/projects/verilator/wiki/Installing
......@@ -72,16 +72,16 @@ The default target language for these two implementations is Verilog. The follow
how to run both of them:
* Test Verilog backend
* Go to `<tvm-root>/vta/apps/tsim_example`
* Go to `<tvm-root>/vta/vta-hw/apps/tsim_example`
* Run `make`
* Test Chisel3 backend
* Go to `<tvm-root>/vta/apps/tsim_example`
* Go to `<tvm-root>/vta/vta-hw/apps/tsim_example`
* Run `make run_chisel`
* Some pointers
* Verilog and Chisel3 tests in `<tvm-root>/vta/apps/tsim_example/tests/python`
* Verilog accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
* Chisel3 accelerator backend `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
* Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
* Software Python driver (frontend) that handles the accelerator `<tvm-root>/vta/apps/tsim_example/python/accel`
* Verilog and Chisel3 tests in `<tvm-root>/vta/vta-hw/apps/tsim_example/tests/python`
* Verilog accelerator backend `<tvm-root>/vta/vta-hw/apps/tsim_example/hardware/verilog`
* Chisel3 accelerator backend `<tvm-root>/vta/vta-hw/apps/tsim_example/hardware/chisel`
* Software C++ driver (backend) that handles the accelerator `<tvm-root>/vta/vta-hw/apps/tsim_example/src/driver.cc`
* Software Python driver (frontend) that handles the accelerator `<tvm-root>vtay/vta-hw/apps/tsim_example/python/accel`
vta/apps/tsim_example/hardware/chisel/Makefile → vta/vta-hw/apps/tsim_example/hardware/chisel/Makefile
......@@ -38,7 +38,7 @@ USE_TRACE = 0
LIBNAME = libhw
vta_dir = $(abspath ../../../../)
tvm_dir = $(abspath ../../../../../)
tvm_dir = $(abspath ../../../../../../)
build_dir = $(abspath .)/$(BUILD_NAME)
verilator_build_dir = $(build_dir)/verilator
chisel_build_dir = $(build_dir)/chisel
......
vta/apps/tsim_example/hardware/verilog/Makefile → vta/vta-hw/apps/tsim_example/hardware/verilog/Makefile
......@@ -38,7 +38,7 @@ USE_TRACE = 0
LIBNAME = libhw
vta_dir = $(abspath ../../../../)
tvm_dir = $(abspath ../../../../../)
tvm_dir = $(abspath ../../../../../../)
build_dir = $(abspath .)/$(BUILD_NAME)
verilator_opt = --cc
......
vta/config/vta_config.py → vta/vta-hw/config/vta_config.py
......@@ -23,7 +23,7 @@ import argparse
def get_pkg_config(cfg):
"""Get the pkg config object."""
curr_path = os.path.dirname(os.path.abspath(os.path.expanduser(__file__)))
proj_root = os.path.abspath(os.path.join(curr_path, "../../"))
proj_root = os.path.abspath(os.path.join(curr_path, "../../../"))
pkg_config_py = os.path.join(proj_root, "vta/python/vta/pkg_config.py")
libpkg = {"__file__": pkg_config_py}
exec(compile(open(pkg_config_py, "rb").read(), pkg_config_py, "exec"), libpkg, libpkg)
......@@ -107,9 +107,9 @@ def main():
curr_path = os.path.dirname(
os.path.abspath(os.path.expanduser(__file__)))
proj_root = os.path.abspath(os.path.join(curr_path, "../../"))
proj_root = os.path.abspath(os.path.join(curr_path, "../../../"))
path_list = [
os.path.join(proj_root, "vta/config/vta_config.json")
os.path.join(proj_root, "vta/vta-hw/config/vta_config.json")
]
if args.use_cfg:
path_list = [args.use_cfg]
......
vta/hardware/chisel/Makefile → vta/vta-hw/hardware/chisel/Makefile
......@@ -21,15 +21,15 @@ endif
# Change VERILATOR_INC_DIR if Verilator is installed on a different location
ifeq (, $(VERILATOR_INC_DIR))
ifeq (, $(wildcard /usr/local/share/verilator/include/*))
ifeq (, $(wildcard /usr/share/verilator/include/*))
$(error "Verilator include directory is not set properly")
else
VERILATOR_INC_DIR := /usr/share/verilator/include
endif
else
VERILATOR_INC_DIR := /usr/local/share/verilator/include
endif
ifeq (, $(wildcard /usr/local/share/verilator/include/*))
ifeq (, $(wildcard /usr/share/verilator/include/*))
$(error "Verilator include directory is not set properly")
else
VERILATOR_INC_DIR := /usr/share/verilator/include
endif
else
VERILATOR_INC_DIR := /usr/local/share/verilator/include
endif
endif
CONFIG = DefaultDe10Config
......@@ -49,7 +49,7 @@ USE_TRACE_FST = 0
# This will significantly increase the trace size and should only be used
# on a per need basis for difficult debug problems.
USE_TRACE_DETAILED = 0
USE_THREADS = $(shell nproc)
USE_THREADS = 0
VTA_LIBNAME = libvta_hw
UNITTEST_NAME = all
CXX = g++
......@@ -65,7 +65,7 @@ CXX_HAS_ALIGN_NEW := $(shell [ $(CXX_MAJOR) -ge 7 ] && echo true)
config_test = $(TOP_TEST)$(CONFIG)
vta_dir = $(abspath ../../)
tvm_dir = $(abspath ../../../)
tvm_dir = $(abspath ../../../../)
verilator_build_dir = $(vta_dir)/$(BUILD_NAME)/verilator
chisel_build_dir = $(vta_dir)/$(BUILD_NAME)/chisel
......@@ -81,14 +81,14 @@ verilator_opt += -Mdir ${verilator_build_dir}
verilator_opt += -I$(chisel_build_dir)
ifeq ($(DEBUG), 0)
cxx_flags = -O2 -Wall -fvisibility=hidden
cxx_flags = -O2 -Wall -fvisibility=hidden
else
cxx_flags = -O0 -g -Wall
cxx_flags = -O0 -g -Wall
endif
cxx_flags += -std=c++11 -Wno-maybe-uninitialized
ifeq ($(CXX_HAS_ALIGN_NEW),true)
cxx_flags += -faligned-new
cxx_flags += -faligned-new
endif
cxx_flags += -DVL_TSIM_NAME=V$(TOP_TEST)
cxx_flags += -DVL_PRINTF=printf
......@@ -107,50 +107,50 @@ cxx_flags += -I$(tvm_dir)/3rdparty/dlpack/include
ld_flags = -fPIC -shared
ifeq ($(SANITIZE), 1)
ifeq ($(DEBUG), 1)
cxx_flags += -fno-omit-frame-pointer -fsanitize=address -fsanitize-recover=address
ld_flags += -fno-omit-frame-pointer -fsanitize=address -fsanitize-recover=address
endif
ifeq ($(DEBUG), 1)
cxx_flags += -fno-omit-frame-pointer -fsanitize=address -fsanitize-recover=address
ld_flags += -fno-omit-frame-pointer -fsanitize=address -fsanitize-recover=address
endif
endif
cxx_objs = $(verilator_build_dir)/verilated.o $(verilator_build_dir)/verilated_dpi.o $(verilator_build_dir)/tsim_device.o
ifneq ($(USE_TRACE), 0)
cxx_flags += -DVM_TRACE=1
ifeq ($(USE_TRACE_FST), 1)
cxx_flags += -DVM_TRACE_FST
verilator_opt += --trace-fst
else
verilator_opt += --trace
endif
ifeq ($(USE_TRACE_DETAILED), 1)
verilator_opt += --trace-underscore --trace-structs
endif
ifeq ($(USE_TRACE_FST), 1)
cxx_flags += -DTSIM_TRACE_FILE=$(verilator_build_dir)/$(TOP_TEST).fst
cxx_objs += $(verilator_build_dir)/verilated_fst_c.o
else
cxx_flags += -DTSIM_TRACE_FILE=$(verilator_build_dir)/$(TOP_TEST).vcd
cxx_objs += $(verilator_build_dir)/verilated_vcd_c.o
endif
cxx_flags += -DVM_TRACE=1
ifeq ($(USE_TRACE_FST), 1)
cxx_flags += -DVM_TRACE_FST
verilator_opt += --trace-fst
else
verilator_opt += --trace
endif
ifeq ($(USE_TRACE_DETAILED), 1)
verilator_opt += --trace-underscore --trace-structs
endif
ifeq ($(USE_TRACE_FST), 1)
cxx_flags += -DTSIM_TRACE_FILE=$(verilator_build_dir)/$(TOP_TEST).fst
cxx_objs += $(verilator_build_dir)/verilated_fst_c.o
else
cxx_flags += -DTSIM_TRACE_FILE=$(verilator_build_dir)/$(TOP_TEST).vcd
cxx_objs += $(verilator_build_dir)/verilated_vcd_c.o
endif
else
cxx_flags += -DVM_TRACE=0
cxx_flags += -DVM_TRACE=0
endif
ifneq ($(USE_THREADS), 0)
verilator_opt += --threads $(USE_THREADS)
cxx_flags += -DVL_THREADED
cxx_objs += $(verilator_build_dir)/verilated_threads.o
verilator_opt += --threads $(USE_THREADS)
cxx_flags += -DVL_THREADED
cxx_objs += $(verilator_build_dir)/verilated_threads.o
endif
VPATH = $(VERILATOR_INC_DIR):$(verilator_build_dir):$(vta_dir)/hardware/dpi
# The following is to be consistent with cmake
ifeq ($(shell uname), Darwin)
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).dylib
cxx_flags += -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).dylib
cxx_flags += -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk
else
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
lib_path = $(vta_dir)/$(BUILD_NAME)/$(VTA_LIBNAME).so
endif
default: lint lib
......@@ -193,4 +193,5 @@ clean:
cleanall:
-rm -rf $(vta_dir)/$(BUILD_NAME)/chisel
-rm -rf $(vta_dir)/$(BUILD_NAME)/libvta_hw.so
-rm -rf $(vta_dir)/$(BUILD_NAME)/libvta_hw.dylib
-rm -rf $(vta_dir)/$(BUILD_NAME)/verilator
vta/hardware/chisel/README.md → vta/vta-hw/hardware/chisel/README.md
......@@ -15,16 +15,16 @@
<!--- specific language governing permissions and limitations -->
<!--- under the License. -->
VTA in Chisel
VTA in Chisel
===================================================
For contributors who wants to test a chisel module:
- You can add your test files in `src/test/scala/unitttest`
- Add your test name and tests to the `test` object in `src/test/scala/unitttest/Launcher.scala`
- Check out the provided sample test `mvm` which tests the MatrixVectorComputation module
in `src/main/scala/core/TensorGemm.scala`
- Running unit tests: `make test test_name=your_own test_name`
vta/hardware/chisel/build.sbt → vta/vta-hw/hardware/chisel/build.sbt
......@@ -62,7 +62,7 @@ resolvers ++= Seq(
val defaultVersions = Map(
"chisel3" -> "3.1.7",
"chisel-iotesters" -> "[1.2.5,1.3-SNAPSHOT["
"chisel-iotesters" -> "1.2.4"
)
libraryDependencies ++= Seq("chisel3","chisel-iotesters").map {
......
vta/hardware/chisel/project/build.properties → vta/vta-hw/hardware/chisel/project/build.properties
......@@ -17,4 +17,4 @@
* under the License.
*/
sbt.version = 1.1.1
sbt.version = 1.3.2
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment