[VTA][Dockerfile] Chisel dependencies for TSIM CI (#3721)

docker/Dockerfile.ci_cpu

@@ -59,10 +59,13 @@ RUN bash /install/ubuntu_install_nnpack.sh
 
 ENV PATH $PATH:$CARGO_HOME/bin:/usr/lib/go-1.10/bin
 
-
 # ANTLR deps
 COPY install/ubuntu_install_java.sh /install/ubuntu_install_java.sh
 RUN bash /install/ubuntu_install_java.sh
 
 COPY install/ubuntu_install_antlr.sh /install/ubuntu_install_antlr.sh
 RUN bash /install/ubuntu_install_antlr.sh
+
+# Chisel deps for TSIM
+COPY install/ubuntu_install_chisel.sh /install/ubuntu_install_chisel.sh
+RUN bash /install/ubuntu_install_chisel.sh

docker/Dockerfile.ci_i386

@@ -37,3 +37,7 @@ RUN bash /install/ubuntu_install_python_package.sh
 # AutoTVM deps
 COPY install/ubuntu_install_redis.sh /install/ubuntu_install_redis.sh
 RUN bash /install/ubuntu_install_redis.sh
+
+# Chisel deps for TSIM
+COPY install/ubuntu_install_chisel.sh /install/ubuntu_install_chisel.sh
+RUN bash /install/ubuntu_install_chisel.sh

docker/Dockerfile.demo_cpu

@@ -40,6 +40,12 @@ RUN pip3 install matplotlib Image Pillow jupyter[notebook]
 # Deep learning frameworks
 RUN pip3 install mxnet tensorflow keras gluoncv dgl
 
+# Chisel
+RUN echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
+RUN sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
+RUN sudo apt-get update
+RUN sudo apt-get install -y verilator sbt
+
 # Build TVM
 COPY install/install_tvm_cpu.sh /install/install_tvm_cpu.sh
 RUN bash /install/install_tvm_cpu.sh

docker/install/ubuntu_install_chisel.sh

+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+set -e
+set -u
+set -o pipefail
+
+# Install the necessary dependencies for Chisel
+echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
+sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
+sudo apt-get update
+sudo apt-get install -y verilator sbt

tests/scripts/task_python_vta.sh

@@ -27,8 +27,27 @@ rm -rf ~/.tvm
 # Rebuild cython
 make cython3
 
-echo "Running unittest..."
+# Run unit tests in functional/fast simulator
+echo "Running unittest in fsim..."
 python3 -m nose -v vta/tests/python/unittest
 
-echo "Running integration test..."
+# Run unit tests in functional/fast simulator
+echo "Running integration test in fsim..."
 python3 -m nose -v vta/tests/python/integration
+
+# # Build VTA chisel design and verilator simulator
+# cd vta/hardware/chisel/ && make && cd -
+
+# # Set default VTA config to use TSIM cycle accurate sim
+# cp vta/config/tsim_sample.json vta/config/vta_config.json
+
+# # Run unit tests in functional/fast simulator
+# echo "Running unittest in tsim..."
+# python3 -m nose -v vta/tests/python/unittest
+
+# # Run unit tests in functional/fast simulator
+# echo "Running integration test in tsim..."
+# python3 -m nose -v vta/tests/python/integration
+
+# # Reset default fsim simulation
+# cp vta/config/fsim_sample.json vta/config/vta_config.json
\ No newline at end of file

vta/config/fsim_sample.json

+{
+  "TARGET" : "sim",
+  "HW_VER" : "0.0.1",
+  "LOG_INP_WIDTH" : 3,
+  "LOG_WGT_WIDTH" : 3,
+  "LOG_ACC_WIDTH" : 5,
+  "LOG_BATCH" : 0,
+  "LOG_BLOCK" : 4,
+  "LOG_UOP_BUFF_SIZE" : 15,
+  "LOG_INP_BUFF_SIZE" : 15,
+  "LOG_WGT_BUFF_SIZE" : 18,
+  "LOG_ACC_BUFF_SIZE" : 17
+}

vta/config/tsim_sample.json

+{
+  "TARGET" : "tsim",
+  "HW_VER" : "0.0.1",
+  "LOG_INP_WIDTH" : 3,
+  "LOG_WGT_WIDTH" : 3,
+  "LOG_ACC_WIDTH" : 5,
+  "LOG_BATCH" : 0,
+  "LOG_BLOCK" : 4,
+  "LOG_UOP_BUFF_SIZE" : 15,
+  "LOG_INP_BUFF_SIZE" : 15,
+  "LOG_WGT_BUFF_SIZE" : 18,
+  "LOG_ACC_BUFF_SIZE" : 17
+}