[VTA] [APPS] [TSIM] small naming fix (#3293)

* make off lowercase

* update README

vta/apps/tsim_example/README.md

@@ -49,8 +49,7 @@ sudo apt install verilator sbt
 ## Setup in TVM
 
 1. Install `verilator` and `sbt` as described above
-2. Set the VTA TARGET to `tsim` on `<tvm-root>/vta/config/vta_config.json`
-3. Build tvm
+2. Build tvm
 
 ## How to run VTA TSIM examples
 
@@ -60,7 +59,7 @@ These examples are located at `<tvm-root>/vta/apps/tsim_example`.
 * Instructions
     * Open `<tvm-root>/vta/apps/tsim_example/python/tsim/config.json`
     * Change `TARGET` from `verilog` to `chisel`, depending on what language backend you would like to test
-    * Go to `tvm/vta/apps/tsim`
+    * Go to `tvm/vta/apps/tsim_example`
     * Run `make`
 
 * Some pointers

vta/apps/tsim_example/cmake/modules/hw.cmake

@@ -87,7 +87,7 @@ else()
     if (TSIM_TARGET STREQUAL "chisel" OR TSIM_TARGET STREQUAL "verilog")
 
       # Check if tracing can be enabled
-      if (NOT TSIM_USE_TRACE STREQUAL "OFF")
+      if (NOT TSIM_USE_TRACE STREQUAL "off")
         message(STATUS "[TSIM_HW] Verilog enable tracing")
       else()
         message(STATUS "[TSIM_HW] Verilator disable tracing")
@@ -101,7 +101,7 @@ else()
       list(APPEND VERILATOR_OPT --top-module ${TSIM_TOP_NAME} -Mdir ${VERILATOR_BUILD_DIR})
       list(APPEND VERILATOR_OPT --cc ${VERILATOR_RTL_SRC})
 
-      if (NOT TSIM_USE_TRACE STREQUAL "OFF")
+      if (NOT TSIM_USE_TRACE STREQUAL "off")
         list(APPEND VERILATOR_OPT --trace)
       endif()
 
@@ -116,7 +116,7 @@ else()
       set(VERILATOR_INC_DIR /usr/local/share/verilator/include)
       set(VERILATOR_LIB_SRC ${VERILATOR_INC_DIR}/verilated.cpp ${VERILATOR_INC_DIR}/verilated_dpi.cpp)
 
-      if (NOT TSIM_USE_TRACE STREQUAL "OFF")
+      if (NOT TSIM_USE_TRACE STREQUAL "off")
         list(APPEND VERILATOR_LIB_SRC ${VERILATOR_INC_DIR}/verilated_vcd_c.cpp)
       endif()
 
@@ -125,7 +125,7 @@ else()
       add_library(hw SHARED ${VERILATOR_LIB_SRC} ${VERILATOR_GEN_SRC} ${VERILATOR_SRC})
 
       set(VERILATOR_DEF VL_USER_FINISH VL_TSIM_NAME=V${TSIM_TOP_NAME} VL_PRINTF=printf VM_COVERAGE=0 VM_SC=0)
-      if (NOT TSIM_USE_TRACE STREQUAL "OFF")
+      if (NOT TSIM_USE_TRACE STREQUAL "off")
         list(APPEND VERILATOR_DEF VM_TRACE=1 TSIM_TRACE_FILE=${TSIM_BUILD_DIR}/${TSIM_TRACE_NAME}.vcd)
       else()
         list(APPEND VERILATOR_DEF VM_TRACE=0)

vta/apps/tsim_example/config/config.json

@@ -2,6 +2,6 @@
   "TARGET" : "verilog",
   "TOP_NAME" : "TestAccel",
   "BUILD_NAME" : "build",
-  "USE_TRACE" : "OFF",
+  "USE_TRACE" : "off",
   "TRACE_NAME" : "trace"
 }