Fix verilog testcase (#1047)

4b72f293 · Tianqi Chen · GitHub · 1ab05faf · 4b72f293
Commit 4b72f293 authored Mar 24, 2018 by Tianqi Chen Committed by GitHub Mar 24, 2018
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tests/verilog/integration/test_codegen_verilog.py
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--- a/tests/verilog/integration/test_codegen_verilog.py
+++ b/tests/verilog/integration/test_codegen_verilog.py
@@ -18,7 +18,7 @@ def lower(s, args, name):
    stmt = tvm.ir_pass.CanonicalSimplify(stmt)
    stmt = tvm.ir_pass.Simplify(stmt)
    stmt = tvm.ir_pass.SplitPipeline(stmt, True)
-    fapi = tvm.ir_pass.MakeAPI(stmt, name, arg_list, 0)
+    fapi = tvm.ir_pass.MakeAPI(stmt, name, arg_list, 0, True)
    return fapi

 @tvm.register_func