Acknowledge related projects (#465)

* [CODEGEN] Redo CodegenLLVM.

* Add remarks about origin of the pass

Properly acknowledge related projects

* Fix and expression

README.md

@@ -28,3 +28,12 @@ TVM adopts apache committer model, we aim to create an open source project that
 - [Contributor Guide](docs/how_to/contribute.md)
 - Please add your name to [CONTRIBUTORS.md](CONTRIBUTORS.md)
 - Please also update [NEWS.md](NEWS.md) on changes and improvements in API and codes.
+
+Acknowledgement
+---------------
+We learnt a lot from the following projects when building TVM.
+- [Halide](https://github.com/halide/Halide): TVM uses [HalideIR](https://github.com/dmlc/HalideIR) as data structure for
+  arithematic simplification and low level lowering. HalideIR is derived from Halide.
+  We also learns from Halide when implementing the lowering pipeline in TVM.
+- [Loopy](https://github.com/inducer/loopy): use of integer set analysis and its loop transformation primitives.
+- [Theano](https://github.com/Theano/Theano): the design inspiration of symbolic scan operator for recurrence.

src/codegen/llvm/codegen_llvm.h

@@ -242,6 +242,8 @@ class CodeGenLLVM :
   std::unordered_map<const Variable*, arith::ModularEntry> align_map_;
   // set of var that are not restricted(can alias)
   std::unordered_set<const Variable*> alias_var_set_;
+  // set of volatile buffer.
+  std::unordered_set<const Variable*> volatile_buf_;
 };
 }  // namespace codegen
 }  // namespace tvm

src/pass/vectorize_loop.cc

@@ -28,7 +28,13 @@ inline Expr BroadcastTo(Expr e, int lanes) {
 }
 
 // Rewrite vectorized allocation access
+// This is necessary for making each vector component containing its own workspace.
+// Originates from Halide's loop vectorizer
+//
 // s[i] = s[i * lanes + var]
+//
+// The same principle applies when using one thread to simulate multiple context.
+//
 class VecAllocAccess : public IRMutator {
  public:
   VecAllocAccess(const Variable* buf, Var var, int var_lanes)