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Commit 2738eddf by Liangfu Chen Committed by Thierry Moreau
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[VTA][TSIM] Enable TSIM CI Testing (#4407) 

* Update task_python_vta.sh

* install sbt=1.1.1 with apt-get

* update verilator_opt

* install verilator with major version 4.0

* disable multi-threading for now

* bug fix for correcting uop fetch address in LoadUop module

* bug fix for correcting uop fetch address in LoadUop module

* adjustment to read from dram_offset

* enable USE_THREADS with verilator 4.x

* DEBUG: try avoid core dump with verilator 4.x

* bug fix in LoadUop module

* log mega cycles in tsim

* download cat.png to avoid fetching in each run

* bug fix in LoadUop module

* solve dram_even/sram_even issue

* bug fix

* introduce scalalint in ci

* speedup tsim in ci

* bug fix

* lint scala code before building

* disable multi-threading

* split fsim/tsim script

* update Jenkins settings

* duplicate task_python_vta_fsim.sh as task_python_vta.sh for now

Co-authored-by: Thierry Moreau <tmoreau@octoml.ai>
parent 2f8a01f7
Showing with 45 additions and 63 deletions
Makefile
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
ROOTDIR = $(CURDIR) ROOTDIR = $(CURDIR)
.PHONY: clean all test doc pylint cpplint lint\ .PHONY: clean all test doc pylint cpplint scalalint lint\
cython cython2 cython3 web runtime vta cython cython2 cython3 web runtime vta
ifndef DMLC_CORE_PATH ifndef DMLC_CORE_PATH
...@@ -80,7 +80,10 @@ pylint: ...@@ -80,7 +80,10 @@ pylint:
jnilint: jnilint:
python3 3rdparty/dmlc-core/scripts/lint.py tvm4j-jni cpp jvm/native/src python3 3rdparty/dmlc-core/scripts/lint.py tvm4j-jni cpp jvm/native/src
lint: cpplint pylint jnilint scalalint:
make -C vta/hardware/chisel lint
lint: cpplint pylint jnilint scalalint
doc: doc:
doxygen docs/Doxyfile doxygen docs/Doxyfile
......
tests/scripts/task_python_vta.sh
...@@ -29,6 +29,9 @@ rm -rf ~/.tvm ...@@ -29,6 +29,9 @@ rm -rf ~/.tvm
# Rebuild cython # Rebuild cython
make cython3 make cython3
# Reset default fsim simulation
cp vta/config/fsim_sample.json vta/config/vta_config.json
# Run unit tests in functional/fast simulator # Run unit tests in functional/fast simulator
echo "Running unittest in fsim..." echo "Running unittest in fsim..."
python3 -m pytest -v vta/tests/python/unittest python3 -m pytest -v vta/tests/python/unittest
...@@ -36,20 +39,3 @@ python3 -m pytest -v vta/tests/python/unittest ...@@ -36,20 +39,3 @@ python3 -m pytest -v vta/tests/python/unittest
# Run unit tests in functional/fast simulator # Run unit tests in functional/fast simulator
echo "Running integration test in fsim..." echo "Running integration test in fsim..."
python3 -m pytest -v vta/tests/python/integration python3 -m pytest -v vta/tests/python/integration
# # Build VTA chisel design and verilator simulator
# (make -C vta/hardware/chisel/)
# # Set default VTA config to use TSIM cycle accurate sim
# cp vta/config/tsim_sample.json vta/config/vta_config.json
# # Run unit tests in cycle accurate simulator
# echo "Running unittest in tsim..."
# python3 -m pytest -v vta/tests/python/unittest
# # Run unit tests in cycle accurate simulator
# echo "Running integration test in tsim..."
# python3 -m pytest -v vta/tests/python/integration
# # Reset default fsim simulation
# cp vta/config/fsim_sample.json vta/config/vta_config.json
tests/scripts/task_python_vta_fsim.sh
...@@ -29,6 +29,9 @@ rm -rf ~/.tvm ...@@ -29,6 +29,9 @@ rm -rf ~/.tvm
# Rebuild cython # Rebuild cython
make cython3 make cython3
# Reset default fsim simulation
cp vta/config/fsim_sample.json vta/config/vta_config.json
# Run unit tests in functional/fast simulator # Run unit tests in functional/fast simulator
echo "Running unittest in fsim..." echo "Running unittest in fsim..."
python3 -m pytest -v vta/tests/python/unittest python3 -m pytest -v vta/tests/python/unittest
...@@ -36,20 +39,3 @@ python3 -m pytest -v vta/tests/python/unittest ...@@ -36,20 +39,3 @@ python3 -m pytest -v vta/tests/python/unittest
# Run unit tests in functional/fast simulator # Run unit tests in functional/fast simulator
echo "Running integration test in fsim..." echo "Running integration test in fsim..."
python3 -m pytest -v vta/tests/python/integration python3 -m pytest -v vta/tests/python/integration
# # Build VTA chisel design and verilator simulator
# (make -C vta/hardware/chisel/)
# # Set default VTA config to use TSIM cycle accurate sim
# cp vta/config/tsim_sample.json vta/config/vta_config.json
# # Run unit tests in cycle accurate simulator
# echo "Running unittest in tsim..."
# python3 -m pytest -v vta/tests/python/unittest
# # Run unit tests in cycle accurate simulator
# echo "Running integration test in tsim..."
# python3 -m pytest -v vta/tests/python/integration
# # Reset default fsim simulation
# cp vta/config/fsim_sample.json vta/config/vta_config.json
tests/scripts/task_python_vta_tsim.sh
...@@ -29,27 +29,25 @@ rm -rf ~/.tvm ...@@ -29,27 +29,25 @@ rm -rf ~/.tvm
# Rebuild cython # Rebuild cython
make cython3 make cython3
# Run unit tests in functional/fast simulator # Set default VTA config to use TSIM cycle accurate sim
echo "Running unittest in fsim..." cp vta/config/tsim_sample.json vta/config/vta_config.json
python3 -m pytest -v vta/tests/python/unittest
# Run unit tests in functional/fast simulator
echo "Running integration test in fsim..."
python3 -m pytest -v vta/tests/python/integration
# # Build VTA chisel design and verilator simulator # Check style of scala code
# (make -C vta/hardware/chisel/) echo "Check style of scala code..."
make -C vta/hardware/chisel lint
# # Set default VTA config to use TSIM cycle accurate sim # Build VTA chisel design and verilator simulator
# cp vta/config/tsim_sample.json vta/config/vta_config.json echo "Building VTA chisel design..."
make -C vta/hardware/chisel cleanall
make -C vta/hardware/chisel USE_THREADS=0 lib
# # Run unit tests in cycle accurate simulator # Run unit tests in cycle accurate simulator
# echo "Running unittest in tsim..." echo "Running unittest in tsim..."
# python3 -m pytest -v vta/tests/python/unittest python3 -m pytest -v vta/tests/python/unittest
# # Run unit tests in cycle accurate simulator # Run unit tests in cycle accurate simulator
# echo "Running integration test in tsim..." echo "Running integration test in tsim..."
# python3 -m pytest -v vta/tests/python/integration python3 -m pytest -v vta/tests/python/integration
# # Reset default fsim simulation # Reset default fsim simulation
# cp vta/config/fsim_sample.json vta/config/vta_config.json cp vta/config/fsim_sample.json vta/config/vta_config.json
vta/hardware/chisel/Makefile
...@@ -94,7 +94,7 @@ else ...@@ -94,7 +94,7 @@ else
endif endif
ifneq ($(USE_THREADS), 0) ifneq ($(USE_THREADS), 0)
verilator_opt += -threads $(USE_THREADS) verilator_opt += --threads $(USE_THREADS)
cxx_flags += -DVL_THREADED cxx_flags += -DVL_THREADED
cxx_objs += $(verilator_build_dir)/verilated_threads.o cxx_objs += $(verilator_build_dir)/verilated_threads.o
endif endif
......
vta/hardware/chisel/src/main/scala/core/LoadUop.scala
...@@ -81,7 +81,8 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { ...@@ -81,7 +81,8 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
val xmax = (1 << mp.lenBits).U val xmax = (1 << mp.lenBits).U
val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U
val offsetIsEven = (dec.sram_offset % 2.U) === 0.U val dram_even = (dec.dram_offset % 2.U) === 0.U
val sram_even = (dec.sram_offset % 2.U) === 0.U
val sizeIsEven = (dec.xsize % 2.U) === 0.U val sizeIsEven = (dec.xsize % 2.U) === 0.U
val sIdle :: sReadCmd :: sReadData :: Nil = Enum(3) val sIdle :: sReadCmd :: sReadData :: Nil = Enum(3)
...@@ -129,11 +130,10 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { ...@@ -129,11 +130,10 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
// read-from-dram // read-from-dram
val maskOffset = VecInit(Seq.fill(M_DRAM_OFFSET_BITS)(true.B)).asUInt val maskOffset = VecInit(Seq.fill(M_DRAM_OFFSET_BITS)(true.B)).asUInt
when(state === sIdle) { when(state === sIdle) {
when(offsetIsEven) { when(dram_even) {
raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes))) raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))
}.otherwise { }.otherwise {
raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil( raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) - uopBytes.U
uopBytes)))) - uopBytes.U
} }
}.elsewhen(state === sReadData && xcnt === xlen && xrem =/= 0.U) { }.elsewhen(state === sReadData && xcnt === xlen && xrem =/= 0.U) {
raddr := raddr + xmax_bytes raddr := raddr + xmax_bytes
...@@ -162,7 +162,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { ...@@ -162,7 +162,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
val mem = SyncReadMem(uopDepth, chiselTypeOf(wdata)) val mem = SyncReadMem(uopDepth, chiselTypeOf(wdata))
val wmask = Reg(Vec(numUop, Bool())) val wmask = Reg(Vec(numUop, Bool()))
when(offsetIsEven) { when(sram_even) {
when(sizeIsEven) { when(sizeIsEven) {
wmask := "b_11".U.asTypeOf(wmask) wmask := "b_11".U.asTypeOf(wmask)
}.elsewhen(io.vme_rd.cmd.fire()) { }.elsewhen(io.vme_rd.cmd.fire()) {
...@@ -192,6 +192,12 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module { ...@@ -192,6 +192,12 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
} }
wdata := io.vme_rd.data.bits.asTypeOf(wdata) wdata := io.vme_rd.data.bits.asTypeOf(wdata)
when(dram_even === false.B && sram_even) {
wdata(0) := io.vme_rd.data.bits.asTypeOf(wdata)(1)
}.elsewhen(sram_even === false.B && dram_even) {
wdata(1) := io.vme_rd.data.bits.asTypeOf(wdata)(0)
}
when(io.vme_rd.data.fire()) { when(io.vme_rd.data.fire()) {
mem.write(waddr, wdata, wmask) mem.write(waddr, wdata, wmask)
} }
......
vta/hardware/dpi/tsim_device.cc
...@@ -141,6 +141,8 @@ int VTADPISim() { ...@@ -141,6 +141,8 @@ int VTADPISim() {
tfp->dump(static_cast<vluint64_t>(trace_count * 2 + 1)); tfp->dump(static_cast<vluint64_t>(trace_count * 2 + 1));
#endif #endif
trace_count++; trace_count++;
if ((trace_count % 1000000) == 1)
fprintf(stderr, "[traced %dM cycles]\n", trace_count / 1000000);
while (top->sim_wait) { while (top->sim_wait) {
top->clock = 0; top->clock = 0;
std::this_thread::sleep_for(std::chrono::milliseconds(100)); std::this_thread::sleep_for(std::chrono::milliseconds(100));
......
vta/tutorials/frontend/deploy_vision_on_vta.py
...@@ -225,10 +225,11 @@ synset = eval(open(categ_fn).read()) ...@@ -225,10 +225,11 @@ synset = eval(open(categ_fn).read())
# Download test image # Download test image
image_url = 'https://homes.cs.washington.edu/~moreau/media/vta/cat.jpg' image_url = 'https://homes.cs.washington.edu/~moreau/media/vta/cat.jpg'
response = requests.get(image_url) image_fn = 'cat.png'
download.download(image_url, image_fn)
# Prepare test image for inference # Prepare test image for inference
image = Image.open(BytesIO(response.content)).resize((224, 224)) image = Image.open(image_fn).resize((224, 224))
plt.imshow(image) plt.imshow(image)
plt.show() plt.show()
image = np.array(image) - np.array([123., 117., 104.]) image = np.array(image) - np.array([123., 117., 104.])
......
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