Commit 1022ad7c by Siju Committed by Tianqi Chen

[DOC]Errors corrected (#1767)

parent 48cf48b2
......@@ -217,7 +217,7 @@ Stmt NarrowChannelAccess(Stmt stmt);
* \param auto_max_step The maximum step before stop attach automatic unroll
* \param auto_max_depth The maximum depth before stop attach automatic unroll
* \param auto_max_extent The maximum extent of the loop we can unroll,
* this is an legacy option that donot take the loop total steps into account.
* this is an legacy option that do not take the loop total steps into account.
* \param explicit_unroll Whether explicitly unroll the loop, or leave unroll annotation to codegen.
* \return Transformed stmt.
*/
......
......@@ -67,7 +67,7 @@ class TVMType(ctypes.Structure):
bits = 64
head = ""
else:
raise ValueError("Donot know how to handle type %s" % type_str)
raise ValueError("Do not know how to handle type %s" % type_str)
bits = int(head) if head else bits
self.bits = bits
......
......@@ -362,7 +362,7 @@ class Stage(NodeBase):
"""
if nparts is not None:
if factor is not None:
raise ValueError("Donot need to provide both outer and nparts")
raise ValueError("Do not need to provide both outer and nparts")
outer, inner = _api_internal._StageSplitByNParts(self, parent, nparts)
else:
if factor is None:
......
......@@ -72,7 +72,7 @@ def decl_tensor_intrin(op,
binds_list = []
for t in inputs:
if not isinstance(t.op, _tensor.PlaceholderOp):
raise ValueError("Donot yet support composition op")
raise ValueError("Do not yet support composition op")
cfg = current_build_config()
for t in tensors:
......
......@@ -207,7 +207,7 @@ std::string CodeGenC::GetStructRef(
} else if (t.is_int()) {
os << "v_int64";
} else {
LOG(FATAL) << "donot know how to handle type" << t;
LOG(FATAL) << "Do not know how to handle type" << t;
}
os << ")";
return os.str();
......
......@@ -213,11 +213,11 @@ VerilogValue CodeGenVerilog::VisitExpr_(const UIntImm *op) {
return IntConst(op, this);
}
VerilogValue CodeGenVerilog::VisitExpr_(const FloatImm *op) {
LOG(FATAL) << "Donot support float constant in Verilog";
LOG(FATAL) << "Do not support float constant in Verilog";
return VerilogValue();
}
VerilogValue CodeGenVerilog::VisitExpr_(const StringImm *op) {
LOG(FATAL) << "Donot support string constant in Verilog";
LOG(FATAL) << "Do not support string constant in Verilog";
return VerilogValue();
}
......
......@@ -52,10 +52,10 @@ size_t InferTensorizeRegion(
const IterVarAttr& attr = (*iit).second;
if (!found_point) {
CHECK(!attr->bind_thread.defined())
<< "Donot allow thread in tensorize scope";
<< "Do not allow thread in tensorize scope";
}
if (attr->iter_type == kTensorized) {
CHECK(!found_point) << "Donot allow two tensorized point";
CHECK(!found_point) << "Do not allow two tensorized point";
found_point = true;
loc_scope = i - 1;
}
......
......@@ -168,7 +168,7 @@ inline PackedFunc PackFuncNonBufferArg_(
switch (codes[i]) {
case INT64_TO_INT64:
case FLOAT64_TO_FLOAT64: {
LOG(FATAL) << "Donot support 64bit argument to device function"; break;
LOG(FATAL) << "Do not support 64bit argument to device function"; break;
}
case INT64_TO_INT32: {
holder[i].v_int32 = static_cast<int32_t>(args.values[base + i].v_int64);
......
......@@ -250,9 +250,9 @@ class RPCSession::EventHandler : public dmlc::Stream {
this->Write(arr->dtype);
this->WriteArray(arr->shape, arr->ndim);
CHECK(arr->strides == nullptr)
<< "Donot support strided remote array";
<< "Do not support strided remote array";
CHECK_EQ(arr->byte_offset, 0)
<< "Donot support send byte offset";
<< "Do not support send byte offset";
break;
}
case kNull: break;
......
......@@ -556,7 +556,7 @@ def inject_dma_intrin(stmt_in):
return irb.get()
else:
raise RuntimeError("Donot support copy %s->%s" % (src.scope, dst.scope))
raise RuntimeError("Do not support copy %s->%s" % (src.scope, dst.scope))
return tvm.ir_pass.InjectCopyIntrin(stmt_in, "dma_copy", _inject_copy)
......
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