python/tvm/module.py · 623748a698e43171d80cef46cce3a7eac1708b51 · wenyuanbo / tic · GitLab

Blame History Permalink

[PERF/TIMER] Add builtin timing logic (#168) · 5912ed03
```
* [PERF/TIMER] Add buildin timing logic

* fix lint
```
Tianqi Chen committed Jun 03, 2017
5912ed03

module.py 4.16 KB