chisel_accel.py
6.6 KB
-
[VTA][Chisel] TSIM VTA Source Refactor (#4163) · 13b28566
* app init push * fix on readme * change name, add bit serial explanantion * rm serialLoadMM, change doc * syntax change for readme * add parallel test functionality * fix readme * add python doc * syntax * init commit * fix empty line * fix typo
Benjamin Tu committed