README.md 441 Bytes
Newer Older
Tianqi Chen committed
1 2
# Verilog Code Guidline

3 4
The verilog backend is still at early alpha and not yet ready to use.

Tianqi Chen committed
5 6 7 8 9 10 11 12 13 14 15 16 17
- Use ```my_port_name``` for variable naming.
- Always use suffix to indicate certain usage.

## Common Suffix

- ```clk```: clock
- ```rst```: reset
- ```in```: input port
- ```out```: output port
- ```en```: enable signal
- ```addr```: address port
- ```valid```: valid signal in FIFO handshake.
- ```ready```: ready signal in FIFO handshake.