Commit 29ddcdc3 by songxinkai

ram api //ramulator:ram and //ramulator:testram

parent a9f31f6a
#!/bin/bash
bazel build --copt="-DRAMULATOR" //ramulator:main
bazel build --copt="-DRAMULATOR" //ramulator:testram
cc_binary(
name="testram",
srcs=[
"testram.cpp",
],
deps=[
"ram",
],
copts=[
"-O3",
"-std=c++11",
"-g",
"-Wall",
],
)
cc_binary(
name="main",
srcs=[
"Main.cpp",
......@@ -37,6 +53,46 @@ cc_binary(
)
cc_library(
name="ram",
srcs=[
"ram.cpp",
],
hdrs=[
"ram.h",
],
deps=[
":Config",
":Controller",
":SpeedyController",
":Memory",
":DRAM",
":Statistics",
":Gem5Wrapper",
":DDR3",
":DDR4",
":DSARP",
":GDDR5",
":LPDDR3",
":LPDDR4",
":WideIO",
":WideIO2",
":HBM",
":SALP",
":ALDRAM",
":TLDRAM",
":STTMRAM",
":PCM",
],
copts=[
"-O3",
"-std=c++11",
"-g",
"-Wall",
],
visibility = ["//visibility:public"],
)
cc_library(
name="Processor",
srcs=["Processor.cpp",
],
......
#include "ram.h"
#include <assert.h>
#include <functional>
template<typename T>
Ram<T>::Ram(const std::string& config_file){
clk_ = 0;
processor_frequency_ratio_ = 1;
Config configs(config_file);
const std::string& standard = configs["standard"];
assert(standard != "" || "DRAM standard should be specified.");
//not usefull
configs.add("trace_type", "CPU");
//mapping strategy
configs.add("mapping", "defaultmapping");
//not usefull
configs.set_core_num(1);
T* ddr = new T(configs["org"], configs["speed"]);
InitMemory(configs, ddr); // not implement: SALP-MASA, WideIO2, DSARP, TLDRAM
//run simulation according to the memory standard.
/*
if (standard == "DDR3") {
DDR3* ddr3 = new DDR3(configs["org"], configs["speed"]);
InitMemory(configs, ddr3);
} else if (standard == "DDR4") {
DDR4* ddr4 = new DDR4(configs["org"], configs["speed"]);
InitMemory(configs, ddr4);
} else if (standard == "SALP-MASA") {
SALP* salp8 = new SALP(configs["org"], configs["speed"], "SALP-MASA", configs.get_subarrays());
InitMemory(configs, salp8);
} else if (standard == "LPDDR3") {
LPDDR3* lpddr3 = new LPDDR3(configs["org"], configs["speed"]);
InitMemory(configs, lpddr3);
} else if (standard == "LPDDR4") {
// total cap: 2GB, 1/2 of others
LPDDR4* lpddr4 = new LPDDR4(configs["org"], configs["speed"]);
InitMemory(configs, lpddr4);
} else if (standard == "GDDR5") {
GDDR5* gddr5 = new GDDR5(configs["org"], configs["speed"]);
InitMemory(configs, gddr5);
} else if (standard == "HBM") {
HBM* hbm = new HBM(configs["org"], configs["speed"]);
InitMemory(configs, hbm);
} else if (standard == "WideIO") {
// total cap: 1GB, 1/4 of others
WideIO* wio = new WideIO(configs["org"], configs["speed"]);
InitMemory(configs, wio);
} else if (standard == "WideIO2") {
// total cap: 2GB, 1/2 of others
WideIO2* wio2 = new WideIO2(configs["org"], configs["speed"], configs.get_channels());
wio2->channel_width *= 2;
InitMemory(configs, wio2);
} else if (standard == "STTMRAM") {
STTMRAM* sttmram = new STTMRAM(configs["org"], configs["speed"]);
InitMemory(configs, sttmram);
} else if (standard == "PCM") {
PCM* pcm = new PCM(configs["org"], configs["speed"]);
InitMemory(configs, pcm);
}
// Various refresh mechanisms
else if (standard == "DSARP") {
DSARP* dsddr3_dsarp = new DSARP(configs["org"], configs["speed"], DSARP::Type::DSARP, configs.get_subarrays());
InitMemory(configs, dsddr3_dsarp);
} else if (standard == "ALDRAM") {
ALDRAM* aldram = new ALDRAM(configs["org"], configs["speed"]);
InitMemory(configs, aldram);
} else if (standard == "TLDRAM") {
TLDRAM* tldram = new TLDRAM(configs["org"], configs["speed"], configs.get_subarrays());
InitMemory(configs, tldram);
}
*/
}
template<typename T>
Ram<T>::~Ram(){
}
template<typename T>
void Ram<T>::InitMemory(const Config& configs, T* spec){
int C = configs.get_channels(), R = configs.get_ranks();
// Check and Set channel, rank number
spec->set_channel_number(C);
spec->set_rank_number(R);
std::vector<Controller<T>*> ctrls;
for (int c = 0 ; c < C ; c++) {
DRAM<T>* channel = new DRAM<T>(spec, T::Level::Channel);
channel->id = c;
channel->regStats("");//not usefull
Controller<T>* ctrl = new Controller<T>(configs, channel);
ctrls.push_back(ctrl);
}
memory_ = std::make_shared<Memory<T, Controller> >(configs, ctrls);
}
template<typename T>
long Ram<T>::AccessMemory(const long req_addr, const Request::Type req_type){
long tmp_clk = 0;
bool data_return = false;
long req_addr_param = req_addr;
auto req_type_param = req_type;
auto callback = std::function<void(Request&)>([&data_return](Request& rq){data_return = true;});
Request req(req_addr_param, req_type_param, callback, 0);
memory_->send(req);
while (!data_return){
memory_->tick();
clk_ ++;
tmp_clk ++;
}
return ConvertCyclesRam2Processor(tmp_clk);
}
template<typename T>
long Ram<T>::AccessMemory(const long send_clk_processor, const long req_addr, const Request::Type req_type){
long send_clk = ConvertCyclesRam2Processor(send_clk_processor);
long tmp_clk = 0;
while (clk_ < send_clk){
memory_->tick();
clk_ ++;
tmp_clk ++;
}
bool data_return = false;
long req_addr_param = req_addr;
auto req_type_param = req_type;
auto callback = std::function<void(Request&)>([&data_return](Request& rq){data_return = true;});
Request req(req_addr_param, req_type_param, callback, 0);
memory_->send(req);
while (!data_return){
memory_->tick();
clk_ ++;
tmp_clk ++;
}
return ConvertCyclesRam2Processor(tmp_clk);
}
template<typename T>
long Ram<T>::ConvertCyclesRam2Processor(const long cycles){
return long(double(cycles) * processor_frequency_ratio_);
}
template<typename T>
long Ram<T>::ConvertCyclesProcessor2Ram(const long cycles){
return long(double(cycles) / processor_frequency_ratio_);
}
template<typename T>
void Ram<T>::SetProcessorFrequencyRatio(const double r){
void SetProcessorFrequencyRatio(const double r);
this->processor_frequency_ratio_ = r;
}
template<typename T>
long Ram<T>::GetClockProcessor(){
return this->clk_ * processor_frequency_ratio_;
}
template<typename T>
long Ram<T>::GetClockRam(){
return this->clk_;
}
// yet not implement: SALP-MASA, WideIO2, DSARP, TLDRAM
template class Ram<ramulator::DDR3>;
template class Ram<ramulator::DDR4>;
template class Ram<ramulator::GDDR5>;
template class Ram<ramulator::LPDDR3>;
template class Ram<ramulator::LPDDR4>;
//template class Ram<ramulator::DSARP>;
template class Ram<ramulator::WideIO>;
//template class Ram<ramulator::WideIO2>;
template class Ram<ramulator::HBM>;
//template class Ram<ramulator::SALP>;
template class Ram<ramulator::ALDRAM>;
//template class Ram<ramulator::TLDRAM>;
template class Ram<ramulator::STTMRAM>;
template class Ram<ramulator::PCM>;
#include "Config.h"
#include "Controller.h"
#include "SpeedyController.h"
#include "Memory.h"
#include "DRAM.h"
#include "Request.h"
/* Standards */
#include "Gem5Wrapper.h"
#include "DDR3.h"
#include "DDR4.h"
#include "DSARP.h"
#include "GDDR5.h"
#include "LPDDR3.h"
#include "LPDDR4.h"
#include "WideIO.h"
#include "WideIO2.h"
#include "HBM.h"
#include "SALP.h"
#include "ALDRAM.h"
#include "TLDRAM.h"
#include "STTMRAM.h"
#include "PCM.h"
#include <string>
#include <memory> // std::shared_ptr
using namespace ramulator;
template<typename T>
class Ram{
public:
Ram(const std::string& config_file);
~Ram();
long AccessMemory(const long req_addr, const Request::Type req_type);
long AccessMemory(const long send_clk_processor, const long req_addr, const Request::Type req_type);
long ConvertCyclesRam2Processor(const long cycles);
long ConvertCyclesProcessor2Ram(const long cycles);
void SetProcessorFrequencyRatio(const double r);
long GetClockProcessor();
long GetClockRam();
protected:
void InitMemory(const Config& configs, T* spec);
double processor_frequency_ratio_;
long clk_;
std::shared_ptr<Memory<T, Controller> > memory_;
};
#include "ram.h"
#include <iostream>
#include <string>
using namespace ramulator;
int main(int argc, const char *argv[]){
if (argc < 3) {
printf("Usage: %s <configs-file> <memory access interval>\n"
"Example: %s ramulator-configs.cfg 16\n", argv[0], argv[0]);
return 0;
}
Ram<ramulator::DDR3> ram(argv[1]);
ram.SetProcessorFrequencyRatio(4.0);
int addr_interval = std::stoi(argv[2]);
long last_access_time = -1;
int same_access_time_count = 0;
for (int i = 0; i < 1000; ++i){
long access_time = ram.AccessMemory(long(20734016 + i * addr_interval), ramulator::Request::Type::READ);
if (last_access_time != access_time && last_access_time > 0){
cout << "access id: " << i << ", cycles: " << last_access_time << " (" << same_access_time_count << ")" << endl;
same_access_time_count = 1;
}else{
same_access_time_count ++;
}
last_access_time = access_time;
}
std::cout << "total cycles: " << ram.GetClockProcessor() << std::endl;
return 0;
}
#!/bin/bash
./bazel-bin/ramulator/testram ./configs/DDR3-config.cfg $1
./bazel-bin/ramulator/main ./configs/DDR3-config.cfg $1
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