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lvzhengyang
yosys-tests
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9210153a665eebdc5daf38dae1483d38be52aa8b
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yosys-tests
architecture
xilinx_ug901_synthesis_examples
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improved values in tests
· 337efd01
Miodrag Milanovic
committed
Jun 26, 2020
337efd01
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asym_ram_sdp_read_wider.v
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asym_ram_sdp_write_wider.v
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asym_ram_tdp_read_first.v
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asym_ram_tdp_write_first.v
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black_box_1.v
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bytewrite_ram_1b.v
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bytewrite_tdp_ram_nc.v
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bytewrite_tdp_ram_readfirst2.v
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bytewrite_tdp_ram_rf.v
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bytewrite_tdp_ram_wf.v
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cmacc.v
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cmult.v
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dynamic_shift_registers_1.v
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dynpreaddmultadd.v
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fsm_1.v
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latches.v
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macc.v
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mult_unsigned.v
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presubmult.v
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ram_simple_dual_one_clock.v
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ram_simple_dual_two_clocks.v
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rams_dist.v
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rams_init_file.data
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rams_init_file.v
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rams_pipeline.v
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rams_sp_nc.v
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rams_sp_rf.v
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rams_sp_rf_rst.v
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rams_sp_rom.v
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rams_sp_rom_1.v
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rams_sp_wf.v
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rams_tdp_rf_rf.v
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registers_1.v
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sfir_shifter.v
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shift_registers_0.v
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shift_registers_1.v
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squarediffmacc.v
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squarediffmult.v
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top_mux.v
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tristates_1.v
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tristates_2.v
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xilinx_ug901_asym_ram_sdp_read_wider.ys
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xilinx_ug901_asym_ram_sdp_write_wider.ys
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xilinx_ug901_asym_ram_tdp_read_first.ys
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xilinx_ug901_asym_ram_tdp_write_first.ys
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xilinx_ug901_black_box_1.ys
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xilinx_ug901_bytewrite_ram_1b.ys
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xilinx_ug901_bytewrite_tdp_ram_nc.ys
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xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys
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xilinx_ug901_bytewrite_tdp_ram_rf.ys
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xilinx_ug901_bytewrite_tdp_ram_wf.ys
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xilinx_ug901_cmacc.ys
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xilinx_ug901_cmult.ys
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xilinx_ug901_dynamic_shift_registers_1.ys
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xilinx_ug901_dynpreaddmultadd.ys
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xilinx_ug901_fsm_1.ys
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xilinx_ug901_latches.ys
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xilinx_ug901_macc.ys
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xilinx_ug901_mult_unsigned.ys
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xilinx_ug901_presubmult.ys
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xilinx_ug901_ram_simple_dual_one_clock.ys
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xilinx_ug901_ram_simple_dual_two_clocks.ys
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xilinx_ug901_rams_dist.ys
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xilinx_ug901_rams_init_file.ys
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xilinx_ug901_rams_pipeline.ys
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xilinx_ug901_rams_sp_nc.ys
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xilinx_ug901_rams_sp_rf.ys
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xilinx_ug901_rams_sp_rf_rst.ys
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xilinx_ug901_rams_sp_rom.ys
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xilinx_ug901_rams_sp_rom_1.ys
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xilinx_ug901_rams_sp_wf.ys
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xilinx_ug901_rams_tdp_rf_rf.ys
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xilinx_ug901_registers_1.ys
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xilinx_ug901_sfir_shifter.ys
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xilinx_ug901_shift_registers_0.ys
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xilinx_ug901_shift_registers_1.ys
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xilinx_ug901_squarediffmacc.ys
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xilinx_ug901_squarediffmult.ys
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xilinx_ug901_top_mux.ys
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xilinx_ug901_tristates_1.ys
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xilinx_ug901_tristates_2.ys
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xilinx_ug901_xilinx_ultraram_single_port_no_change.ys
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xilinx_ug901_xilinx_ultraram_single_port_read_first.ys
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xilinx_ug901_xilinx_ultraram_single_port_write_first.ys
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xilinx_ultraram_single_port_no_change.v
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xilinx_ultraram_single_port_read_first.v
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xilinx_ultraram_single_port_write_first.v
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