simple & misc
===========
Note that some of commands you can not test with checking with testbench
so those place in misc.
1. passes/cmds/add.cc
Note that here you need to load some existing verilog and add additional
wires, inputs or outputs
2. passes/cmds/blackbox.cc
you could create design with sub module, execute blackbox and check if
sub module is replaced with blackbox module.
3. passes/cmds/bugpoint.cc
4. passes/cmds/chformal.cc
5. passes/cmds/chtype.cc
6. passes/cmds/connect.cc
Maybe can be covered together with add command
7.passes/cmds/connwrappers.cc
8. passes/cmds/design.cc
missing covering -import option
9.passes/cmds/plugin.cc
10. passes/cmds/rename.cc
rename parts of existing design
11. /passes/cmds/select.cc
Lot of options is not used , so room to improve
12.passes/cmds/setattr.cc
note there are 3 commands to cover here
13. passes/cmds/setundef.cc
setting with one, anyseq, anyconst ...
14. passes/sat/assertpmux.cc
15. passes/sat/async2sync.cc
16. passes/sat/eval.cc
17. passes/sat/freduce.cc
18. passes/sat/miter.cc
run with -assert option
19. passes/sat/sat.cc
many options are not tested
20. passes/sat/sim.cc
21. passes/techmap/flowmap.cc
