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lvzhengyang
yosys-tests
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19f1c9acd16bad8fe588d50c292d9273ad57778c
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yosys-tests
verific
vhdl
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Add simple verific VHDL test case
· 42963512
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf
committed
Aug 22, 2018
42963512
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.gitignore
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Makefile
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bar.vhd
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foo.vhd
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tb.sv
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test.ys
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top.vhd
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