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lvzhengyang
yosys-tests
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095a01032ce7f7110bea7037bd76bb17e9099382
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yosys-tests
architecture
xilinx_ug901_synthesis_examples
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xilinx UG901 test. Divide to separate tests for each case.
· 3d49abc1
...
Divided to understand regress on #171 build.
SergeyDegtyar
committed
Sep 30, 2019
3d49abc1
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..
asym_ram_sdp_read_wider.v
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asym_ram_sdp_write_wider.v
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asym_ram_tdp_read_first.v
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asym_ram_tdp_write_first.v
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black_box_1.v
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bytewrite_ram_1b.v
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bytewrite_tdp_ram_nc.v
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bytewrite_tdp_ram_readfirst2.v
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bytewrite_tdp_ram_rf.v
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bytewrite_tdp_ram_wf.v
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cmacc.v
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cmult.v
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dynamic_shift_registers_1.v
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dynpreaddmultadd.v
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fsm_1.v
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latches.v
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macc.v
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mult_unsigned.v
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presubmult.v
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ram_simple_dual_one_clock.v
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ram_simple_dual_two_clocks.v
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rams_dist.v
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rams_init_file.data
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rams_init_file.v
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rams_pipeline.v
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rams_sp_nc.v
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rams_sp_rf.v
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rams_sp_rf_rst.v
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rams_sp_rom.v
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rams_sp_rom_1.v
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rams_sp_wf.v
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rams_tdp_rf_rf.v
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registers_1.v
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sfir_shifter.v
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shift_registers_0.v
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shift_registers_1.v
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squarediffmacc.v
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squarediffmult.v
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top_mux.v
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tristates_1.v
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tristates_2.v
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xilinx_ultraram_single_port_no_change.v
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xilinx_ultraram_single_port_read_first.v
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xilinx_ultraram_single_port_write_first.v
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