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Created with Raphaël 2.2.020Sep19181615121110965330Aug282316151310987653129Jul26242322181716171615141311109862130Jun292827262524211713629May282421185432130Apr272625222120121110854329Mar282725242221201918161514131298654128Feb272120116529Jan2725242315219Dec161221Sep628Aug225May6Mar43126FebRevert regression fixFix regress on #160 build; Clean up issue_01161.ys.Update synth_xilinx_dsp testsAdd muladd testsUpdate assert_area.pyRe-enable testing dffe on ice40 DSPsNew tests for closed issues and open bugs.Merge pull request #66 from SergeyDegtyar/SergeyDegtyar/tests_for_new_featuresFix failed testsTests to actually generate addersIgnore log filesMerge pull request #65 from SergeyDegtyar/SergeyDegtyar/tests_for_new_featuresMerge pull request #64 from SergeyDegtyar/SergeyDegtyar/xilinx_ug901_synthesis_examples_testsMerge pull request #63 from SergeyDegtyar/fix_regress_for_build_150Add tests for closed issuesAdd tests for new commands in passes/pmgenMove tests for Xilinx UG901 examples from tests/xilinx_ug901 to yosys-testsAdd tests for synth_efinix commandAdd tests for anlogic_fixcarry commandAdd test for read_aiger -map optionFix regress on build #150Update assert_area.py for muladdFix spaceUpdateAdapt for maccAdd some new testcasesAdd macc testsExtend assert_area.py support for maccUpdate for M registerAdd argument for -matchRemove -tech greenpak4 as that sets -clkpolAdd include dir for ecp5_abc9 tooDeprecate use of shregmap's "-tech xilinx" optionAdd include directory for ecp5Fix tests to represent how it should be usedDo not simulate, check ram generatedmessage check fixOoopsUpdate synth_xilinx_srl to cope with BUFGAdd some FDRE tests