Programming languages used in this repository
-
Verilog
99.44 %
-
Max
0.14 %
-
Python
0.13 %
-
Assembly
0.1 %
-
SystemVerilog
0.09 %
-
Shell
0.04 %
-
Makefile
0.03 %
-
Coq
0.03 %
-
VHDL
0.01 %
-
Smarty
0.0 %
-
C
0.0 %
-
Tcl
0.0 %
Commit statistics for a25094f65d82de8fbf81702c91a28878ed2a6ec5 Feb 26 - Apr 27
- Total: 451 commits
- Average per day: 0 commits
- Authors: 11
Commits per day of month
Commits per weekday
Commits per day hour (UTC)