Programming languages used in this repository
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Verilog
99.44 %
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Max
0.14 %
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Python
0.13 %
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Assembly
0.1 %
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SystemVerilog
0.09 %
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Shell
0.04 %
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Makefile
0.03 %
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Coq
0.03 %
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VHDL
0.01 %
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Smarty
0.0 %
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C
0.0 %
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Tcl
0.0 %
Commit statistics for 2a17ff0db35fbe0e1ce4fe51f2e712b392bbc9c7 Feb 26 - Jul 09
- Total: 212 commits
- Average per day: 0 commits
- Authors: 7
Commits per day of month
Commits per weekday
Commits per day hour (UTC)