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yosys-tests
Commit fae17050 by SergeyDegtyar
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Commit tests for "I Simple" tasks section 

5. clk2fflogic (104 - 144,180-195 are not covered)
9. memory_nordff(75-101 is not covered)
10. memory_unpack(91-108 is not covered)
12. hierarchy (the coverage from 44% increased to 61,3%)
parent 050cc693
Showing with 1893 additions and 0 deletions
simple/Makefile
......@@ -50,4 +50,37 @@ $(eval $(call template,fsm_unreach, fsm))
$(eval $(call template,fsm, fsm))
$(eval $(call template,fsm_opt, fsm))
#Extract full and half adders
$(eval $(call template,full_adder,full_adder half_adder))
#Extract reduce
$(eval $(call template,reduce,reduce reduce_allow_off_chain))
#nlutmap
$(eval $(call template,nlutmap,nlutmap nlutmap_luts nlutmap_assert))
#zinit
$(eval $(call template,zinit,zinit zinit_singleton))
#clk2fflogic (104 - 144,180-195 is not reached)
$(eval $(call template,clk2fflogic,clk2fflogic))
$(eval $(call template,clk2fflogic_latch,clk2fflogic))
$(eval $(call template,clk2fflogic_mem,clk2fflogic_mem))
# ??? one loop isn't reached $(eval $(call template,clk2fflogic_mem2,clk2fflogic_mem))
#muxcover
$(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcover_mux4_nodecode muxcover_mux8 muxcover_mux8_nodecode muxcover_mux16 muxcover_mux16_nodecode muxcover_4_8_16_nodecode))
#aigmap
$(eval $(call template,aigmap,aigmap aigmap_nand))
#memory_memx, memory_nordff(75-101 not covered), memory_unpack(91-108 not covered)
$(eval $(call template,memory,memory_memx memory_nordff memory_unpack))
#uniquify
$(eval $(call template,uniquify,uniquify))
#hierarchy (44% increased to 61,3%)
$(eval $(call template,hierarchy,hierarchy hierarchy_top hierarchy_check hierarchy_simcheck hierarchy_purge_lib hierarchy_libdir hierarchy_keep_positionals hierarchy_keep_portwidths hierarchy_nokeep_asserts hierarchy_auto_top hierarchy_generate))
.PHONY: all clean
simple/aigmap/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
simple/aigmap/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
reg Y;
wire[3:0] S;
wire[15:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
8 : Y = D[8];
9 : Y = D[9];
10 : Y = D[10];
11 : Y = D[11];
12 : Y = D[12];
13 : Y = D[13];
14 : Y = D[14];
15 : Y = D[15];
endcase
end
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
simple/clk2fflogic/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/clk2fflogic/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/clk2fflogic_latch/testbench.v 0 → 100644
module testbench;
reg en;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3;
reg lat,nlat,alat,alatn = 0;
top uut (
.en (en ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 )
);
always @(posedge en) begin
#3;
dinA <= dinA + 1;
end
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( dinA[2] )
lat <= 1'b0;
else if ( dinA[1] )
lat <= 1'b1;
else if ( en )
lat <= dinA[0];
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( !dinA[2] )
nlat <= 1'b0;
else if ( !dinA[1] )
nlat <= 1'b1;
else if (!en)
nlat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( dinA[2] )
alat <= 1'b0;
else if (en)
alat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( !dinA[2] )
alatn <= 1'b0;
else if (!en)
alatn <= dinA[0];
assert_dff lat_test(.clk(en), .test(doutB), .pat(lat));
assert_dff nlat_test(.clk(en), .test(doutB1), .pat(nlat));
assert_dff alat_test(.clk(en), .test(doutB2), .pat(alat));
assert_dff alatn_test(.clk(en), .test(doutB3), .pat(alatn));
endmodule
simple/clk2fflogic_latch/top.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple/clk2fflogic_mem/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
wire [7:0] q_a,q_b;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/clk2fflogic_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
simple/common.v
......@@ -32,3 +32,15 @@ module assert_Z(input clk, input A);
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
simple/full_adder/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
simple/full_adder/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
simple/hierarchy/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/hierarchy/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module adff
( inout d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
parameter S=0;
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
parameter Z=1'bZ;
initial begin
q = Z;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( d, clk, pre, clr, q );
parameter s=2;
parameter l=1;
input [s-1:l] d;
input clk, pre, clr;
output reg [s-1:l] q;
initial begin
q = 2'b11;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 2'b00;
`else
q <= d;
`endif
else if ( !pre )
q <= 2'b11;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
wire a1,b11;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr #(4) u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d ({a,a1} ),
.q ({b1,b11} )
);
defparam u_ndffnsnr.l = 0;
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/memory/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/memory/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple/muxcover/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [255:0] D = 1;
reg [7:0] S = 0;
wire M256;
top uut (
.S (S ),
.D (D ),
.M256 (M256 )
);
always @(posedge clk) begin
//#3;
D <= {D[254:0],D[255]};
S <= S + 1;
end
assert_tri m16_test(.en(clk), .A(1'b1), .B(M256));
endmodule
simple/muxcover/top.v 0 → 100644
module top (
input [7:0] S,
input [255:0] D,
output M256
);
assign M256 = D[S];
endmodule
simple/nlutmap/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
simple/nlutmap/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire p,r,s;
xor (p,x,y);
`ifndef BUG
xor (A,p,cin);
`else
and (A,p,cin);
`endif
and(r,p,cin);
and(s,x,y);
or(cout,r,s);
endmodule
simple/reduce/testbench.v 0 → 100644
module testbench;
reg [7:0] in;
wire pi_and,i_and;
wire pi_or,i_or;
wire pi_xor,i_xor;
wire pi_nand,i_nand;
wire pi_nor,i_nor;
wire pi_xnor,i_xnor;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in),
.o_and(i_and),
.o_or(i_or),
.o_xor(i_xor),
.o_nand(i_nand),
.o_nor(i_nor),
.o_xnor(i_xnor)
);
assign pi_and = &in;
assign pi_or = |in;
assign pi_xor = ^in;
assign pi_nand = ~&in;
assign pi_nor = ~|in;
assign pi_xnor = ~^in;
assert_comb and_test(.A(pi_and), .B(i_and));
endmodule
simple/reduce/top.v 0 → 100644
module top
(
input [7:0] x,
output o_and,
output o_or,
output o_xor,
output o_nand,
output o_nor,
output o_xnor
);
`ifndef BUG
assign o_and = &x;
assign o_or = |x;
assign o_xor = ^x;
assign o_nand = ~&x;
assign o_nor = ~|x;
assign o_xnor = ~^x;
`else
assign o_and = ~&x;
assign o_or = &x;
assign o_xor = ~^x;
assign o_nand = &x;
assign o_nor = ^x;
assign o_xnor = ~&x;
`endif
endmodule
simple/scripts/aigmap.ys 0 → 100644
read_verilog ../top.v
aigmap
proc
aigmap
synth -top top
aigmap
write_verilog synth.v
simple/scripts/aigmap_nand.ys 0 → 100644
read_verilog ../top.v
aigmap -nand
proc
aigmap -nand
synth -top top
aigmap -nand
write_verilog synth.v
simple/scripts/clk2fflogic.ys 0 → 100644
read_verilog ../top.v
proc
clk2fflogic
synth -top top
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/clk2fflogic_mem.ys 0 → 100644
read_verilog ../top.v
memory_collect
proc
clk2fflogic
synth -top top
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/full_adder.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_fa -fa -v
synth -top top
write_verilog synth.v
simple/scripts/half_adder.ys 0 → 100644
read_verilog ../top.v
proc
synth -top top
extract_fa -ha -v
synth -top top
write_verilog synth.v
simple/scripts/hierarchy.ys 0 → 100644
read_verilog ../top.v
hierarchy
proc
hierarchy
opt
hierarchy
synth -top top
hierarchy
write_verilog synth.v
simple/scripts/hierarchy_auto_top.ys 0 → 100644
read_verilog ../top.v
hierarchy -auto-top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_check.ys 0 → 100644
read_verilog ../top.v
hierarchy -check -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_generate.ys 0 → 100644
read_verilog ../top.v
hierarchy -generate dff adff adffn i@1:i o@2:o io@3:io
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_keep_portwidths.ys 0 → 100644
read_verilog ../top.v
hierarchy -keep_portwidths -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_keep_positionals.ys 0 → 100644
read_verilog ../top.v
hierarchy -keep_positionals -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_libdir.ys 0 → 100644
read_verilog ../top.v
hierarchy -libdir libdir -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_nokeep_asserts.ys 0 → 100644
read_verilog ../top.v
hierarchy -nokeep_asserts -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_purge_lib.ys 0 → 100644
read_verilog ../top.v
hierarchy -purge_lib -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_simcheck.ys 0 → 100644
read_verilog ../top.v
hierarchy -simcheck -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_top.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
synth -top top
write_verilog synth.v
simple/scripts/memory_memx.ys 0 → 100644
read_verilog ../top.v
memory_memx
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_nordff.ys 0 → 100644
read_verilog ../top.v
memory_collect
memory_nordff
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/memory_unpack.ys 0 → 100644
read_verilog ../top.v
memory_collect
memory_memx
memory_unpack
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple/scripts/mux.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover
write_verilog synth.v
simple/scripts/muxcover.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover
write_verilog synth.v
simple/scripts/muxcover_4_8_16_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux4 -mux8 -mux16 -nodecode
write_verilog synth.v
simple/scripts/muxcover_mux16.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux16
write_verilog synth.v
simple/scripts/muxcover_mux16_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux16 -nodecode
write_verilog synth.v
simple/scripts/muxcover_mux4.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux4
write_verilog synth.v
simple/scripts/muxcover_mux4_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux4 -nodecode
write_verilog synth.v
simple/scripts/muxcover_mux8.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux8
write_verilog synth.v
simple/scripts/muxcover_mux8_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux8 -nodecode
write_verilog synth.v
simple/scripts/muxcover_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -nodecode
write_verilog synth.v
simple/scripts/nlutmap.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 2:5
nlutmap
write_verilog synth.v
simple/scripts/nlutmap_assert.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 4
nlutmap -luts 10,20,30,40 -assert
write_verilog synth.v
simple/scripts/nlutmap_luts.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 4
nlutmap -luts 10,20,30,40
write_verilog synth.v
simple/scripts/reduce.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_reduce
synth -top top
write_verilog synth.v
simple/scripts/reduce_allow_off_chain.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_reduce -allow-off-chain
synth -top top
write_verilog synth.v
simple/scripts/uniquify.ys 0 → 100644
read_verilog ../top.v
synth -top top
uniquify
write_verilog synth.v
simple/scripts/zinit.ys 0 → 100644
read_verilog ../top.v
synth -top top
zinit
write_verilog synth.v
simple/scripts/zinit_singleton.ys 0 → 100644
read_verilog ../top.v
synth -top top
zinit -singleton
write_verilog synth.v
simple/uniquify/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/uniquify/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 1'bZ;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 1;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/zinit/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/zinit/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 1'bZ;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 1;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
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