Commit f708126e by Miodrag Milanovic

Fix misc tests

parent 08feab0a
......@@ -2,4 +2,4 @@ read_verilog ../top_mux.v
proc
synth -top top
abc
select -assert-count 104 t:$_MUX_
select -assert-count 109 t:$_MUX_
read_verilog ../top_mux.v
synth -top top
abc -mux4
select -assert-count 61 t:$_MUX4_
select -assert-count 60 t:$_MUX4_
......@@ -2,5 +2,5 @@ read_verilog ../top_mux.v
synth -top top
tee -o result.out abc -g cmos3
abc -g cmos3
select -assert-count 153 t:$_AOI3_
select -assert-count 168 t:$_OAI3_
select -assert-count 121 t:$_AOI3_
select -assert-count 163 t:$_OAI3_
......@@ -3,7 +3,7 @@ synth -top top
tee -o result.out abc -g cmos4
abc -g cmos4
select -assert-count 80 t:$_AOI3_
select -assert-count 21 t:$_AOI4_
select -assert-count 118 t:$_OAI3_
select -assert-count 46 t:$_OAI4_
select -assert-count 90 t:$_AOI3_
select -assert-count 17 t:$_AOI4_
select -assert-count 132 t:$_OAI3_
select -assert-count 37 t:$_OAI4_
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