Unverified Commit f53c39cf by Eddie Hung Committed by GitHub

Revert "Revert "Make bigsim more bigly again""

parent 6e8adfbf
......@@ -2,13 +2,28 @@
/.start
/*_cmos.status
/*_ice40.status
/*_ice40_abc9.status
/*_falsify.status
/*_sim.status
/*_ecp5.status
/*_ecp5_abc9.status
/*_xilinx.status
/*_xilinx_abc9.status
/*/work_sim
/*/work_cmos
/*/work_ice40
/*/work_ice40_abc9
/*/work_falsify
/*/work_ecp5
/*/work_ecp5_abc9
/*/work_xilinx
/*/work_xilinx_abc9
/*/.stamp_sim
/*/.stamp_cmos
/*/.stamp_ice40
/*/.stamp_ice40_abc9
/*/.stamp_falsify
/*/.stamp_ecp5
/*/.stamp_ecp5_abc9
/*/.stamp_xilinx
/*/.stamp_xilinx_abc9
......@@ -15,19 +15,16 @@ $(1)/.stamp_falsify: $(1)/.stamp_sim
bash run.sh $(1) falsify
touch $$@
$(1)/.stamp_cmos: $(1)/.stamp_sim
bash run.sh $(1) cmos
touch $$@
$(1)/.stamp_ice40: $(1)/.stamp_sim
bash run.sh $(1) ice40
$(1)/.stamp_%: $(1)/.stamp_sim
bash run.sh $(1) $$*
touch $$@
clean::
rm -rf $(1)/.stamp_* $(1)/work_*
rm -f $(1)_cmos.status $(1)_ice40.status $(1)_falsify.status
rm -f $(1)_{cmos,ice40,falsify,ecp5,xilinx}{,_abc9}.status
endef
$(eval $(call template,navre,cmos ice40))
$(eval $(call template,navre,cmos ice40 ice40_abc9 ecp5 ecp5_abc9 xilinx xilinx_abc9))
$(eval $(call template,picorv32,cmos ice40 ice40_abc9 ecp5 ecp5_abc9 xilinx xilinx_abc9))
.PHONY: all clean
PicoRV32 - A Size-Optimized RISC-V CPU
https://github.com/cliffordwolf/picorv32
https://github.com/cliffordwolf/picorv32/tree/d046cbfa4986acb50ef6b6e5ff58e9cab543980b
TOP="picorv32_axi"
RTL="picorv32.v"
SIM="testbench.v"
BUGMACRO="PICORV32_TESTBUG_001"
PRESYN="chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi"
if [ "$2" == "sim" ]; then
SIMARGS="-DCOMPRESSED_ISA=1"
else
SIMARGS="-DSYNTH_TEST"
fi
PLUSARGS="+firmware=../sim/firmware.hex"
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -2,12 +2,12 @@
set -x
source $1/config
mkdir $1/work_$2
mkdir -p $1/work_$2
cd $1/work_$2
touch .start
iverilog_cmd="iverilog -o sim -s testbench -I../rtl -I../sim"
iverilog_cmd="iverilog -o sim -s testbench -I../rtl -I../sim $SIMARGS"
rtl_files=""
for fn in $RTL; do
......@@ -26,16 +26,36 @@ case "$2" in
iverilog_cmd="$iverilog_cmd $rtl_files"
;;
falsify)
iverilog_cmd="$iverilog_cmd -DBUG $rtl_files"
iverilog_cmd="$iverilog_cmd -D${BUGMACRO:-BUG} $rtl_files"
;;
cmos)
yosys -ql synthlog.txt -p "synth -top $TOP; abc -g cmos4; write_verilog synth.v" $rtl_files
yosys -ql synthlog.txt -p "$PRESYN; synth -top $TOP; abc -g cmos4; write_verilog synth.v" $rtl_files
iverilog_cmd="$iverilog_cmd synth.v"
;;
ice40)
yosys -ql synthlog.txt -p "synth_ice40 -top $TOP; write_verilog synth.v" $rtl_files
yosys -ql synthlog.txt -p "$PRESYN; synth_ice40 -top $TOP; write_verilog synth.v" $rtl_files
iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ice40/cells_sim.v"
;;
ice40_abc9)
yosys -ql synthlog.txt -p "$PRESYN; synth_ice40 -abc9 -top $TOP; write_verilog synth.v" $rtl_files
iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ice40/cells_sim.v"
;;
ecp5)
yosys -ql synthlog.txt -p "$PRESYN; synth_ecp5 -top $TOP; write_verilog synth.v" $rtl_files
iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ecp5/cells_sim.v"
;;
ecp5_abc9)
yosys -ql synthlog.txt -p "$PRESYN; synth_ecp5 -abc9 -top $TOP; write_verilog synth.v" $rtl_files
iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ecp5/cells_sim.v"
;;
xilinx)
yosys -ql synthlog.txt -p "$PRESYN; synth_xilinx -top $TOP; write_verilog synth.v" $rtl_files
iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
;;
xilinx_abc9)
yosys -ql synthlog.txt -p "$PRESYN; synth_xilinx -abc9 -top $TOP; write_verilog synth.v" $rtl_files
iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
;;
*)
exit 1
;;
......@@ -46,16 +66,15 @@ for fn in $SIM; do
done
$iverilog_cmd
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
vvp -N sim | pv -l > output.txt
vvp -N sim $PLUSARGS | pv -l > output.txt
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if [ "$2" = "falsify" ]; then
......
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