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lvzhengyang
yosys-tests
Commits
f3f90a5c
Commit
f3f90a5c
authored
Aug 07, 2019
by
Eddie Hung
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Tighten area bounds
parent
d6f9941d
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architecture/synth_ice40_dsp/assert_area.py
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architecture/synth_ice40_dsp/assert_area.py
View file @
f3f90a5c
...
@@ -25,9 +25,9 @@ for fn in glob.glob('*.v'):
...
@@ -25,9 +25,9 @@ for fn in glob.glob('*.v'):
count_DFF
+=
A
%
16
+
B
%
16
count_DFF
+=
A
%
16
+
B
%
16
else
:
else
:
# TODO: Tighter bounds on count_DFF
# TODO: Tighter bounds on count_DFF
if
Areg
or
Breg
and
(
A
%
16
==
1
or
B
%
16
==
1
):
if
(
Areg
or
Breg
)
and
(
A
%
16
==
1
or
B
%
16
==
1
):
count_DFF
+=
A
+
B
count_DFF
+=
A
+
B
if
Preg
:
if
Preg
and
(
A
>
16
or
B
>
16
)
:
count_DFF
+=
A
+
B
count_DFF
+=
A
+
B
# TODO: Assert on number of SB_CARRY and SB_LUT too
# TODO: Assert on number of SB_CARRY and SB_LUT too
...
...
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