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yosys-tests
Commit ec58e672 by Miodrag Milanovic
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Revert "clock buffering is no default anymore" 

This reverts commit 2ba32455.
parent 2ba32455
Showing with 42 additions and 24 deletions
architecture/synth_sf2/synth_sf2.ys
...@@ -9,6 +9,7 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,6 +9,7 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
...@@ -24,6 +25,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,6 +25,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
......
architecture/synth_sf2/synth_sf2_clkbuf.ys
...@@ -5,28 +5,28 @@ hierarchy -top dff ...@@ -5,28 +5,28 @@ hierarchy -top dff
proc proc
#-assert option was skipped because of unproven cells #-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check #equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKBUF select -assert-count 1 t:CLKINT
select -assert-count 1 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CLKBUF t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
proc proc
#-assert option was skipped because of unproven cells #-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check #equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKBUF select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKBUF t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_edif.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_json.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_noflatten.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_noiobs.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_retime.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_run.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_top.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_vlog.ys
...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check ...@@ -9,10 +9,11 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read design -load read
hierarchy -top dffe hierarchy -top dffe
...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p ...@@ -24,7 +25,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module cd dffe # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:CFG3 select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
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