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lvzhengyang
yosys-tests
Commits
ea8a42ef
Commit
ea8a42ef
authored
Feb 10, 2020
by
Miodrag Milanovic
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Plain Diff
Made bigsim appear same as other tests
parent
8501c415
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3 changed files
with
32 additions
and
55 deletions
+32
-55
bigsim/.gitignore
+2
-29
bigsim/Makefile
+24
-20
bigsim/run.sh
+6
-6
No files found.
bigsim/.gitignore
View file @
ea8a42ef
/.stamp
/.start
/*_cmos.status
/*_ice40.status
/*_ice40_abc9.status
/*_falsify.status
/*_sim.status
/*_ecp5.status
/*_ecp5_abc9.status
/*_xilinx.status
/*_xilinx_abc9.status
/*/work_sim
/*/work_cmos
/*/work_ice40
/*/work_ice40_abc9
/*/work_falsify
/*/work_ecp5
/*/work_ecp5_abc9
/*/work_xilinx
/*/work_xilinx_abc9
/*/.stamp_sim
/*/.stamp_cmos
/*/.stamp_ice40
/*/.stamp_ice40_abc9
/*/.stamp_falsify
/*/.stamp_ecp5
/*/.stamp_ecp5_abc9
/*/.stamp_xilinx
/*/.stamp_xilinx_abc9
/*/work_*
bigsim/Makefile
View file @
ea8a42ef
all
:
work
touch .stamp
clean
::
rm
-f
.stamp
define
template
work
::
$(addprefix $(1)/.stamp_
,
sim falsify $(2))
$(1)/.stamp_sim
:
bash run.sh
$
(
1
)
sim
touch
$$
@
$(1)/.stamp_falsify
:
$(1)/.stamp_sim
bash run.sh
$
(
1
)
falsify
touch
$$
@
$(1)/.stamp_%
:
$(1)/.stamp_sim
bash run.sh
$
(
1
)
$$
*
touch
$$
@
$(foreach
design,$(1),
all
::
$(design)/work_sim/.stamp
$(design)/work_sim/.stamp
:
@
echo
'Running
$(design)
/sim..'
@
bash run.sh
$(design)
sim
clean
::
@
echo
'Cleaning
$(design)
/sim..'
@
rm
-rf
$(design)
/work_sim
all
::
$(design)/work_falsify/.stamp
$(design)/work_falsify/.stamp
:
@
echo
'Running
$(design)
/falsify..'
@
bash run.sh
$(design)
falsify
clean
::
rm
-rf
$
(
1
)
/.stamp_
*
$
(
1
)
/work_
*
rm
-f
$
(
1
)
_
{
cmos,ice40,falsify,ecp5,xilinx
}{
,_retime,_abc9,_abc9_dff
}
.status
@
echo
'Cleaning
$(design)
/falsify..'
@
rm
-rf
$(design)
/work_falsify
$(foreach
script,$(2),
all
::
$(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp
:
$(design)/work_sim/.stamp
@
echo
'Running
$(design)
/
$(script)
..'
@
bash run.sh
$(design)
$(script)
clean
::
@
echo
'Cleaning
$(design)
/
$(script)
..'
@
rm
-rf
$(design)
/work_
$(script)
))
endef
$(eval
$(call
template,navre,cmos
ice40
ice40_retime
ice40_abc9
ecp5
ecp5_retime
ecp5_abc9
xilinx
xilinx_retime
xilinx_abc9
xilinx_abc9_dff))
ifeq
($(ENABLE_HEAVY_TESTS),1)
$(eval
$(call
template,picorv32,cmos
ice40
ice40_retime
ice40_abc9
ecp5
ecp5_retime
ecp5_abc9
xilinx
xilinx_retime
xilinx_abc9
xilinx_abc9_dff))
...
...
bigsim/run.sh
View file @
ea8a42ef
...
...
@@ -22,7 +22,6 @@ fi
case
"
$2
"
in
sim
)
touch ../../.start
iverilog_cmd
=
"
$iverilog_cmd
$rtl_files
"
;;
falsify
)
...
...
@@ -95,16 +94,17 @@ fi
if
[
"
$2
"
=
"falsify"
]
;
then
if
cmp output.txt ../work_sim/output.txt
;
then
echo
FAIL
>
../../
${
1
}
_
${
2
}
.status
echo
FAIL
>
${
1
}
_
${
2
}
.status
else
echo
PASS
>
../../
${
1
}
_
${
2
}
.status
echo
PASS
>
${
1
}
_
${
2
}
.status
fi
elif
[
"
$2
"
!=
"sim"
]
;
then
if
cmp output.txt ../work_sim/output.txt
;
then
echo
PASS
>
../../
${
1
}
_
${
2
}
.status
echo
PASS
>
${
1
}
_
${
2
}
.status
else
echo
FAIL
>
../../
${
1
}
_
${
2
}
.status
echo
FAIL
>
${
1
}
_
${
2
}
.status
fi
elif
[
"
$2
"
==
"sim"
]
;
then
echo
PASS
>
../../
${
1
}
_
${
2
}
.status
echo
PASS
>
${
1
}
_
${
2
}
.status
fi
touch .stamp
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