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Unverified Commit e5dabce1 by Miodrag Milanović Committed by GitHub
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Merge pull request #44 from YosysHQ/xc7srl_cleanup 

Cleanup xc7srl tests by using YosysHQ/yosys#1150
parents 728b8cc6 729cdfd9
Showing with 274 additions and 36 deletions
architecture/synth_xilinx_srl/generate.py
#!/usr/bin/python3
import re, glob
N = 131
def assert_static_area(fp, i, name):
if i < 3:
srl32,srl16,fd = (0,0,i)
else:
srl32 = i // 32
if (i % 32) == 0:
srl16 = 0
fd = 0
elif (i % 32) == 1:
srl16 = 0
fd = 1
elif (i % 32) <= 17:
srl16 = 1
fd = (i % 32) - 16
else:
srl32 += 1
srl16 = 0
fd = 0
fp.write('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; cd {3}_{4}; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
'''.format(fd, srl16, srl32, name, i))
def assert_dynamic_area(fp, i, name):
if i < 3:
srl32,srl16,fd = (0,0,i)
lut3 = 1 if i > 1 else 0
lut5 = 0
else:
srl32 = i // 32
if (i % 128) == 0 or (i % 32) == 0:
srl16 = 0
fd = 0
elif (i % 128) == 1:
srl16 = 0
fd = 1
elif (i % 32) <= 16:
srl16 = 1
fd = 0
else:
srl32 += 1
srl16 = 0
fd = 0
lut3 = 1 if i > 128 and i < 257 else 0
lut5 = 1 if i > 256 else 0
muxf8 = (srl32+srl16) // 4
if ((srl32 + srl16) % 4) == 0:
muxf7 = muxf8 * 2
elif ((srl32 + srl16) % 4) == 3:
muxf8 += 1
muxf7 = muxf8 * 2
else:
muxf7 = (srl32+srl16) // 2
fp.write('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; select t:MUXF7 -assert-count {3}; select t:MUXF8 -assert-count {4}; select t:LUT3 -assert-count {5}; select t:LUT5 -assert-count {6}; cd {7}_{8}; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT3 t:LUT5 %% %n t:* %i -assert-none";
endmodule
`endif
'''.format(fd, srl16, srl32, muxf7, muxf8, lut3, lut5, name, i))
# Test 1: pos_clk_no_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test1_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test1_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -20,11 +87,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test1')
# Test 2: pos_clk_with_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test2_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test2_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -39,11 +108,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test2')
# Test 3: pos_clk_with_enable_with_init_inferred
for i in range(1,N+1):
with open('test3_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test3_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -65,11 +136,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test3')
# Test 4: neg_clk_no_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test4_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test4_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -84,11 +157,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test4')
# Test 5: neg_clk_no_enable_no_init_inferred
for i in range(1,N+1):
with open('test5_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test5_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -107,11 +182,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test5')
# Test 6: neg_clk_with_enable_with_init_inferred
for i in range(1,N+1):
with open('test6_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test6_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -133,11 +210,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test6')
# Test 10: pos_clk_no_enable_no_init_not_inferred_var_len
for i in range(1,N+1):
with open('test10_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test10_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -154,11 +233,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_dynamic_area(fp, i, 'test10')
# Test 11: neg_clk_with_enable_with_init_inferred_var_len
for i in range(1,N+1):
with open('test11_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test11_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -180,11 +261,30 @@ generate
endgenerate
endmodule
'''.format(i))
assert_dynamic_area(fp, i, 'test11')
import lfsr_area
re_lfsr = re.compile(r'lfsr_(\d+)\.v')
for fn in glob.glob('lfsr_*.v'):
m = re_lfsr.match(fn)
if not m: continue
W = int(m.group(1))
with open(fn, 'a') as f:
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "%s";
endmodule
`endif
''' % lfsr_area.area[W], file=f)
# Test 15: pos_clk_no_enable_no_init_not_inferred
for i in range(128+1,128+N+1):
with open('test15_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test15_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -199,11 +299,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test15')
# Test 16: neg_clk_with_enable_with_init_inferred_var_len
for i in range(128+1,128+N+1):
with open('test16_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test16_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -225,11 +327,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_dynamic_area(fp, i, 'test16')
# Test 18: neg_clk_with_enable_with_init_inferred2
for i in range(1,N+1):
with open('test18_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test18_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
......@@ -237,7 +341,7 @@ generate
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
//initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(negedge clk) if (e) int[d][w] <= i[w];
......@@ -250,11 +354,13 @@ generate
assign q = int[depth-1];
endgenerate
endmodule'''.format(i))
assert_static_area(fp, i, 'test18')
# Test 19: pos_clk_with_enable_no_init_inferred2_var_len
for i in range(1,N+1):
with open('test19_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test19_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
......@@ -275,3 +381,4 @@ generate
assign q = int[l];
endgenerate
endmodule'''.format(i))
assert_dynamic_area(fp, i, 'test19')
architecture/synth_xilinx_srl/run-test.sh
#!/bin/bash
set -e
shopt -s extglob
OPTIND=1
......@@ -22,10 +23,19 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm
python3 generate_lfsr.py
python3 ../generate.py
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx -retime' -l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../*.ys .
for ys in *.ys; do
yosys -q $ys
done
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx -retime; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
architecture/synth_xilinx_srl/test13.ys deleted 100644 → 0
# Check that non chain users block SRLs
design -reset; read_verilog test13a.out/test13a_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13b.out/test13b_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13c.out/test13c_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13d.out/test13d_syn0.v; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test13a.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_port
(* top *)
module test13a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
......@@ -15,3 +16,9 @@ generate
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13a; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test13b.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_port
(* top *)
module test13b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
......@@ -22,3 +23,9 @@ generate
assign state = int[0];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13b; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test13c.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_xor
(* top *)
module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
......@@ -15,3 +16,9 @@ generate
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13c; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test13d.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_xor
module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
(* top *)
module test13d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
......@@ -22,3 +23,9 @@ generate
assign state = {depth{^int[0]}};
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13d; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test17.ys deleted 100644 → 0
design -reset; read_verilog test17a.out/test17a_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17b.out/test17b_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17c.out/test17c_syn0.v; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17d.out/test17d_syn0.v; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;
design -reset; read_verilog test17e.out/test17e_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
architecture/synth_xilinx_srl/test17a.v
// Check inference even when not in vector
(* top *)
module test17a (input clk, input i, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
......@@ -13,3 +14,9 @@ generate
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17a; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17b.v
// Check inference even when not in vector
module test17a (input clk, input i, input e, output q);
(* top *)
module test17b (input clk, input i, input e, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17b; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17c.v
// Check inference even when keep attribute specified
(* top *)
module test17c (input clk, input i, input e, output q);
generate
reg a1, a2, a3;
......@@ -8,3 +9,9 @@ generate
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17c; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17d.v
// Check inference even when keep attribute specified
(* top *)
module test17d (input clk, input i, input e, output q);
generate
reg a1, a2;
......@@ -9,3 +10,9 @@ generate
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17d; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17e.v
// Check inference even when keep attribute specified
module test17d (input clk, input i, input e, output q);
(* top *)
module test17e (input clk, input i, input e, output q);
generate
reg a1, a2;
(* blah *) reg a3;
......@@ -11,3 +12,9 @@ generate
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17e; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test20.v
(* top *)
module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
......@@ -18,3 +19,9 @@ generate
assign z = int[depth-1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test20; select t:FD* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test20.ys deleted 100644 → 0
design -reset; read_verilog test20.out/test20_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test21.ys deleted 100644 → 0
# Check that retiming does not infer shift registers
design -reset; read_verilog test21a.out/test21a_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
design -reset; read_verilog test21b.out/test21b_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
architecture/synth_xilinx_srl/test21a.v
(* top *)
module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
genvar d;
wire [depth:0] int;
......@@ -9,3 +10,9 @@ module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i,
endgenerate
assign q = int[depth];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21a; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture/synth_xilinx_srl/test21b.v
(* top *)
module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
reg [depth-1:0] int;
......@@ -14,3 +15,9 @@ module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i,
assign q = int[depth-1];
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21b; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture/synth_xilinx_srl/test7.ys deleted 100644 → 0
# Check that shift registers with resets are not inferred into SRLs
design -reset; read_verilog test7a.out/test7a_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7b.out/test7b_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7c.out/test7c_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7d.out/test7d_syn0.v; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test7a.v
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset
(* top *)
module test7a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -13,3 +14,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7a; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test7b.v
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset
(* top *)
module test7b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -20,3 +21,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7b; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test7c.v
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
(* top *)
module test7c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -15,3 +16,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7c; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test7d.v
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
(* top *)
module test7d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -20,3 +21,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7d; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test8.v
// Check multi-bit works
// pos_clk_no_enable_no_init_not_inferred_N_width
(* top *)
module test8 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -13,3 +14,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test8; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test8.ys deleted 100644 → 0
# Check that wide shift registers are not a problem
read_verilog test8.out/test8_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test9.v
// Check multi-bit works
// neg_clk_no_enable_with_init_with_inferred_N_width
(* top *)
module test9 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -20,3 +21,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test9; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test9.ys deleted 100644 → 0
read_verilog test9.out/test9_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/ug901.ys deleted 100644 → 0
design -reset; read_verilog ug901a.out/ug901a_syn0.v; select t:SRLC32E -assert-count 1
design -reset; read_verilog ug901b.out/ug901b_syn0.v; select t:SRLC32E -assert-count 1
design -reset; read_verilog ug901c.out/ug901c_syn0.v; select t:SRLC32E -assert-count 1
architecture/synth_xilinx_srl/ug901a.v
......@@ -5,6 +5,7 @@
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
(* top *)
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
......@@ -17,3 +18,9 @@ begin
end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_0; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/ug901b.v
......@@ -5,6 +5,7 @@
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
(* top *)
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
......@@ -23,3 +24,8 @@ end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/ug901c.v
......@@ -3,6 +3,7 @@
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
(* top *)
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
......@@ -17,3 +18,9 @@ always @(posedge CLK)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd dynamic_shift_register_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
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