Fixed some regressed tests

regression/issue_00084/top.v

@@ -6,7 +6,13 @@ input ce;
 output reg [7:0] q;
 
 reg [7:0] ram[1023:0];
+integer j;
 
+// memory not created if there is no initial content
+initial 
+for(j = 0; j < 256; j = j+1) 
+    ram[j] = 8'h00;
+    
 always @(posedge clk)
 begin
     if (ce)

regression/issue_00623/issue_00623.ys

@@ -2,4 +2,6 @@ read_verilog ../top.v
 tribuf -logic
 synth -top bidirtest
 iopadmap -bits -inpad IBUF O:PAD -outpad OBUF I:PAD -tinoutpad IOBUF ENA:O:I:PAD bidirtest
-select -assert-count 0 t:IOBUF
+select -assert-count 1 t:IOBUF
+select -assert-count 2 t:IBUF
+select -assert-count 1 t:OBUF

regression/issue_00705/top.v

@@ -5,6 +5,12 @@ module top(
     );
 
     reg [7:0] rom_data[0:255];
+    integer j;
+
+    // memory not created if there is no initial content
+    initial 
+    for(j = 0; j < 256; j = j+1) 
+        rom_data[j] = 8'h00;
 
     always @(posedge clk)
         dbr <= rom_data[addr];