Fix test17

architecture/synth_xilinx_srl/test17.ys

-read_verilog -icells -DTEST17 ../top.v
-synth_xilinx -top top
-rename -top synth
-clean -purge
-write_verilog -norename synth17.v
-
-select t:SRL16E %x:+[Q] w:infer1* %i -assert-count 1; select t:FD* %x:+[Q] w:infer1* %i -assert-count 0
-select t:SRL16E %x:+[Q] w:infer2* %i -assert-count 1; select t:FD* %x:+[Q] w:infer2* %i -assert-count 0
-
-select t:SRL16E %x:+[Q] w:keep1* %i -assert-count 2; select t:SRL16E %x:+[Q] w:keep1.a4 %i -assert-count 1; select t:FD* %x:+[Q] w:*keep1* %i -assert-count 0
-select t:SRL16E %x:+[Q] w:keep2* %i -assert-count 2; select t:SRL16E %x:+[Q] w:keep2.a3 %i -assert-count 1; select t:FD* %x:+[Q] w:*keep2.a4* %i -assert-count 1; 
-select t:SRL16E %x:+[Q] w:attr* %i -assert-count 1; select t:FD* %x:+[Q] w:attr* %i -assert-count 0
+design -reset; read_verilog test17a.out/test17a_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
+design -reset; read_verilog test17b.out/test17b_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
+design -reset; read_verilog test17c.out/test17c_syn0.v; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;
+design -reset; read_verilog test17d.out/test17d_syn0.v; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;
+design -reset; read_verilog test17e.out/test17e_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;

architecture/synth_xilinx_srl/test17c.v

@@ -5,6 +5,6 @@ generate
     (* keep *) reg a4;
     reg a5, a6, a7, a8;
     always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
-    assign z = a8;
+    assign q = a8;
 endgenerate
 endmodule