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lvzhengyang
yosys-tests
Commits
d6f9941d
Commit
d6f9941d
authored
Aug 07, 2019
by
Eddie Hung
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Add two (* keep *) tests
parent
33fdefa5
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+59
-0
architecture/synth_ice40_dsp/mul_16_16_keepABP_.v
+29
-0
architecture/synth_ice40_dsp/mul_32_32_keepB_.v
+29
-0
architecture/synth_ice40_dsp/run-test.sh
+1
-0
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architecture/synth_ice40_dsp/mul_16_16_keepABP_.v
0 → 100644
View file @
d6f9941d
(
*
top
*
)
module
mul_16_16_keepABP_
#(
parameter
AW
=
16
,
BW
=
16
,
AREG
=
1
,
BREG
=
1
,
PREG
=
1
)
(
input
clk
,
CEA
,
CEB
,
CEP
,
input
[
AW
-
1
:
0
]
A
,
input
[
BW
-
1
:
0
]
B
,
(
*
keep
*
)
output
reg
[
AW
+
BW
-
1
:
0
]
P
)
;
(
*
keep
*
)
reg
[
AW
-
1
:
0
]
Ar
;
(
*
keep
*
)
reg
[
BW
-
1
:
0
]
Br
;
generate
if
(
AREG
)
begin
always
@
(
posedge
clk
)
if
(
1
)
Ar
<=
A
;
end
else
always
@*
Ar
<=
A
;
if
(
BREG
)
begin
always
@
(
posedge
clk
)
if
(
1
)
Br
<=
B
;
end
else
always
@*
Br
<=
B
;
if
(
PREG
)
begin
always
@
(
posedge
clk
)
if
(
1
)
P
<=
Ar
*
Br
;
end
else
always
@*
P
<=
Ar
*
Br
;
endgenerate
endmodule
`ifndef
_
AUTOTB
module
__
test
;
wire
[
4095
:
0
]
assert_area
=
"cd mul_16_16_keepABP_; select t:SB_MAC16 -assert-count 1; select t:SB_DFF* -assert-count 64"
;
endmodule
`endif
architecture/synth_ice40_dsp/mul_32_32_keepB_.v
0 → 100644
View file @
d6f9941d
(
*
top
*
)
module
mul_32_32_keepB_
#(
parameter
AW
=
32
,
BW
=
32
,
AREG
=
1
,
BREG
=
1
,
PREG
=
0
)
(
input
clk
,
CEA
,
CEB
,
CEP
,
input
[
AW
-
1
:
0
]
A
,
input
[
BW
-
1
:
0
]
B
,
output
reg
[
AW
+
BW
-
1
:
0
]
P
)
;
reg
[
AW
-
1
:
0
]
Ar
;
(
*
keep
*
)
reg
[
BW
-
1
:
0
]
Br
;
generate
if
(
AREG
)
begin
always
@
(
posedge
clk
)
if
(
1
)
Ar
<=
A
;
end
else
always
@*
Ar
<=
A
;
if
(
BREG
)
begin
always
@
(
posedge
clk
)
if
(
1
)
Br
<=
B
;
end
else
always
@*
Br
<=
B
;
if
(
PREG
)
begin
always
@
(
posedge
clk
)
if
(
1
)
P
<=
Ar
*
Br
;
end
else
always
@*
P
<=
Ar
*
Br
;
endgenerate
endmodule
`ifndef
_
AUTOTB
module
__
test
;
wire
[
4095
:
0
]
assert_area
=
"cd mul_32_32_keepB_; select t:SB_MAC16 -assert-count 4; select t:SB_DFF* -assert-count 32"
;
endmodule
`endif
architecture/synth_ice40_dsp/run-test.sh
View file @
d6f9941d
...
@@ -22,6 +22,7 @@ fi
...
@@ -22,6 +22,7 @@ fi
cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
PYTHONPATH
=
".:
$PYTHONPATH
"
python3 ../generate_mul.py
PYTHONPATH
=
".:
$PYTHONPATH
"
python3 ../generate_mul.py
python3 ../assert_area.py
python3 ../assert_area.py
cp ../
*
.v
.
${
MAKE
:-
make
}
-f
../../../../tools/autotest.mk
$seed
*
.v
EXTRA_FLAGS
=
"
\
${
MAKE
:-
make
}
-f
../../../../tools/autotest.mk
$seed
*
.v
EXTRA_FLAGS
=
"
\
-p 'design -copy-to __test __test;
\
-p 'design -copy-to __test __test;
\
synth_ice40 -dsp;
\
synth_ice40 -dsp;
\
...
...
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