More testing

architecture/synth_ice40_dsp/assert_area.py

@@ -29,7 +29,10 @@ for fn in glob.glob('*.v'):
             count_DFF += A + B
     if Preg and (A > 16 or B > 16):
         count_DFF += A + B
-    # TODO: Assert on number of SB_CARRY and SB_LUT too
+    # TODO: More assert on number of CARRY and LUTs
+    count_CARRY = ''
+    if A <= 16 or B <= 16:
+        count_CARRY = '; select t:SB_CARRY -assert-none; select t:SB_LUT -assert-none';
 
     bn,_ = os.path.splitext(fn)
 

architecture/synth_xilinx_dsp/assert_area.py

@@ -32,9 +32,12 @@ for fn in glob.glob('*.v'):
         Y = (B+16) // 17
     count_MAC = X * Y
     count_DFF = 0
-    if Preg:
+    if Preg and (A > 25 or B > 18):
         count_DFF += A + B
-    # TODO: Assert on number of CARRY4s too
+    # TODO: More assert on number of CARRY and LUTs
+    count_CARRY = ''
+    if A <= 25 or B <= 18:
+        count_CARRY = '; select t:XORCY -assert-none; select t:LUT* -assert-none';
 
     bn,_ = os.path.splitext(fn)
 
@@ -42,8 +45,7 @@ for fn in glob.glob('*.v'):
         print('''
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd {0}; select t:DSP48E1 -assert-count {1}; select t:FD* -assert-max {2}";
-    // {3} {4} {5} {6} X={7} Y={8}
+    wire [4095:0] assert_area = "cd {0}; select t:DSP48E1 -assert-count {1}; select t:FD* -assert-max {2}{3}";
 endmodule
 `endif
-'''.format(os.path.splitext(fn)[0], count_MAC, count_DFF, A,B,Asigned,Bsigned,X,Y), file=f)
+'''.format(os.path.splitext(fn)[0], count_MAC, count_DFF, count_CARRY), file=f)

architecture/synth_xilinx_dsp/generate_mul.py

+#!/usr/bin/env python3
+
+from common_mul import gen_mul
+
+ARange = ['17','17s','18','18s','19','19s','24','24s','25','25s','36','36s','49','49s','50','50s','75','75s']
+BRange = ['17','17s','18','18s','19','19s','27','27s','34','34s','35','35s','36','36s']
+
+if __name__ == "__main__":
+    gen_mul(ARange, BRange)