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yosys-tests
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lvzhengyang
yosys-tests
Commits
d5557a24
Commit
d5557a24
authored
May 04, 2019
by
Miodrag Milanovic
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fix run script
parent
9afdd641
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1 changed file
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9 additions
and
1 deletions
+9
-1
bigsim/run.sh
+9
-1
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bigsim/run.sh
View file @
d5557a24
...
@@ -14,6 +14,12 @@ for fn in $RTL; do
...
@@ -14,6 +14,12 @@ for fn in $RTL; do
rtl_files
=
"
$rtl_files
../rtl/
$fn
"
rtl_files
=
"
$rtl_files
../rtl/
$fn
"
done
done
if
[
-f
"../../../../../techlibs/common/simcells.v"
]
;
then
TECHLIBS_PREFIX
=
../../../../../techlibs
else
TECHLIBS_PREFIX
=
/usr/local/share/yosys
fi
case
"
$2
"
in
case
"
$2
"
in
sim
)
sim
)
touch ../../.start
touch ../../.start
...
@@ -28,7 +34,7 @@ case "$2" in
...
@@ -28,7 +34,7 @@ case "$2" in
;;
;;
ice40
)
ice40
)
yosys
-ql
synthlog.txt
-p
"synth_ice40 -top
$TOP
; write_verilog synth.v"
$rtl_files
yosys
-ql
synthlog.txt
-p
"synth_ice40 -top
$TOP
; write_verilog synth.v"
$rtl_files
iverilog_cmd
=
"
$iverilog_cmd
synth.v
$
(
yosys-config
--datdir
/ice40/cells_sim.v
)
"
iverilog_cmd
=
"
$iverilog_cmd
synth.v
$
TECHLIBS_PREFIX
/ice40/cells_sim.v
"
;;
;;
*
)
*
)
exit
1
exit
1
...
@@ -64,4 +70,6 @@ elif [ "$2" != "sim" ]; then
...
@@ -64,4 +70,6 @@ elif [ "$2" != "sim" ]; then
else
else
echo
FAIL
>
../../
${
1
}
_
${
2
}
.status
echo
FAIL
>
../../
${
1
}
_
${
2
}
.status
fi
fi
elif
[
"
$2
"
==
"sim"
]
;
then
echo
PASS
>
../../
${
1
}
_
${
2
}
.status
fi
fi
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