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lvzhengyang
yosys-tests
Commits
9afdd641
Commit
9afdd641
authored
May 04, 2019
by
Miodrag Milanovic
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fix special case
parent
753930e7
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2 changed files
with
14 additions
and
3 deletions
+14
-3
backends/common.v
+11
-0
backends/write_simplec/testbench.v
+3
-3
No files found.
backends/common.v
View file @
9afdd641
module
assert_equal
(
input
clk
,
input
test
,
input
pat
)
;
always
@
(
posedge
clk
)
begin
if
(
test
!=
pat
)
begin
$
display
(
"ERROR: ASSERTION FAILED in %m:"
,
$
time
)
;
$
stop
;
end
end
endmodule
module
assert_dff
(
input
clk
,
input
test
,
input
pat
)
;
always
@
(
posedge
clk
)
begin
...
...
backends/write_simplec/testbench.v
View file @
9afdd641
...
...
@@ -31,10 +31,10 @@ module testbench;
dinA
<=
!
dinA
;
end
assert_
dff
b_test
(
.
clk
(
en
)
,
.
test
(
dinA
)
,
.
pat
(
dioB
[
0
]))
;
assert_
equal
b_test
(
.
clk
(
en
)
,
.
test
(
dinA
)
,
.
pat
(
dioB
[
0
]))
;
assert_
dff
c_test
(
.
clk
(
en
)
,
.
test
(
dinA
)
,
.
pat
(
doutC
[
0
]))
;
assert_
equal
c_test
(
.
clk
(
en
)
,
.
test
(
dinA
)
,
.
pat
(
doutC
[
0
]))
;
assert_
dff
cz_test
(
.
clk
(
!
en
)
,
.
test
(
1
'
bZ
)
,
.
pat
(
doutC
[
0
]))
;
assert_
equal
cz_test
(
.
clk
(
!
en
)
,
.
test
(
1
'
bZ
)
,
.
pat
(
doutC
[
0
]))
;
endmodule
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