Re-enable testing dffe on ice40 DSPs

architecture/synth_ice40_dsp/assert_area.py

@@ -10,6 +10,7 @@ for fn in glob.glob('*.v'):
     m = re_mux.match(fn)
     if not m: continue
 
+    macc = False
     A,B = map(int, m.group(1,3))
     Asigned, Bsigned = m.group(2,4)
     Areg = 'A' in m.group(5)
@@ -29,6 +30,12 @@ for fn in glob.glob('*.v'):
             count_DFF += A + B
     if Preg and (A > 16 or B > 16):
         count_DFF += A + B
+        if macc:
+            count_DFF += 5 # In my testcases, accumulator is always
+                           # 5bits bigger than multiplier result
+        elif (A > 16) ^ (B > 16):
+            count_DFF -= 1 # For pure multipliers with just one big dimension,
+                           #   expect last slice to absorb at least one register
     # TODO: More assert on number of CARRY and LUTs
     count_CARRY = ''
     if (A <= 16 or B <= 16) and A % 16 != 1 and B % 16 != 1:

architecture/synth_ice40_dsp/generate_mul.py

@@ -6,4 +6,4 @@ ARange = ['16','16s','17','17s','24','24s','31','31s','32','32s','33','33s','47'
 BRange = ['15','15s','16','16s','17','17s','24','24s','31','31s','32','32s']
 
 if __name__ == "__main__":
-    gen_mul(ARange, BRange)
+    gen_mul(ARange, BRange, "ABP")

architecture/synth_ice40_dsp/mul_16_16_keepABP_.v

@@ -23,7 +23,7 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd mul_16_16_keepABP_; select t:SB_MAC16 -assert-count 1; select t:SB_DFF* -assert-count 64";
+    wire [4095:0] assert_area = "cd mul_16_16_keepABP_; select t:SB_MAC16 -assert-count 1; select t:SB_DFF* -assert-count 32";
 endmodule
 `endif