remove not valid test

architecture/synth_greenpak4/synth_greenpak4_adffsr.ys

-read_verilog ../top_dffsr.v
-design -save read
-
-hierarchy -top dffsr
-proc
-equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffsr # Constrain all select calls below inside the top module
-stat
-select -assert-count 1 t:$_DFFSR_PPP_
-select -assert-count 1 t:GP_2LUT
-select -assert-count 4 t:GP_IBUF
-select -assert-count 1 t:GP_OBUF
-select -assert-none t:$_DFFSR_PPP_ t:GP_2LUT t:GP_IBUF t:GP_OBUF %% t:* %D
-
-design -load read
-hierarchy -top ndffnsnr
-proc
-equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd ndffnsnr # Constrain all select calls below inside the top module
-stat
-select -assert-count 1 t:$_DFFSR_NPP_
-select -assert-count 1 t:GP_2LUT
-select -assert-count 4 t:GP_IBUF
-select -assert-count 1 t:GP_INV
-select -assert-count 1 t:GP_OBUF
-select -assert-none t:$_DFFSR_NPP_ t:GP_2LUT t:GP_IBUF t:GP_INV t:GP_OBUF %% t:* %D