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yosys-tests
Commit 6fd3dbda by Miodrag Milanovic
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Fix for SF2

parent 13cc6608
Showing with 0 additions and 12 deletions
architecture/synth_sf2/top.v
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
......@@ -19,9 +13,6 @@ endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
......
architecture/synth_sf2_lcov/top.v
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
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